Commit | Line | Data |
---|---|---|
7f2d50f8 | 1 | * Renesas VSP Video Processing Engine |
34d1cbda | 2 | |
7f2d50f8 | 3 | The VSP is a video processing engine that supports up-/down-scaling, alpha |
34d1cbda LP |
4 | blending, color space conversion and various other image processing features. |
5 | It can be found in the Renesas R-Car second generation SoCs. | |
6 | ||
7 | Required properties: | |
8 | ||
7f2d50f8 LP |
9 | - compatible: Must contain one of the following values |
10 | - "renesas,vsp1" for the R-Car Gen2 VSP1 | |
11 | - "renesas,vsp2" for the R-Car Gen3 VSP2 | |
34d1cbda | 12 | |
7f2d50f8 LP |
13 | - reg: Base address and length of the registers block for the VSP. |
14 | - interrupts: VSP interrupt specifier. | |
15 | - clocks: A phandle + clock-specifier pair for the VSP functional clock. | |
34d1cbda | 16 | |
94fcdf82 LP |
17 | Optional properties: |
18 | ||
19 | - renesas,fcp: A phandle referencing the FCP that handles memory accesses | |
20 | for the VSP. Not needed on Gen2, mandatory on Gen3. | |
21 | ||
34d1cbda LP |
22 | |
23 | Example: R8A7790 (R-Car H2) VSP1-S node | |
24 | ||
25 | vsp1@fe928000 { | |
26 | compatible = "renesas,vsp1"; | |
27 | reg = <0 0xfe928000 0 0x8000>; | |
28 | interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; | |
29 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; | |
34d1cbda | 30 | }; |