[linux-block.git] / Documentation / devicetree / bindings / media / fsl-pxp.txt

Freescale Pixel Pipeline
========================

The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
that supports scaling, colorspace conversion, alpha blending, rotation, and
pixel conversion via lookup table. Different versions are present on various
i.MX SoCs from i.MX23 to i.MX7.

Required properties:
- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
  imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d.
- reg: the register base and size for the device registers
- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
- clock-names: should be "axi"
- clocks: the PXP AXI clock

Example:

pxp@21cc000 {
	compatible = "fsl,imx6ull-pxp";
	reg = <0x021cc000 0x4000>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "axi";
	clocks = <&clks IMX6UL_CLK_PXP>;
};
Commit	Line	Data
b0c351b5 PZ	1	Freescale Pixel Pipeline
	2	========================
	3
	4	The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
	5	that supports scaling, colorspace conversion, alpha blending, rotation, and
	6	pixel conversion via lookup table. Different versions are present on various
	7	i.MX SoCs from i.MX23 to i.MX7.
	8
	9	Required properties:
	10	- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
031c8cd8	11	imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d.
b0c351b5 PZ	12	- reg: the register base and size for the device registers
	13	- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
	14	- clock-names: should be "axi"
	15	- clocks: the PXP AXI clock
	16
	17	Example:
	18
	19	pxp@21cc000 {
	20	compatible = "fsl,imx6ull-pxp";
	21	reg = <0x021cc000 0x4000>;
	22	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	23	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	24	clock-names = "axi";
	25	clocks = <&clks IMX6UL_CLK_PXP>;
	26	};