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1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
2 | %YAML 1.2 | |
3 | --- | |
e1056f9b | 4 | $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml# |
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5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
6 | ||
dd3cb467 | 7 | title: Allwinner A10 CMOS Sensor Interface (CSI) |
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8 | |
9 | maintainers: | |
10 | - Chen-Yu Tsai <wens@csie.org> | |
5c7404bb | 11 | - Maxime Ripard <mripard@kernel.org> |
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12 | |
13 | description: |- | |
14 | The Allwinner A10 and later has a CMOS Sensor Interface to retrieve | |
15 | frames from a parallel or BT656 sensor. | |
16 | ||
17 | properties: | |
18 | compatible: | |
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19 | oneOf: |
20 | - const: allwinner,sun4i-a10-csi1 | |
21 | - const: allwinner,sun7i-a20-csi0 | |
22 | - items: | |
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23 | - const: allwinner,sun7i-a20-csi1 |
24 | - const: allwinner,sun4i-a10-csi1 | |
7866d690 | 25 | - items: |
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26 | - const: allwinner,sun8i-r40-csi0 |
27 | - const: allwinner,sun7i-a20-csi0 | |
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28 | |
29 | reg: | |
30 | maxItems: 1 | |
31 | ||
32 | interrupts: | |
33 | maxItems: 1 | |
34 | ||
35 | clocks: | |
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36 | oneOf: |
37 | - items: | |
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38 | - description: The CSI interface clock |
39 | - description: The CSI DRAM clock | |
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40 | |
41 | - items: | |
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42 | - description: The CSI interface clock |
43 | - description: The CSI ISP clock | |
44 | - description: The CSI DRAM clock | |
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45 | |
46 | clock-names: | |
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47 | oneOf: |
48 | - items: | |
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49 | - const: bus |
50 | - const: ram | |
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51 | |
52 | - items: | |
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53 | - const: bus |
54 | - const: isp | |
55 | - const: ram | |
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56 | |
57 | resets: | |
58 | maxItems: 1 | |
59 | ||
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60 | # FIXME: This should be made required eventually once every SoC will |
61 | # have the MBUS declared. | |
62 | interconnects: | |
63 | maxItems: 1 | |
64 | ||
65 | # FIXME: This should be made required eventually once every SoC will | |
66 | # have the MBUS declared. | |
67 | interconnect-names: | |
68 | const: dma-mem | |
69 | ||
c5e8f4cc | 70 | port: |
066a94e2 | 71 | $ref: /schemas/graph.yaml#/$defs/port-base |
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72 | additionalProperties: false |
73 | ||
74 | properties: | |
75 | endpoint: | |
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76 | $ref: video-interfaces.yaml# |
77 | unevaluatedProperties: false | |
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78 | |
79 | properties: | |
80 | bus-width: | |
81 | enum: [8, 16] | |
82 | ||
83 | data-active: true | |
84 | hsync-active: true | |
85 | pclk-sample: true | |
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86 | vsync-active: true |
87 | ||
88 | required: | |
89 | - bus-width | |
90 | - data-active | |
91 | - hsync-active | |
92 | - pclk-sample | |
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93 | - vsync-active |
94 | ||
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95 | required: |
96 | - compatible | |
97 | - reg | |
98 | - interrupts | |
99 | - clocks | |
100 | ||
101 | additionalProperties: false | |
102 | ||
103 | examples: | |
104 | - | | |
105 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
106 | #include <dt-bindings/clock/sun7i-a20-ccu.h> | |
107 | #include <dt-bindings/reset/sun4i-a10-ccu.h> | |
108 | ||
109 | csi0: csi@1c09000 { | |
110 | compatible = "allwinner,sun7i-a20-csi0"; | |
111 | reg = <0x01c09000 0x1000>; | |
112 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
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113 | clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; |
114 | clock-names = "bus", "isp", "ram"; | |
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115 | resets = <&ccu RST_CSI0>; |
116 | ||
117 | port { | |
118 | csi_from_ov5640: endpoint { | |
119 | remote-endpoint = <&ov5640_to_csi>; | |
120 | bus-width = <8>; | |
121 | hsync-active = <1>; /* Active high */ | |
122 | vsync-active = <0>; /* Active low */ | |
123 | data-active = <1>; /* Active high */ | |
124 | pclk-sample = <1>; /* Rising */ | |
125 | }; | |
126 | }; | |
127 | }; | |
128 | ||
129 | ... |