projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 4a93f21d LP |
1 | * Renesas VMSA-Compatible IOMMU |
| 2 | ||
| 3 | The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables. | |
| 4 | It provides address translation for bus masters outside of the CPU, each | |
| 5 | connected to the IPMMU through a port called micro-TLB. | |
| 6 | ||
| 7 | ||
| 8 | Required Properties: | |
| 9 | ||
| d4e42e72 MD |
10 | - compatible: Must contain SoC-specific and generic entry below in case |
| 11 | the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU. | |
| 89ae54ba MD |
12 | |
| 13 | - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU. | |
| 9fe77e01 BD |
14 | - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU. |
| 15 | - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU. | |
| 89ae54ba MD |
16 | - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU. |
| 17 | - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU. | |
| 18 | - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU. | |
| 19 | - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU. | |
| d4e42e72 | 20 | - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU. |
| ca84eaeb | 21 | - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU. |
| 9327b810 SH |
22 | - "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU. |
| 23 | - "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU. | |
| 9fe77e01 BD |
24 | - "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible |
| 25 | IPMMU. | |
| 89ae54ba | 26 | |
| 4a93f21d LP |
27 | - reg: Base address and size of the IPMMU registers. |
| 28 | - interrupts: Specifiers for the MMU fault interrupts. For instances that | |
| 29 | support secure mode two interrupts must be specified, for non-secure and | |
| 30 | secure mode, in that order. For instances that don't support secure mode a | |
| d4e42e72 | 31 | single interrupt must be specified. Not required for cache IPMMUs. |
| 4a93f21d LP |
32 | |
| 33 | - #iommu-cells: Must be 1. | |
| 34 | ||
| d4e42e72 MD |
35 | Optional properties: |
| 36 | ||
| 37 | - renesas,ipmmu-main: reference to the main IPMMU instance in two cells. | |
| 38 | The first cell is a phandle to the main IPMMU and the second cell is | |
| 39 | the interrupt bit number associated with the particular cache IPMMU device. | |
| 40 | The interrupt bit number needs to match the main IPMMU IMSSTR register. | |
| 41 | Only used by cache IPMMU instances. | |
| 42 | ||
| 43 | ||
| 4a93f21d LP |
44 | Each bus master connected to an IPMMU must reference the IPMMU in its device |
| 45 | node with the following property: | |
| 46 | ||
| 47 | - iommus: A reference to the IPMMU in two cells. The first cell is a phandle | |
| 48 | to the IPMMU and the second cell the number of the micro-TLB that the | |
| 49 | device is connected to. | |
| 50 | ||
| 51 | ||
| 52 | Example: R8A7791 IPMMU-MX and VSP1-D0 bus master | |
| 53 | ||
| 54 | ipmmu_mx: mmu@fe951000 { | |
| 89ae54ba | 55 | compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa"; |
| 4a93f21d LP |
56 | reg = <0 0xfe951000 0 0x1000>; |
| 57 | interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, | |
| 58 | <0 221 IRQ_TYPE_LEVEL_HIGH>; | |
| 59 | #iommu-cells = <1>; | |
| 60 | }; | |
| 61 | ||
| d67ac3ae | 62 | vsp@fe928000 { |
| 4a93f21d LP |
63 | ... |
| 64 | iommus = <&ipmmu_mx 13>; | |
| 65 | ... | |
| 66 | }; |