Commit | Line | Data |
---|---|---|
d27bd6b9 RH |
1 | # SPDX-License-Identifier: GPL-2.0-only |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: ARM System MMU Architecture Implementation | |
8 | ||
9 | maintainers: | |
10 | - Will Deacon <will@kernel.org> | |
11 | - Robin Murphy <Robin.Murphy@arm.com> | |
12 | ||
13 | description: |+ | |
14 | ARM SoCs may contain an implementation of the ARM System Memory | |
15 | Management Unit Architecture, which can be used to provide 1 or 2 stages | |
16 | of address translation to bus masters external to the CPU. | |
17 | ||
18 | The SMMU may also raise interrupts in response to various fault | |
19 | conditions. | |
20 | ||
21 | properties: | |
22 | $nodename: | |
23 | pattern: "^iommu@[0-9a-f]*" | |
24 | compatible: | |
25 | oneOf: | |
26 | - description: Qcom SoCs implementing "arm,smmu-v2" | |
27 | items: | |
28 | - enum: | |
29 | - qcom,msm8996-smmu-v2 | |
30 | - qcom,msm8998-smmu-v2 | |
31 | - qcom,sdm845-smmu-v2 | |
32 | - const: qcom,smmu-v2 | |
33 | ||
34 | - description: Qcom SoCs implementing "arm,mmu-500" | |
35 | items: | |
36 | - enum: | |
f0d83c66 | 37 | - qcom,sc7180-smmu-500 |
d27bd6b9 RH |
38 | - qcom,sdm845-smmu-500 |
39 | - const: arm,mmu-500 | |
40 | - items: | |
41 | - const: arm,mmu-500 | |
42 | - const: arm,smmu-v2 | |
43 | - items: | |
44 | - const: arm,mmu-401 | |
45 | - const: arm,smmu-v1 | |
46 | - enum: | |
47 | - arm,smmu-v1 | |
48 | - arm,smmu-v2 | |
49 | - arm,mmu-400 | |
50 | - arm,mmu-401 | |
51 | - arm,mmu-500 | |
52 | - cavium,smmu-v2 | |
53 | ||
54 | reg: | |
55 | maxItems: 1 | |
56 | ||
57 | '#global-interrupts': | |
58 | description: The number of global interrupts exposed by the device. | |
59 | allOf: | |
60 | - $ref: /schemas/types.yaml#/definitions/uint32 | |
61 | minimum: 0 | |
62 | maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters | |
63 | ||
64 | '#iommu-cells': | |
65 | enum: [ 1, 2 ] | |
66 | description: | | |
67 | See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a | |
68 | value of 1, each IOMMU specifier represents a distinct stream ID emitted | |
69 | by that device into the relevant SMMU. | |
70 | ||
71 | SMMUs with stream matching support and complex masters may use a value of | |
72 | 2, where the second cell of the IOMMU specifier represents an SMR mask to | |
73 | combine with the ID in the first cell. Care must be taken to ensure the | |
74 | set of matched IDs does not result in conflicts. | |
75 | ||
76 | interrupts: | |
77 | minItems: 1 | |
78 | maxItems: 388 # 260 plus 128 contexts | |
79 | description: | | |
80 | Interrupt list, with the first #global-interrupts entries corresponding to | |
81 | the global interrupts and any following entries corresponding to context | |
82 | interrupts, specified in order of their indexing by the SMMU. | |
83 | ||
84 | For SMMUv2 implementations, there must be exactly one interrupt per | |
85 | context bank. In the case of a single, combined interrupt, it must be | |
86 | listed multiple times. | |
87 | ||
88 | dma-coherent: | |
89 | description: | | |
90 | Present if page table walks made by the SMMU are cache coherent with the | |
91 | CPU. | |
92 | ||
93 | NOTE: this only applies to the SMMU itself, not masters connected | |
94 | upstream of the SMMU. | |
95 | ||
96 | calxeda,smmu-secure-config-access: | |
97 | type: boolean | |
98 | description: | |
99 | Enable proper handling of buggy implementations that always use secure | |
100 | access to SMMU configuration registers. In this case non-secure aliases of | |
101 | secure registers have to be used during SMMU configuration. | |
102 | ||
103 | stream-match-mask: | |
104 | $ref: /schemas/types.yaml#/definitions/uint32 | |
105 | description: | | |
106 | For SMMUs supporting stream matching and using #iommu-cells = <1>, | |
107 | specifies a mask of bits to ignore when matching stream IDs (e.g. this may | |
108 | be programmed into the SMRn.MASK field of every stream match register | |
109 | used). For cases where it is desirable to ignore some portion of every | |
110 | Stream ID (e.g. for certain MMU-500 configurations given globally unique | |
111 | input IDs). This property is not valid for SMMUs using stream indexing, or | |
112 | using stream matching with #iommu-cells = <2>, and may be ignored if | |
113 | present in such cases. | |
114 | ||
115 | clock-names: | |
116 | items: | |
117 | - const: bus | |
118 | - const: iface | |
119 | ||
120 | clocks: | |
121 | items: | |
122 | - description: bus clock required for downstream bus access and for the | |
123 | smmu ptw | |
124 | - description: interface clock required to access smmu's registers | |
125 | through the TCU's programming interface. | |
126 | ||
127 | power-domains: | |
128 | maxItems: 1 | |
129 | ||
130 | required: | |
131 | - compatible | |
132 | - reg | |
133 | - '#global-interrupts' | |
134 | - '#iommu-cells' | |
135 | - interrupts | |
136 | ||
137 | additionalProperties: false | |
138 | ||
139 | examples: | |
140 | - |+ | |
141 | /* SMMU with stream matching or stream indexing */ | |
142 | smmu1: iommu@ba5e0000 { | |
143 | compatible = "arm,smmu-v1"; | |
144 | reg = <0xba5e0000 0x10000>; | |
145 | #global-interrupts = <2>; | |
146 | interrupts = <0 32 4>, | |
147 | <0 33 4>, | |
148 | <0 34 4>, /* This is the first context interrupt */ | |
149 | <0 35 4>, | |
150 | <0 36 4>, | |
151 | <0 37 4>; | |
152 | #iommu-cells = <1>; | |
153 | }; | |
154 | ||
155 | /* device with two stream IDs, 0 and 7 */ | |
156 | master1 { | |
157 | iommus = <&smmu1 0>, | |
158 | <&smmu1 7>; | |
159 | }; | |
160 | ||
161 | ||
162 | /* SMMU with stream matching */ | |
163 | smmu2: iommu@ba5f0000 { | |
164 | compatible = "arm,smmu-v1"; | |
165 | reg = <0xba5f0000 0x10000>; | |
166 | #global-interrupts = <2>; | |
167 | interrupts = <0 38 4>, | |
168 | <0 39 4>, | |
169 | <0 40 4>, /* This is the first context interrupt */ | |
170 | <0 41 4>, | |
171 | <0 42 4>, | |
172 | <0 43 4>; | |
173 | #iommu-cells = <2>; | |
174 | }; | |
175 | ||
176 | /* device with stream IDs 0 and 7 */ | |
177 | master2 { | |
178 | iommus = <&smmu2 0 0>, | |
179 | <&smmu2 7 0>; | |
180 | }; | |
181 | ||
182 | /* device with stream IDs 1, 17, 33 and 49 */ | |
183 | master3 { | |
184 | iommus = <&smmu2 1 0x30>; | |
185 | }; | |
186 | ||
187 | ||
188 | /* ARM MMU-500 with 10-bit stream ID input configuration */ | |
189 | smmu3: iommu@ba600000 { | |
190 | compatible = "arm,mmu-500", "arm,smmu-v2"; | |
191 | reg = <0xba600000 0x10000>; | |
192 | #global-interrupts = <2>; | |
193 | interrupts = <0 44 4>, | |
194 | <0 45 4>, | |
195 | <0 46 4>, /* This is the first context interrupt */ | |
196 | <0 47 4>, | |
197 | <0 48 4>, | |
198 | <0 49 4>; | |
199 | #iommu-cells = <1>; | |
200 | /* always ignore appended 5-bit TBU number */ | |
201 | stream-match-mask = <0x7c00>; | |
202 | }; | |
203 | ||
204 | bus { | |
205 | /* bus whose child devices emit one unique 10-bit stream | |
206 | ID each, but may master through multiple SMMU TBUs */ | |
207 | iommu-map = <0 &smmu3 0 0x400>; | |
208 | ||
209 | ||
210 | }; | |
211 | ||
212 | - |+ | |
213 | /* Qcom's arm,smmu-v2 implementation */ | |
214 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
215 | #include <dt-bindings/interrupt-controller/irq.h> | |
216 | smmu4: iommu@d00000 { | |
217 | compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; | |
218 | reg = <0xd00000 0x10000>; | |
219 | ||
220 | #global-interrupts = <1>; | |
221 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
222 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
223 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; | |
224 | #iommu-cells = <1>; | |
225 | power-domains = <&mmcc 0>; | |
226 | ||
227 | clocks = <&mmcc 123>, | |
228 | <&mmcc 124>; | |
229 | clock-names = "bus", "iface"; | |
230 | }; |