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d27bd6b9 RH |
1 | # SPDX-License-Identifier: GPL-2.0-only |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: ARM System MMU Architecture Implementation | |
8 | ||
9 | maintainers: | |
10 | - Will Deacon <will@kernel.org> | |
11 | - Robin Murphy <Robin.Murphy@arm.com> | |
12 | ||
13 | description: |+ | |
14 | ARM SoCs may contain an implementation of the ARM System Memory | |
15 | Management Unit Architecture, which can be used to provide 1 or 2 stages | |
16 | of address translation to bus masters external to the CPU. | |
17 | ||
18 | The SMMU may also raise interrupts in response to various fault | |
19 | conditions. | |
20 | ||
21 | properties: | |
22 | $nodename: | |
23 | pattern: "^iommu@[0-9a-f]*" | |
24 | compatible: | |
25 | oneOf: | |
26 | - description: Qcom SoCs implementing "arm,smmu-v2" | |
27 | items: | |
28 | - enum: | |
29 | - qcom,msm8996-smmu-v2 | |
30 | - qcom,msm8998-smmu-v2 | |
dbf88f74 | 31 | - qcom,sdm630-smmu-v2 |
d27bd6b9 RH |
32 | - const: qcom,smmu-v2 |
33 | ||
6c84bbd1 | 34 | - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" |
d27bd6b9 RH |
35 | items: |
36 | - enum: | |
f1edce3d | 37 | - qcom,qcm2290-smmu-500 |
6313f4b5 | 38 | - qcom,qdu1000-smmu-500 |
0802999c | 39 | - qcom,sa8775p-smmu-500 |
f0d83c66 | 40 | - qcom,sc7180-smmu-500 |
a9aa2bb1 | 41 | - qcom,sc7280-smmu-500 |
9cde12ba | 42 | - qcom,sc8180x-smmu-500 |
38db6b41 | 43 | - qcom,sc8280xp-smmu-500 |
8d3a9ec6 | 44 | - qcom,sdm670-smmu-500 |
d27bd6b9 | 45 | - qcom,sdm845-smmu-500 |
eb9181a3 MS |
46 | - qcom,sdx55-smmu-500 |
47 | - qcom,sdx65-smmu-500 | |
6c84bbd1 | 48 | - qcom,sm6115-smmu-500 |
822765f4 | 49 | - qcom,sm6125-smmu-500 |
6c84bbd1 DB |
50 | - qcom,sm6350-smmu-500 |
51 | - qcom,sm6375-smmu-500 | |
52 | - qcom,sm8150-smmu-500 | |
53 | - qcom,sm8250-smmu-500 | |
54 | - qcom,sm8350-smmu-500 | |
55 | - qcom,sm8450-smmu-500 | |
7f061c19 | 56 | - qcom,sm8550-smmu-500 |
6c84bbd1 DB |
57 | - const: qcom,smmu-500 |
58 | - const: arm,mmu-500 | |
59 | ||
6c84bbd1 DB |
60 | - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) |
61 | deprecated: true | |
62 | items: | |
63 | # Do not add additional SoC to this list. Instead use two previous lists. | |
64 | - enum: | |
65 | - qcom,qcm2290-smmu-500 | |
66 | - qcom,sc7180-smmu-500 | |
67 | - qcom,sc7280-smmu-500 | |
68 | - qcom,sc8180x-smmu-500 | |
69 | - qcom,sc8280xp-smmu-500 | |
70 | - qcom,sdm845-smmu-500 | |
728b22a5 | 71 | - qcom,sm6115-smmu-500 |
e4a40f15 | 72 | - qcom,sm6350-smmu-500 |
743302d4 | 73 | - qcom,sm6375-smmu-500 |
7b6b70d8 JM |
74 | - qcom,sm8150-smmu-500 |
75 | - qcom,sm8250-smmu-500 | |
70b5b6a6 | 76 | - qcom,sm8350-smmu-500 |
810d8cab | 77 | - qcom,sm8450-smmu-500 |
d27bd6b9 | 78 | - const: arm,mmu-500 |
5c368661 KD |
79 | - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" |
80 | items: | |
81 | - enum: | |
387a80a7 | 82 | - qcom,sa8775p-smmu-500 |
5c368661 | 83 | - qcom,sc7280-smmu-500 |
84b8a7fe | 84 | - qcom,sc8280xp-smmu-500 |
3ad65855 KD |
85 | - qcom,sm6115-smmu-500 |
86 | - qcom,sm6125-smmu-500 | |
5c368661 KD |
87 | - qcom,sm8150-smmu-500 |
88 | - qcom,sm8250-smmu-500 | |
16d16468 | 89 | - qcom,sm8350-smmu-500 |
5c368661 KD |
90 | - const: qcom,adreno-smmu |
91 | - const: qcom,smmu-500 | |
92 | - const: arm,mmu-500 | |
93 | - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding) | |
94 | deprecated: true | |
dbf88f74 | 95 | items: |
5c368661 | 96 | # Do not add additional SoC to this list. Instead use previous list. |
dbf88f74 DB |
97 | - enum: |
98 | - qcom,sc7280-smmu-500 | |
11321f77 | 99 | - qcom,sm8150-smmu-500 |
dbf88f74 DB |
100 | - qcom,sm8250-smmu-500 |
101 | - const: qcom,adreno-smmu | |
102 | - const: arm,mmu-500 | |
a29bbb08 JC |
103 | - description: Qcom Adreno GPUs implementing "arm,smmu-v2" |
104 | items: | |
105 | - enum: | |
dbf88f74 | 106 | - qcom,msm8996-smmu-v2 |
a29bbb08 | 107 | - qcom,sc7180-smmu-v2 |
dbf88f74 | 108 | - qcom,sdm630-smmu-v2 |
a29bbb08 | 109 | - qcom,sdm845-smmu-v2 |
5a47cb4d | 110 | - qcom,sm6350-smmu-v2 |
a29bbb08 JC |
111 | - const: qcom,adreno-smmu |
112 | - const: qcom,smmu-v2 | |
3a12e8c0 DB |
113 | - description: Qcom Adreno GPUs on Google Cheza platform |
114 | items: | |
115 | - const: qcom,sdm845-smmu-v2 | |
116 | - const: qcom,smmu-v2 | |
e85e84d1 TN |
117 | - description: Marvell SoCs implementing "arm,mmu-500" |
118 | items: | |
119 | - const: marvell,ap806-smmu-500 | |
120 | - const: arm,mmu-500 | |
4287861d TR |
121 | - description: NVIDIA SoCs that require memory controller interaction |
122 | and may program multiple ARM MMU-500s identically with the memory | |
123 | controller interleaving translations between multiple instances | |
124 | for improved performance. | |
125 | items: | |
3d2deb0c | 126 | - enum: |
bf3ec9de | 127 | - nvidia,tegra186-smmu |
95d5aeab TR |
128 | - nvidia,tegra194-smmu |
129 | - nvidia,tegra234-smmu | |
3d2deb0c | 130 | - const: nvidia,smmu-500 |
d27bd6b9 RH |
131 | - items: |
132 | - const: arm,mmu-500 | |
133 | - const: arm,smmu-v2 | |
134 | - items: | |
bd0d6960 AP |
135 | - enum: |
136 | - arm,mmu-400 | |
137 | - arm,mmu-401 | |
d27bd6b9 RH |
138 | - const: arm,smmu-v1 |
139 | - enum: | |
140 | - arm,smmu-v1 | |
141 | - arm,smmu-v2 | |
142 | - arm,mmu-400 | |
143 | - arm,mmu-401 | |
144 | - arm,mmu-500 | |
145 | - cavium,smmu-v2 | |
146 | ||
147 | reg: | |
3d2deb0c KR |
148 | minItems: 1 |
149 | maxItems: 2 | |
d27bd6b9 RH |
150 | |
151 | '#global-interrupts': | |
152 | description: The number of global interrupts exposed by the device. | |
3d21a460 | 153 | $ref: /schemas/types.yaml#/definitions/uint32 |
d27bd6b9 RH |
154 | minimum: 0 |
155 | maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters | |
156 | ||
157 | '#iommu-cells': | |
158 | enum: [ 1, 2 ] | |
159 | description: | | |
160 | See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a | |
161 | value of 1, each IOMMU specifier represents a distinct stream ID emitted | |
162 | by that device into the relevant SMMU. | |
163 | ||
164 | SMMUs with stream matching support and complex masters may use a value of | |
165 | 2, where the second cell of the IOMMU specifier represents an SMR mask to | |
166 | combine with the ID in the first cell. Care must be taken to ensure the | |
167 | set of matched IDs does not result in conflicts. | |
168 | ||
169 | interrupts: | |
170 | minItems: 1 | |
171 | maxItems: 388 # 260 plus 128 contexts | |
172 | description: | | |
173 | Interrupt list, with the first #global-interrupts entries corresponding to | |
174 | the global interrupts and any following entries corresponding to context | |
175 | interrupts, specified in order of their indexing by the SMMU. | |
176 | ||
177 | For SMMUv2 implementations, there must be exactly one interrupt per | |
178 | context bank. In the case of a single, combined interrupt, it must be | |
179 | listed multiple times. | |
180 | ||
181 | dma-coherent: | |
182 | description: | | |
183 | Present if page table walks made by the SMMU are cache coherent with the | |
184 | CPU. | |
185 | ||
186 | NOTE: this only applies to the SMMU itself, not masters connected | |
187 | upstream of the SMMU. | |
188 | ||
189 | calxeda,smmu-secure-config-access: | |
190 | type: boolean | |
191 | description: | |
192 | Enable proper handling of buggy implementations that always use secure | |
193 | access to SMMU configuration registers. In this case non-secure aliases of | |
194 | secure registers have to be used during SMMU configuration. | |
195 | ||
196 | stream-match-mask: | |
197 | $ref: /schemas/types.yaml#/definitions/uint32 | |
198 | description: | | |
199 | For SMMUs supporting stream matching and using #iommu-cells = <1>, | |
200 | specifies a mask of bits to ignore when matching stream IDs (e.g. this may | |
201 | be programmed into the SMRn.MASK field of every stream match register | |
202 | used). For cases where it is desirable to ignore some portion of every | |
203 | Stream ID (e.g. for certain MMU-500 configurations given globally unique | |
204 | input IDs). This property is not valid for SMMUs using stream indexing, or | |
205 | using stream matching with #iommu-cells = <2>, and may be ignored if | |
206 | present in such cases. | |
207 | ||
208 | clock-names: | |
982295bf DB |
209 | minItems: 1 |
210 | maxItems: 7 | |
d27bd6b9 RH |
211 | |
212 | clocks: | |
982295bf DB |
213 | minItems: 1 |
214 | maxItems: 7 | |
d27bd6b9 RH |
215 | |
216 | power-domains: | |
6bc6af37 KD |
217 | minItems: 1 |
218 | maxItems: 3 | |
d27bd6b9 | 219 | |
c02bda09 TR |
220 | nvidia,memory-controller: |
221 | description: | | |
222 | A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. | |
223 | The memory controller needs to be programmed with a mapping of memory | |
224 | client IDs to ARM SMMU stream IDs. | |
225 | ||
226 | If this property is absent, the mapping programmed by early firmware | |
227 | will be used and it is not guaranteed that IOMMU translations will be | |
228 | enabled for any given device. | |
229 | $ref: /schemas/types.yaml#/definitions/phandle | |
230 | ||
d27bd6b9 RH |
231 | required: |
232 | - compatible | |
233 | - reg | |
234 | - '#global-interrupts' | |
235 | - '#iommu-cells' | |
236 | - interrupts | |
237 | ||
238 | additionalProperties: false | |
239 | ||
3d2deb0c KR |
240 | allOf: |
241 | - if: | |
242 | properties: | |
243 | compatible: | |
244 | contains: | |
245 | enum: | |
4287861d | 246 | - nvidia,tegra186-smmu |
95d5aeab TR |
247 | - nvidia,tegra194-smmu |
248 | - nvidia,tegra234-smmu | |
3d2deb0c KR |
249 | then: |
250 | properties: | |
251 | reg: | |
4287861d | 252 | minItems: 1 |
3d2deb0c | 253 | maxItems: 2 |
c02bda09 TR |
254 | |
255 | # The reference to the memory controller is required to ensure that the | |
256 | # memory client to stream ID mapping can be done synchronously with the | |
257 | # IOMMU attachment. | |
258 | required: | |
259 | - nvidia,memory-controller | |
3d2deb0c KR |
260 | else: |
261 | properties: | |
262 | reg: | |
263 | maxItems: 1 | |
264 | ||
982295bf DB |
265 | - if: |
266 | properties: | |
267 | compatible: | |
268 | contains: | |
269 | enum: | |
270 | - qcom,msm8998-smmu-v2 | |
271 | - qcom,sdm630-smmu-v2 | |
272 | then: | |
273 | anyOf: | |
274 | - properties: | |
275 | clock-names: | |
276 | items: | |
277 | - const: bus | |
278 | clocks: | |
279 | items: | |
280 | - description: bus clock required for downstream bus access and for | |
281 | the smmu ptw | |
282 | - properties: | |
283 | clock-names: | |
284 | items: | |
285 | - const: iface | |
286 | - const: mem | |
287 | - const: mem_iface | |
288 | clocks: | |
289 | items: | |
290 | - description: interface clock required to access smmu's registers | |
291 | through the TCU's programming interface. | |
292 | - description: bus clock required for memory access | |
293 | - description: bus clock required for GPU memory access | |
294 | - properties: | |
295 | clock-names: | |
296 | items: | |
297 | - const: iface-mm | |
298 | - const: iface-smmu | |
299 | - const: bus-mm | |
300 | - const: bus-smmu | |
301 | clocks: | |
302 | items: | |
303 | - description: interface clock required to access mnoc's registers | |
304 | through the TCU's programming interface. | |
305 | - description: interface clock required to access smmu's registers | |
306 | through the TCU's programming interface. | |
307 | - description: bus clock required for downstream bus access | |
308 | - description: bus clock required for the smmu ptw | |
309 | ||
310 | - if: | |
311 | properties: | |
312 | compatible: | |
313 | contains: | |
314 | enum: | |
315 | - qcom,msm8996-smmu-v2 | |
316 | - qcom,sc7180-smmu-v2 | |
317 | - qcom,sdm845-smmu-v2 | |
318 | then: | |
319 | properties: | |
320 | clock-names: | |
321 | items: | |
322 | - const: bus | |
323 | - const: iface | |
324 | ||
325 | clocks: | |
326 | items: | |
327 | - description: bus clock required for downstream bus access and for | |
328 | the smmu ptw | |
329 | - description: interface clock required to access smmu's registers | |
330 | through the TCU's programming interface. | |
331 | ||
332 | - if: | |
333 | properties: | |
334 | compatible: | |
335 | contains: | |
84b8a7fe | 336 | enum: |
387a80a7 | 337 | - qcom,sa8775p-smmu-500 |
84b8a7fe BA |
338 | - qcom,sc7280-smmu-500 |
339 | - qcom,sc8280xp-smmu-500 | |
982295bf DB |
340 | then: |
341 | properties: | |
342 | clock-names: | |
343 | items: | |
344 | - const: gcc_gpu_memnoc_gfx_clk | |
345 | - const: gcc_gpu_snoc_dvm_gfx_clk | |
346 | - const: gpu_cc_ahb_clk | |
347 | - const: gpu_cc_hlos1_vote_gpu_smmu_clk | |
348 | - const: gpu_cc_cx_gmu_clk | |
349 | - const: gpu_cc_hub_cx_int_clk | |
350 | - const: gpu_cc_hub_aon_clk | |
351 | ||
352 | clocks: | |
353 | items: | |
354 | - description: GPU memnoc_gfx clock | |
355 | - description: GPU snoc_dvm_gfx clock | |
356 | - description: GPU ahb clock | |
357 | - description: GPU hlos1_vote_GPU smmu clock | |
358 | - description: GPU cx_gmu clock | |
359 | - description: GPU hub_cx_int clock | |
360 | - description: GPU hub_aon clock | |
361 | ||
362 | - if: | |
363 | properties: | |
364 | compatible: | |
365 | contains: | |
366 | enum: | |
5a47cb4d | 367 | - qcom,sm6350-smmu-v2 |
982295bf DB |
368 | - qcom,sm8150-smmu-500 |
369 | - qcom,sm8250-smmu-500 | |
370 | then: | |
371 | properties: | |
372 | clock-names: | |
373 | items: | |
374 | - const: ahb | |
375 | - const: bus | |
376 | - const: iface | |
377 | ||
378 | clocks: | |
379 | items: | |
380 | - description: bus clock required for AHB bus access | |
381 | - description: bus clock required for downstream bus access and for | |
382 | the smmu ptw | |
383 | - description: interface clock required to access smmu's registers | |
384 | through the TCU's programming interface. | |
385 | ||
3ad65855 KD |
386 | - if: |
387 | properties: | |
388 | compatible: | |
389 | items: | |
390 | - enum: | |
391 | - qcom,sm6115-smmu-500 | |
392 | - qcom,sm6125-smmu-500 | |
393 | - const: qcom,adreno-smmu | |
394 | - const: qcom,smmu-500 | |
395 | - const: arm,mmu-500 | |
396 | then: | |
397 | properties: | |
398 | clock-names: | |
399 | items: | |
400 | - const: mem | |
401 | - const: hlos | |
402 | - const: iface | |
403 | ||
404 | clocks: | |
405 | items: | |
406 | - description: GPU memory bus clock | |
407 | - description: Voter clock required for HLOS SMMU access | |
408 | - description: Interface clock required for register access | |
409 | ||
d565d60d KK |
410 | # Disallow clocks for all other platforms with specific compatibles |
411 | - if: | |
412 | properties: | |
413 | compatible: | |
414 | contains: | |
415 | enum: | |
416 | - cavium,smmu-v2 | |
417 | - marvell,ap806-smmu-500 | |
418 | - nvidia,smmu-500 | |
419 | - qcom,qcm2290-smmu-500 | |
420 | - qcom,qdu1000-smmu-500 | |
421 | - qcom,sc7180-smmu-500 | |
422 | - qcom,sc8180x-smmu-500 | |
d565d60d KK |
423 | - qcom,sdm670-smmu-500 |
424 | - qcom,sdm845-smmu-500 | |
425 | - qcom,sdx55-smmu-500 | |
426 | - qcom,sdx65-smmu-500 | |
d565d60d KK |
427 | - qcom,sm6350-smmu-500 |
428 | - qcom,sm6375-smmu-500 | |
429 | - qcom,sm8350-smmu-500 | |
430 | - qcom,sm8450-smmu-500 | |
7f061c19 | 431 | - qcom,sm8550-smmu-500 |
d565d60d KK |
432 | then: |
433 | properties: | |
434 | clock-names: false | |
435 | clocks: false | |
436 | ||
6bc6af37 KD |
437 | - if: |
438 | properties: | |
439 | compatible: | |
440 | contains: | |
441 | const: qcom,sm6375-smmu-500 | |
442 | then: | |
443 | properties: | |
444 | power-domains: | |
445 | items: | |
446 | - description: SNoC MMU TBU RT GDSC | |
447 | - description: SNoC MMU TBU NRT GDSC | |
448 | - description: SNoC TURING MMU TBU0 GDSC | |
449 | ||
450 | required: | |
451 | - power-domains | |
452 | else: | |
453 | properties: | |
454 | power-domains: | |
455 | maxItems: 1 | |
456 | ||
d27bd6b9 RH |
457 | examples: |
458 | - |+ | |
459 | /* SMMU with stream matching or stream indexing */ | |
460 | smmu1: iommu@ba5e0000 { | |
461 | compatible = "arm,smmu-v1"; | |
462 | reg = <0xba5e0000 0x10000>; | |
463 | #global-interrupts = <2>; | |
464 | interrupts = <0 32 4>, | |
465 | <0 33 4>, | |
466 | <0 34 4>, /* This is the first context interrupt */ | |
467 | <0 35 4>, | |
468 | <0 36 4>, | |
469 | <0 37 4>; | |
470 | #iommu-cells = <1>; | |
471 | }; | |
472 | ||
473 | /* device with two stream IDs, 0 and 7 */ | |
474 | master1 { | |
475 | iommus = <&smmu1 0>, | |
476 | <&smmu1 7>; | |
477 | }; | |
478 | ||
479 | ||
480 | /* SMMU with stream matching */ | |
481 | smmu2: iommu@ba5f0000 { | |
482 | compatible = "arm,smmu-v1"; | |
483 | reg = <0xba5f0000 0x10000>; | |
484 | #global-interrupts = <2>; | |
485 | interrupts = <0 38 4>, | |
486 | <0 39 4>, | |
487 | <0 40 4>, /* This is the first context interrupt */ | |
488 | <0 41 4>, | |
489 | <0 42 4>, | |
490 | <0 43 4>; | |
491 | #iommu-cells = <2>; | |
492 | }; | |
493 | ||
494 | /* device with stream IDs 0 and 7 */ | |
495 | master2 { | |
496 | iommus = <&smmu2 0 0>, | |
497 | <&smmu2 7 0>; | |
498 | }; | |
499 | ||
500 | /* device with stream IDs 1, 17, 33 and 49 */ | |
501 | master3 { | |
502 | iommus = <&smmu2 1 0x30>; | |
503 | }; | |
504 | ||
505 | ||
506 | /* ARM MMU-500 with 10-bit stream ID input configuration */ | |
507 | smmu3: iommu@ba600000 { | |
508 | compatible = "arm,mmu-500", "arm,smmu-v2"; | |
509 | reg = <0xba600000 0x10000>; | |
510 | #global-interrupts = <2>; | |
511 | interrupts = <0 44 4>, | |
512 | <0 45 4>, | |
513 | <0 46 4>, /* This is the first context interrupt */ | |
514 | <0 47 4>, | |
515 | <0 48 4>, | |
516 | <0 49 4>; | |
517 | #iommu-cells = <1>; | |
518 | /* always ignore appended 5-bit TBU number */ | |
519 | stream-match-mask = <0x7c00>; | |
520 | }; | |
521 | ||
522 | bus { | |
523 | /* bus whose child devices emit one unique 10-bit stream | |
524 | ID each, but may master through multiple SMMU TBUs */ | |
525 | iommu-map = <0 &smmu3 0 0x400>; | |
526 | ||
527 | ||
528 | }; | |
529 | ||
530 | - |+ | |
531 | /* Qcom's arm,smmu-v2 implementation */ | |
532 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
533 | #include <dt-bindings/interrupt-controller/irq.h> | |
534 | smmu4: iommu@d00000 { | |
535 | compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; | |
536 | reg = <0xd00000 0x10000>; | |
537 | ||
538 | #global-interrupts = <1>; | |
539 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
540 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
541 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; | |
542 | #iommu-cells = <1>; | |
543 | power-domains = <&mmcc 0>; | |
544 | ||
545 | clocks = <&mmcc 123>, | |
546 | <&mmcc 124>; | |
547 | clock-names = "bus", "iface"; | |
548 | }; |