[linux-2.6-block.git] / Documentation / devicetree / bindings / interrupt-controller / marvell,armada-8k-pic.txt

Marvell Armada 7K/8K PIC Interrupt controller
---------------------------------------------

This is the Device Tree binding for the PIC, a secondary interrupt
controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
typically connected to the GIC as the primary interrupt controller.

Required properties:
- compatible: should be "marvell,armada-8k-pic"
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: the number of cells to define interrupts on this
  controller. Should be 1
- reg: the register area for the PIC interrupt controller
- interrupts: the interrupt to the primary interrupt controller,
  typically the GIC

Example:

	pic: interrupt-controller@3f0100 {
		compatible = "marvell,armada-8k-pic";
		reg = <0x3f0100 0x10>;
		#interrupt-cells = <1>;
		interrupt-controller;
		interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
	};
Commit	Line	Data
33a6c324 TP	1	Marvell Armada 7K/8K PIC Interrupt controller
	2	---------------------------------------------
	3
	4	This is the Device Tree binding for the PIC, a secondary interrupt
	5	controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
	6	typically connected to the GIC as the primary interrupt controller.
	7
	8	Required properties:
	9	- compatible: should be "marvell,armada-8k-pic"
	10	- interrupt-controller: identifies the node as an interrupt controller
	11	- #interrupt-cells: the number of cells to define interrupts on this
	12	controller. Should be 1
	13	- reg: the register area for the PIC interrupt controller
	14	- interrupts: the interrupt to the primary interrupt controller,
	15	typically the GIC
	16
	17	Example:
	18
	19	pic: interrupt-controller@3f0100 {
	20	compatible = "marvell,armada-8k-pic";
	21	reg = <0x3f0100 0x10>;
	22	#interrupt-cells = <1>;
	23	interrupt-controller;
	24	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
	25	};