Commit | Line | Data |
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96f68023 MZ |
1 | * ARM Generic Interrupt Controller, version 3 |
2 | ||
3 | AArch64 SMP cores are often associated with a GICv3, providing Private | |
4 | Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI), | |
5 | Software Generated Interrupts (SGI), and Locality-specific Peripheral | |
6 | Interrupts (LPI). | |
7 | ||
8 | Main node required properties: | |
9 | ||
10 | - compatible : should at least contain "arm,gic-v3". | |
11 | - interrupt-controller : Identifies the node as an interrupt controller | |
12 | - #interrupt-cells : Specifies the number of cells needed to encode an | |
13 | interrupt source. Must be a single cell with a value of at least 3. | |
14 | ||
15 | The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI | |
16 | interrupts. Other values are reserved for future use. | |
17 | ||
18 | The 2nd cell contains the interrupt number for the interrupt type. | |
19 | SPI interrupts are in the range [0-987]. PPI interrupts are in the | |
20 | range [0-15]. | |
21 | ||
22 | The 3rd cell is the flags, encoded as follows: | |
23 | bits[3:0] trigger type and level flags. | |
24 | 1 = edge triggered | |
25 | 4 = level triggered | |
26 | ||
4aff7b85 WD |
27 | Cells 4 and beyond are reserved for future use and must have a value |
28 | of 0 if present. | |
96f68023 MZ |
29 | |
30 | - reg : Specifies base physical address(s) and size of the GIC | |
31 | registers, in the following order: | |
32 | - GIC Distributor interface (GICD) | |
33 | - GIC Redistributors (GICR), one range per redistributor region | |
34 | - GIC CPU interface (GICC) | |
35 | - GIC Hypervisor interface (GICH) | |
36 | - GIC Virtual CPU interface (GICV) | |
37 | ||
38 | GICC, GICH and GICV are optional. | |
39 | ||
40 | - interrupts : Interrupt source of the VGIC maintenance interrupt. | |
41 | ||
42 | Optional | |
43 | ||
44 | - redistributor-stride : If using padding pages, specifies the stride | |
45 | of consecutive redistributors. Must be a multiple of 64kB. | |
46 | ||
47 | - #redistributor-regions: The number of independent contiguous regions | |
48 | occupied by the redistributors. Required if more than one such | |
49 | region is present. | |
50 | ||
b3a92e2c MZ |
51 | Sub-nodes: |
52 | ||
53 | GICv3 has one or more Interrupt Translation Services (ITS) that are | |
54 | used to route Message Signalled Interrupts (MSI) to the CPUs. | |
55 | ||
56 | These nodes must have the following properties: | |
57 | - compatible : Should at least contain "arm,gic-v3-its". | |
58 | - msi-controller : Boolean property. Identifies the node as an MSI controller | |
dc4dae00 MR |
59 | - #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device |
60 | which will generate the MSI. | |
b3a92e2c MZ |
61 | - reg: Specifies the base physical address and size of the ITS |
62 | registers. | |
63 | ||
64 | The main GIC node must contain the appropriate #address-cells, | |
65 | #size-cells and ranges properties for the reg property of all ITS | |
66 | nodes. | |
67 | ||
96f68023 MZ |
68 | Examples: |
69 | ||
70 | gic: interrupt-controller@2cf00000 { | |
71 | compatible = "arm,gic-v3"; | |
72 | #interrupt-cells = <3>; | |
b3a92e2c MZ |
73 | #address-cells = <2>; |
74 | #size-cells = <2>; | |
75 | ranges; | |
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76 | interrupt-controller; |
77 | reg = <0x0 0x2f000000 0 0x10000>, // GICD | |
78 | <0x0 0x2f100000 0 0x200000>, // GICR | |
79 | <0x0 0x2c000000 0 0x2000>, // GICC | |
80 | <0x0 0x2c010000 0 0x2000>, // GICH | |
81 | <0x0 0x2c020000 0 0x2000>; // GICV | |
82 | interrupts = <1 9 4>; | |
b3a92e2c MZ |
83 | |
84 | gic-its@2c200000 { | |
85 | compatible = "arm,gic-v3-its"; | |
86 | msi-controller; | |
dc4dae00 | 87 | #msi-cells = <1>; |
b3a92e2c MZ |
88 | reg = <0x0 0x2c200000 0 0x200000>; |
89 | }; | |
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90 | }; |
91 | ||
92 | gic: interrupt-controller@2c010000 { | |
93 | compatible = "arm,gic-v3"; | |
94 | #interrupt-cells = <3>; | |
b3a92e2c MZ |
95 | #address-cells = <2>; |
96 | #size-cells = <2>; | |
97 | ranges; | |
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98 | interrupt-controller; |
99 | redistributor-stride = <0x0 0x40000>; // 256kB stride | |
100 | #redistributor-regions = <2>; | |
101 | reg = <0x0 0x2c010000 0 0x10000>, // GICD | |
102 | <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31 | |
103 | <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63 | |
104 | <0x0 0x2c040000 0 0x2000>, // GICC | |
105 | <0x0 0x2c060000 0 0x2000>, // GICH | |
106 | <0x0 0x2c080000 0 0x2000>; // GICV | |
107 | interrupts = <1 9 4>; | |
b3a92e2c MZ |
108 | |
109 | gic-its@2c200000 { | |
110 | compatible = "arm,gic-v3-its"; | |
111 | msi-controller; | |
dc4dae00 | 112 | #msi-cells = <1>; |
b3a92e2c MZ |
113 | reg = <0x0 0x2c200000 0 0x200000>; |
114 | }; | |
115 | ||
116 | gic-its@2c400000 { | |
117 | compatible = "arm,gic-v3-its"; | |
118 | msi-controller; | |
dc4dae00 | 119 | #msi-cells = <1>; |
b3a92e2c MZ |
120 | reg = <0x0 0x2c400000 0 0x200000>; |
121 | }; | |
96f68023 | 122 | }; |