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1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/i2c/renesas,riic.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
a431a091 | 7 | title: Renesas RZ/A and RZ/G2L I2C Bus Interface (RIIC) |
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8 | |
9 | maintainers: | |
10 | - Chris Brandt <chris.brandt@renesas.com> | |
11 | - Wolfram Sang <wsa+renesas@sang-engineering.com> | |
12 | ||
13 | allOf: | |
14 | - $ref: /schemas/i2c/i2c-controller.yaml# | |
15 | ||
16 | properties: | |
17 | compatible: | |
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18 | oneOf: |
19 | - items: | |
20 | - enum: | |
21 | - renesas,riic-r7s72100 # RZ/A1H | |
22 | - renesas,riic-r7s9210 # RZ/A2M | |
23 | - renesas,riic-r9a07g043 # RZ/G2UL and RZ/Five | |
24 | - renesas,riic-r9a07g044 # RZ/G2{L,LC} | |
25 | - renesas,riic-r9a07g054 # RZ/V2L | |
26 | - const: renesas,riic-rz # RZ/A or RZ/G2L | |
27 | ||
28 | - const: renesas,riic-r9a09g057 # RZ/V2H(P) | |
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29 | |
30 | reg: | |
31 | maxItems: 1 | |
32 | ||
33 | interrupts: | |
34 | items: | |
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35 | - description: Transmit End Interrupt |
36 | - description: Receive Data Full Interrupt | |
37 | - description: Transmit Data Empty Interrupt | |
38 | - description: Stop Condition Detection Interrupt | |
39 | - description: Start Condition Detection Interrupt | |
40 | - description: NACK Reception Interrupt | |
41 | - description: Arbitration-Lost Interrupt | |
42 | - description: Timeout Interrupt | |
43 | ||
44 | interrupt-names: | |
45 | items: | |
46 | - const: tei | |
47 | - const: ri | |
48 | - const: ti | |
49 | - const: spi | |
50 | - const: sti | |
51 | - const: naki | |
52 | - const: ali | |
53 | - const: tmoi | |
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54 | |
55 | clock-frequency: | |
56 | description: | |
57 | Desired I2C bus clock frequency in Hz. The absence of this property | |
58 | indicates the default frequency 100 kHz. | |
59 | ||
60 | clocks: | |
61 | maxItems: 1 | |
62 | ||
63 | power-domains: | |
64 | maxItems: 1 | |
65 | ||
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66 | resets: |
67 | maxItems: 1 | |
68 | ||
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69 | required: |
70 | - compatible | |
71 | - reg | |
72 | - interrupts | |
13bf92e6 | 73 | - interrupt-names |
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74 | - clocks |
75 | - clock-frequency | |
76 | - power-domains | |
77 | - '#address-cells' | |
78 | - '#size-cells' | |
79 | ||
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80 | if: |
81 | properties: | |
82 | compatible: | |
83 | contains: | |
84 | enum: | |
db92a6eb | 85 | - renesas,riic-r9a07g043 |
a431a091 | 86 | - renesas,riic-r9a07g044 |
eb1e49e0 | 87 | - renesas,riic-r9a07g054 |
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88 | then: |
89 | required: | |
90 | - resets | |
91 | ||
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92 | unevaluatedProperties: false |
93 | ||
94 | examples: | |
95 | - | | |
96 | #include <dt-bindings/clock/r7s72100-clock.h> | |
97 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
98 | ||
99 | i2c0: i2c@fcfee000 { | |
100 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | |
101 | reg = <0xfcfee000 0x44>; | |
102 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
103 | <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, | |
104 | <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, | |
105 | <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, | |
106 | <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, | |
107 | <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, | |
108 | <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, | |
109 | <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
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110 | interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", |
111 | "tmoi"; | |
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112 | clocks = <&mstp9_clks R7S72100_CLK_I2C0>; |
113 | clock-frequency = <100000>; | |
114 | power-domains = <&cpg_clocks>; | |
115 | #address-cells = <1>; | |
116 | #size-cells = <0>; | |
117 | }; |