projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| dc7c59d7 LD |
1 | NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. |
| 2 | ||
| 3 | Required properties: | |
| 193c9d23 PW |
4 | - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or |
| 5 | "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c". | |
| 6 | For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be | |
| 7 | "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is | |
| 8 | tegra124, tegra132, or tegra210. | |
| dc7c59d7 LD |
9 | Details of compatible are as follows: |
| 10 | nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C | |
| 11 | controller. This only support master mode of I2C communication. Register | |
| 12 | interface/offset and interrupts handling are different than generic I2C | |
| 13 | controller. Driver of DVC I2C controller is only compatible with | |
| 14 | "nvidia,tegra20-i2c-dvc". | |
| 15 | nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support | |
| 16 | master and slave mode of I2C communication. The i2c-tegra driver only | |
| 17 | support master mode of I2C communication. Driver of I2C controller is | |
| 18 | only compatible with "nvidia,tegra20-i2c". | |
| 19 | nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is | |
| 20 | very much similar to Tegra20 I2C controller with additional feature: | |
| 21 | Continue Transfer Support. This feature helps to implement M_NO_START | |
| 22 | as per I2C core API transfer flags. Driver of I2C controller is | |
| 23 | compatible with "nvidia,tegra30-i2c" to enable the continue transfer | |
| 24 | support. This is also compatible with "nvidia,tegra20-i2c" without | |
| 25 | continue transfer support. | |
| 26 | nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is | |
| 27 | very much similar to Tegra30 I2C controller with some hardware | |
| 28 | modification: | |
| 29 | - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and | |
| 30 | fast-clk. Tegra114 has only one clock source called as div-clk and | |
| 31 | hence clock mechanism is changed in I2C controller. | |
| 32 | - Tegra30/Tegra20 I2C controller has enabled per packet transfer by | |
| 33 | default and there is no way to disable it. Tegra114 has this | |
| 34 | interrupt disable by default and SW need to enable explicitly. | |
| 35 | Due to above changes, Tegra114 I2C driver makes incompatible with | |
| 36 | previous hardware driver. Hence, tegra114 I2C controller is compatible | |
| 37 | with "nvidia,tegra114-i2c". | |
| 38 | - reg: Should contain I2C controller registers physical address and length. | |
| 39 | - interrupts: Should contain I2C controller interrupts. | |
| 40 | - address-cells: Address cells for I2C device address. | |
| 41 | - size-cells: Size of the I2C device address. | |
| d8f64797 SW |
42 | - clocks: Must contain an entry for each entry in clock-names. |
| 43 | See ../clocks/clock-bindings.txt for details. | |
| 44 | - clock-names: Must include the following entries: | |
| 45 | Tegra20/Tegra30: | |
| 46 | - div-clk | |
| 47 | - fast-clk | |
| 48 | Tegra114: | |
| 49 | - div-clk | |
| 07999587 SW |
50 | - resets: Must contain an entry for each entry in reset-names. |
| 51 | See ../reset/reset.txt for details. | |
| 52 | - reset-names: Must include the following entries: | |
| 53 | - i2c | |
| ed520c90 SW |
54 | - dmas: Must contain an entry for each entry in clock-names. |
| 55 | See ../dma/dma.txt for details. | |
| 56 | - dma-names: Must include the following entries: | |
| 57 | - rx | |
| 58 | - tx | |
| dc7c59d7 LD |
59 | |
| 60 | Example: | |
| 61 | ||
| 62 | i2c@7000c000 { | |
| 63 | compatible = "nvidia,tegra20-i2c"; | |
| 64 | reg = <0x7000c000 0x100>; | |
| 65 | interrupts = <0 38 0x04>; | |
| 66 | #address-cells = <1>; | |
| 67 | #size-cells = <0>; | |
| 68 | clocks = <&tegra_car 12>, <&tegra_car 124>; | |
| 69 | clock-names = "div-clk", "fast-clk"; | |
| 07999587 SW |
70 | resets = <&tegra_car 12>; |
| 71 | reset-names = "i2c"; | |
| ed520c90 SW |
72 | dmas = <&apbdma 16>, <&apbdma 16>; |
| 73 | dma-names = "rx", "tx"; | |
| dc7c59d7 | 74 | }; |