projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 487a07fb MR |
1 | ARM Mali Utgard GPU |
| 2 | =================== | |
| 3 | ||
| 4 | Required properties: | |
| 5 | - compatible | |
| 6 | * Must be one of the following: | |
| 7 | + "arm,mali-300" | |
| 8 | + "arm,mali-400" | |
| 9 | + "arm,mali-450" | |
| 10 | * And, optionally, one of the vendor specific compatible: | |
| 11 | + allwinner,sun4i-a10-mali | |
| 12 | + allwinner,sun7i-a20-mali | |
| 7c6ffa0b | 13 | + allwinner,sun50i-h5-mali |
| 487a07fb MR |
14 | + amlogic,meson-gxbb-mali |
| 15 | + amlogic,meson-gxl-mali | |
| 6e480762 HS |
16 | + rockchip,rk3036-mali |
| 17 | + rockchip,rk3066-mali | |
| 18 | + rockchip,rk3188-mali | |
| 19 | + rockchip,rk3228-mali | |
| 487a07fb MR |
20 | + stericsson,db8500-mali |
| 21 | ||
| 22 | - reg: Physical base address and length of the GPU registers | |
| 23 | ||
| 24 | - interrupts: an entry for each entry in interrupt-names. | |
| 25 | See ../interrupt-controller/interrupts.txt for details. | |
| 26 | ||
| 27 | - interrupt-names: | |
| 28 | * ppX: Pixel Processor X interrupt (X from 0 to 7) | |
| 29 | * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7) | |
| 30 | * pp: Pixel Processor broadcast interrupt (mali-450 only) | |
| 31 | * gp: Geometry Processor interrupt | |
| 32 | * gpmmu: Geometry Processor MMU interrupt | |
| 33 | ||
| 34 | - clocks: an entry for each entry in clock-names | |
| 35 | - clock-names: | |
| 36 | * bus: bus clock for the GPU | |
| 37 | * core: clock driving the GPU itself | |
| 38 | ||
| 39 | Optional properties: | |
| 40 | - interrupt-names and interrupts: | |
| 41 | * pmu: Power Management Unit interrupt, if implemented in hardware | |
| 42 | ||
| b6b204ea MR |
43 | - memory-region: |
| 44 | Memory region to allocate from, as defined in | |
| 45 | Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt | |
| 46 | ||
| 6b76eb80 MR |
47 | - operating-points-v2: |
| 48 | Operating Points for the GPU, as defined in | |
| 49 | Documentation/devicetree/bindings/opp/opp.txt | |
| 50 | ||
| 487a07fb MR |
51 | Vendor-specific bindings |
| 52 | ------------------------ | |
| 53 | ||
| 54 | The Mali GPU is integrated very differently from one SoC to | |
| 55 | another. In order to accomodate those differences, you have the option | |
| 56 | to specify one more vendor-specific compatible, among: | |
| 57 | ||
| 58 | - allwinner,sun4i-a10-mali | |
| 59 | Required properties: | |
| 60 | * resets: phandle to the reset line for the GPU | |
| 61 | ||
| 62 | - allwinner,sun7i-a20-mali | |
| 63 | Required properties: | |
| 64 | * resets: phandle to the reset line for the GPU | |
| 65 | ||
| 7c6ffa0b IZ |
66 | - allwinner,sun50i-h5-mali |
| 67 | Required properties: | |
| 68 | * resets: phandle to the reset line for the GPU | |
| 69 | ||
| 6e480762 HS |
70 | - Rockchip variants: |
| 71 | Required properties: | |
| 72 | * resets: phandle to the reset line for the GPU | |
| 73 | ||
| 487a07fb MR |
74 | - stericsson,db8500-mali |
| 75 | Required properties: | |
| 76 | * interrupt-names and interrupts: | |
| 77 | + combined: combined interrupt of all of the above lines | |
| 78 | ||
| 79 | Example: | |
| 80 | ||
| 81 | mali: gpu@1c40000 { | |
| 82 | compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; | |
| 83 | reg = <0x01c40000 0x10000>; | |
| 84 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, | |
| 85 | <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, | |
| 86 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, | |
| 87 | <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, | |
| 88 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, | |
| 89 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, | |
| 90 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 91 | interrupt-names = "gp", | |
| 92 | "gpmmu", | |
| 93 | "pp0", | |
| 94 | "ppmmu0", | |
| 95 | "pp1", | |
| 96 | "ppmmu1", | |
| 97 | "pmu"; | |
| 98 | clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; | |
| 99 | clock-names = "bus", "core"; | |
| 100 | resets = <&ccu RST_BUS_GPU>; | |
| 101 | }; | |
| 102 |