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1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: NXP i.MX8 DSP core | |
8 | ||
9 | maintainers: | |
10 | - Daniel Baluta <daniel.baluta@nxp.com> | |
11 | ||
12 | description: | | |
13 | Some boards from i.MX8 family contain a DSP core used for | |
14 | advanced pre- and post- audio processing. | |
15 | ||
16 | properties: | |
17 | compatible: | |
18 | enum: | |
19 | - fsl,imx8qxp-dsp | |
20 | ||
21 | reg: | |
22 | description: Should contain register location and length | |
23 | ||
24 | clocks: | |
25 | items: | |
26 | - description: ipg clock | |
27 | - description: ocram clock | |
28 | - description: core clock | |
29 | ||
30 | clock-names: | |
31 | items: | |
32 | - const: ipg | |
33 | - const: ocram | |
34 | - const: core | |
35 | ||
36 | power-domains: | |
37 | description: | |
38 | List of phandle and PM domain specifier as documented in | |
39 | Documentation/devicetree/bindings/power/power_domain.txt | |
40 | maxItems: 4 | |
41 | ||
42 | mboxes: | |
43 | description: | |
44 | List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB | |
45 | (see mailbox/fsl,mu.txt) | |
46 | maxItems: 4 | |
47 | ||
48 | mbox-names: | |
49 | items: | |
50 | - const: txdb0 | |
51 | - const: txdb1 | |
52 | - const: rxdb0 | |
53 | - const: rxdb1 | |
54 | ||
55 | memory-region: | |
56 | description: | |
57 | phandle to a node describing reserved memory (System RAM memory) | |
58 | used by DSP (see bindings/reserved-memory/reserved-memory.txt) | |
59 | maxItems: 1 | |
60 | ||
61 | required: | |
62 | - compatible | |
63 | - reg | |
64 | - clocks | |
65 | - clock-names | |
66 | - power-domains | |
67 | - mboxes | |
68 | - mbox-names | |
69 | - memory-region | |
70 | ||
71 | examples: | |
72 | - | | |
73 | #include <dt-bindings/firmware/imx/rsrc.h> | |
74 | #include <dt-bindings/clock/imx8-clock.h> | |
75 | dsp@596e8000 { | |
76 | compatible = "fsl,imx8qxp-dsp"; | |
77 | reg = <0x596e8000 0x88000>; | |
78 | clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, | |
79 | <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, | |
80 | <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; | |
81 | clock-names = "ipg", "ocram", "core"; | |
82 | power-domains = <&pd IMX_SC_R_MU_13A>, | |
83 | <&pd IMX_SC_R_MU_13B>, | |
84 | <&pd IMX_SC_R_DSP>, | |
85 | <&pd IMX_SC_R_DSP_RAM>; | |
86 | mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; | |
87 | mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>; | |
e2973352 | 88 | memory-region = <&dsp_reserved>; |
7db2f2df | 89 | }; |