Commit | Line | Data |
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3770f2a6 | 1 | * Renesas R-Car (RZ/G) DMA Controller Device Tree bindings |
10f5c843 | 2 | |
ac3e8ea1 | 3 | Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA |
10f5c843 LP |
4 | controller instances named DMAC capable of serving multiple clients. Channels |
5 | can be dedicated to specific clients or shared between a large number of | |
6 | clients. | |
7 | ||
10f5c843 LP |
8 | Each DMA client is connected to one dedicated port of the DMAC, identified by |
9 | an 8-bit port number called the MID/RID. A DMA controller can thus serve up to | |
10 | 256 clients in total. When the number of hardware channels is lower than the | |
11 | number of clients to be served, channels must be shared between multiple DMA | |
12 | clients. The association of DMA clients to DMAC channels is fully dynamic and | |
13 | not described in these device tree bindings. | |
14 | ||
15 | Required Properties: | |
16 | ||
6bf64103 SH |
17 | - compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback. |
18 | Examples with soctypes are: | |
3770f2a6 SS |
19 | - "renesas,dmac-r8a7743" (RZ/G1M) |
20 | - "renesas,dmac-r8a7745" (RZ/G1E) | |
a0b007e1 | 21 | - "renesas,dmac-r8a77470" (RZ/G1C) |
6bf64103 SH |
22 | - "renesas,dmac-r8a7790" (R-Car H2) |
23 | - "renesas,dmac-r8a7791" (R-Car M2-W) | |
24 | - "renesas,dmac-r8a7792" (R-Car V2H) | |
25 | - "renesas,dmac-r8a7793" (R-Car M2-N) | |
26 | - "renesas,dmac-r8a7794" (R-Car E2) | |
27 | - "renesas,dmac-r8a7795" (R-Car H3) | |
942ba9dc | 28 | - "renesas,dmac-r8a7796" (R-Car M3-W) |
a3f406d6 | 29 | - "renesas,dmac-r8a77970" (R-Car V3M) |
9bfda663 | 30 | - "renesas,dmac-r8a77980" (R-Car V3H) |
10f5c843 LP |
31 | |
32 | - reg: base address and length of the registers block for the DMAC | |
33 | ||
34 | - interrupts: interrupt specifiers for the DMAC, one for each entry in | |
35 | interrupt-names. | |
5466c34f GU |
36 | - interrupt-names: one entry for the error interrupt, named "error", plus one |
37 | entry per channel, named "ch%u", where %u is the channel number ranging from | |
38 | zero to the number of channels minus one. | |
10f5c843 LP |
39 | |
40 | - clock-names: "fck" for the functional clock | |
41 | - clocks: a list of phandle + clock-specifier pairs, one for each entry | |
42 | in clock-names. | |
43 | - clock-names: must contain "fck" for the functional clock. | |
44 | ||
45 | - #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port | |
46 | connected to the DMA client | |
47 | - dma-channels: number of DMA channels | |
48 | ||
49 | Example: R8A7790 (R-Car H2) SYS-DMACs | |
50 | ||
51 | dmac0: dma-controller@e6700000 { | |
6bf64103 | 52 | compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; |
10f5c843 LP |
53 | reg = <0 0xe6700000 0 0x20000>; |
54 | interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH | |
55 | 0 200 IRQ_TYPE_LEVEL_HIGH | |
56 | 0 201 IRQ_TYPE_LEVEL_HIGH | |
57 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
58 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
59 | 0 204 IRQ_TYPE_LEVEL_HIGH | |
60 | 0 205 IRQ_TYPE_LEVEL_HIGH | |
61 | 0 206 IRQ_TYPE_LEVEL_HIGH | |
62 | 0 207 IRQ_TYPE_LEVEL_HIGH | |
63 | 0 208 IRQ_TYPE_LEVEL_HIGH | |
64 | 0 209 IRQ_TYPE_LEVEL_HIGH | |
65 | 0 210 IRQ_TYPE_LEVEL_HIGH | |
66 | 0 211 IRQ_TYPE_LEVEL_HIGH | |
67 | 0 212 IRQ_TYPE_LEVEL_HIGH | |
68 | 0 213 IRQ_TYPE_LEVEL_HIGH | |
69 | 0 214 IRQ_TYPE_LEVEL_HIGH>; | |
70 | interrupt-names = "error", | |
71 | "ch0", "ch1", "ch2", "ch3", | |
72 | "ch4", "ch5", "ch6", "ch7", | |
73 | "ch8", "ch9", "ch10", "ch11", | |
74 | "ch12", "ch13", "ch14"; | |
75 | clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; | |
76 | clock-names = "fck"; | |
77 | #dma-cells = <1>; | |
78 | dma-channels = <15>; | |
79 | }; | |
80 | ||
81 | dmac1: dma-controller@e6720000 { | |
6bf64103 | 82 | compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; |
10f5c843 LP |
83 | reg = <0 0xe6720000 0 0x20000>; |
84 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
85 | 0 216 IRQ_TYPE_LEVEL_HIGH | |
86 | 0 217 IRQ_TYPE_LEVEL_HIGH | |
87 | 0 218 IRQ_TYPE_LEVEL_HIGH | |
88 | 0 219 IRQ_TYPE_LEVEL_HIGH | |
89 | 0 308 IRQ_TYPE_LEVEL_HIGH | |
90 | 0 309 IRQ_TYPE_LEVEL_HIGH | |
91 | 0 310 IRQ_TYPE_LEVEL_HIGH | |
92 | 0 311 IRQ_TYPE_LEVEL_HIGH | |
93 | 0 312 IRQ_TYPE_LEVEL_HIGH | |
94 | 0 313 IRQ_TYPE_LEVEL_HIGH | |
95 | 0 314 IRQ_TYPE_LEVEL_HIGH | |
96 | 0 315 IRQ_TYPE_LEVEL_HIGH | |
97 | 0 316 IRQ_TYPE_LEVEL_HIGH | |
98 | 0 317 IRQ_TYPE_LEVEL_HIGH | |
99 | 0 318 IRQ_TYPE_LEVEL_HIGH>; | |
100 | interrupt-names = "error", | |
101 | "ch0", "ch1", "ch2", "ch3", | |
102 | "ch4", "ch5", "ch6", "ch7", | |
103 | "ch8", "ch9", "ch10", "ch11", | |
104 | "ch12", "ch13", "ch14"; | |
105 | clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; | |
106 | clock-names = "fck"; | |
107 | #dma-cells = <1>; | |
108 | dma-channels = <15>; | |
109 | }; |