Commit | Line | Data |
---|---|---|
440b075b | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
0eda3c6c DB |
2 | %YAML 1.2 |
3 | --- | |
4 | $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: Qualcomm SM8450 Display DPU | |
8 | ||
9 | maintainers: | |
10 | - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | |
11 | ||
12 | $ref: /schemas/display/msm/dpu-common.yaml# | |
13 | ||
14 | properties: | |
15 | compatible: | |
16 | const: qcom,sm8450-dpu | |
17 | ||
18 | reg: | |
19 | items: | |
20 | - description: Address offset and size for mdp register set | |
21 | - description: Address offset and size for vbif register set | |
22 | ||
23 | reg-names: | |
24 | items: | |
25 | - const: mdp | |
26 | - const: vbif | |
27 | ||
28 | clocks: | |
29 | items: | |
30 | - description: Display hf axi | |
31 | - description: Display sf axi | |
32 | - description: Display ahb | |
33 | - description: Display lut | |
34 | - description: Display core | |
35 | - description: Display vsync | |
36 | ||
37 | clock-names: | |
38 | items: | |
39 | - const: bus | |
40 | - const: nrt_bus | |
41 | - const: iface | |
42 | - const: lut | |
43 | - const: core | |
44 | - const: vsync | |
45 | ||
46 | required: | |
47 | - compatible | |
48 | - reg | |
49 | - reg-names | |
50 | - clocks | |
51 | - clock-names | |
52 | ||
53 | unevaluatedProperties: false | |
54 | ||
55 | examples: | |
56 | - | | |
57 | #include <dt-bindings/clock/qcom,sm8450-dispcc.h> | |
58 | #include <dt-bindings/clock/qcom,gcc-sm8450.h> | |
59 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
60 | #include <dt-bindings/interconnect/qcom,sm8450.h> | |
61 | #include <dt-bindings/power/qcom-rpmpd.h> | |
62 | ||
63 | display-controller@ae01000 { | |
64 | compatible = "qcom,sm8450-dpu"; | |
65 | reg = <0x0ae01000 0x8f000>, | |
66 | <0x0aeb0000 0x2008>; | |
67 | reg-names = "mdp", "vbif"; | |
68 | ||
69 | clocks = <&gcc GCC_DISP_HF_AXI_CLK>, | |
70 | <&gcc GCC_DISP_SF_AXI_CLK>, | |
71 | <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
72 | <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, | |
73 | <&dispcc DISP_CC_MDSS_MDP_CLK>, | |
74 | <&dispcc DISP_CC_MDSS_VSYNC_CLK>; | |
75 | clock-names = "bus", | |
76 | "nrt_bus", | |
77 | "iface", | |
78 | "lut", | |
79 | "core", | |
80 | "vsync"; | |
81 | ||
82 | assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; | |
83 | assigned-clock-rates = <19200000>; | |
84 | ||
85 | operating-points-v2 = <&mdp_opp_table>; | |
86 | power-domains = <&rpmhpd SM8450_MMCX>; | |
87 | ||
88 | interrupt-parent = <&mdss>; | |
89 | interrupts = <0>; | |
90 | ||
91 | ports { | |
92 | #address-cells = <1>; | |
93 | #size-cells = <0>; | |
94 | ||
95 | port@0 { | |
96 | reg = <0>; | |
97 | dpu_intf1_out: endpoint { | |
98 | remote-endpoint = <&dsi0_in>; | |
99 | }; | |
100 | }; | |
101 | ||
102 | port@1 { | |
103 | reg = <1>; | |
104 | dpu_intf2_out: endpoint { | |
105 | remote-endpoint = <&dsi1_in>; | |
106 | }; | |
107 | }; | |
108 | }; | |
109 | ||
110 | mdp_opp_table: opp-table { | |
111 | compatible = "operating-points-v2"; | |
112 | ||
113 | opp-172000000{ | |
114 | opp-hz = /bits/ 64 <172000000>; | |
115 | required-opps = <&rpmhpd_opp_low_svs_d1>; | |
116 | }; | |
117 | ||
118 | opp-200000000 { | |
119 | opp-hz = /bits/ 64 <200000000>; | |
120 | required-opps = <&rpmhpd_opp_low_svs>; | |
121 | }; | |
122 | ||
123 | opp-325000000 { | |
124 | opp-hz = /bits/ 64 <325000000>; | |
125 | required-opps = <&rpmhpd_opp_svs>; | |
126 | }; | |
127 | ||
128 | opp-375000000 { | |
129 | opp-hz = /bits/ 64 <375000000>; | |
130 | required-opps = <&rpmhpd_opp_svs_l1>; | |
131 | }; | |
132 | ||
133 | opp-500000000 { | |
134 | opp-hz = /bits/ 64 <500000000>; | |
135 | required-opps = <&rpmhpd_opp_nom>; | |
136 | }; | |
137 | }; | |
138 | }; | |
139 | ... |