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3e4d618b GF |
1 | STMicroelectronics STM32H7 Reset and Clock Controller |
2 | ===================================================== | |
3 | ||
4 | The RCC IP is both a reset and a clock controller. | |
5 | ||
6 | Please refer to clock-bindings.txt for common clock controller binding usage. | |
7 | Please also refer to reset.txt for common reset controller binding usage. | |
8 | ||
9 | Required properties: | |
10 | - compatible: Should be: | |
11 | "st,stm32h743-rcc" | |
12 | ||
13 | - reg: should be register base and length as documented in the | |
14 | datasheet | |
15 | ||
16 | - #reset-cells: 1, see below | |
17 | ||
18 | - #clock-cells : from common clock binding; shall be set to 1 | |
19 | ||
20 | - clocks: External oscillator clock phandle | |
21 | - high speed external clock signal (HSE) | |
22 | - low speed external clock signal (LSE) | |
23 | - external I2S clock (I2S_CKIN) | |
24 | ||
25 | Optional properties: | |
26 | - st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain | |
27 | write protection (RTC clock). | |
28 | ||
29 | Example: | |
30 | ||
31 | rcc: reset-clock-controller@58024400 { | |
32 | compatible = "st,stm32h743-rcc", "st,stm32-rcc"; | |
33 | reg = <0x58024400 0x400>; | |
34 | #reset-cells = <1>; | |
127b8e26 | 35 | #clock-cells = <1>; |
3e4d618b GF |
36 | clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>; |
37 | ||
38 | st,syscfg = <&pwrcfg>; | |
39 | }; | |
40 | ||
41 | The peripheral clock consumer should specify the desired clock by | |
42 | having the clock ID in its "clocks" phandle cell. | |
43 | ||
44 | Example: | |
45 | ||
46 | timer5: timer@40000c00 { | |
47 | compatible = "st,stm32-timer"; | |
48 | reg = <0x40000c00 0x400>; | |
49 | interrupts = <50>; | |
50 | clocks = <&rcc TIM5_CK>; | |
51 | }; | |
52 | ||
53 | Specifying softreset control of devices | |
54 | ======================================= | |
55 | ||
56 | Device nodes should specify the reset channel required in their "resets" | |
57 | property, containing a phandle to the reset device node and an index specifying | |
58 | which channel to use. | |
59 | The index is the bit number within the RCC registers bank, starting from RCC | |
60 | base address. | |
61 | It is calculated as: index = register_offset / 4 * 32 + bit_offset. | |
62 | Where bit_offset is the bit offset within the register. | |
63 | ||
64 | For example, for CRC reset: | |
65 | crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107 | |
66 | ||
67 | Example: | |
68 | ||
69 | timer2 { | |
70 | resets = <&rcc STM32H7_APB1L_RESET(TIM2)>; | |
71 | }; |