Commit | Line | Data |
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708e5ca4 XZ |
1 | * Rockchip RK3036 Clock and Reset Unit |
2 | ||
3 | The RK3036 clock controller generates and supplies clock to various | |
4 | controllers within the SoC and also implements a reset controller for SoC | |
5 | peripherals. | |
6 | ||
7 | Required Properties: | |
8 | ||
9 | - compatible: should be "rockchip,rk3036-cru" | |
10 | - reg: physical base address of the controller and length of memory mapped | |
11 | region. | |
12 | - #clock-cells: should be 1. | |
13 | - #reset-cells: should be 1. | |
14 | ||
15 | Optional Properties: | |
16 | ||
17 | - rockchip,grf: phandle to the syscon managing the "general register files" | |
18 | If missing pll rates are not changeable, due to the missing pll lock status. | |
19 | ||
20 | Each clock is assigned an identifier and client nodes can use this identifier | |
21 | to specify the clock which they consume. All available clocks are defined as | |
22 | preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be | |
23 | used in device tree sources. Similar macros exist for the reset sources in | |
24 | these files. | |
25 | ||
26 | External clocks: | |
27 | ||
28 | There are several clocks that are generated outside the SoC. It is expected | |
29 | that they are defined using standard clock bindings with following | |
30 | clock-output-names: | |
31 | - "xin24m" - crystal input - required, | |
32 | - "ext_i2s" - external I2S clock - optional, | |
3d667920 | 33 | - "rmii_clkin" - external EMAC clock - optional |
708e5ca4 XZ |
34 | |
35 | Example: Clock controller node: | |
36 | ||
37 | cru: cru@20000000 { | |
38 | compatible = "rockchip,rk3036-cru"; | |
39 | reg = <0x20000000 0x1000>; | |
40 | rockchip,grf = <&grf>; | |
41 | ||
42 | #clock-cells = <1>; | |
43 | #reset-cells = <1>; | |
44 | }; | |
45 | ||
46 | Example: UART controller node that consumes the clock generated by the clock | |
47 | controller: | |
48 | ||
49 | uart0: serial@20060000 { | |
50 | compatible = "snps,dw-apb-uart"; | |
51 | reg = <0x20060000 0x100>; | |
52 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
53 | reg-shift = <2>; | |
54 | reg-io-width = <4>; | |
55 | clocks = <&cru SCLK_UART0>; | |
56 | }; |