Commit | Line | Data |
---|---|---|
5a989cf6 RS |
1 | * Samsung Exynos5260 Clock Controller |
2 | ||
3 | Exynos5260 has 13 clock controllers which are instantiated | |
4 | independently from the device-tree. These clock controllers | |
5 | generate and supply clocks to various hardware blocks within | |
6 | the SoC. | |
7 | ||
8 | Each clock is assigned an identifier and client nodes can use | |
9 | this identifier to specify the clock which they consume. All | |
10 | available clocks are defined as preprocessor macros in | |
11 | dt-bindings/clock/exynos5260-clk.h header and can be used in | |
12 | device tree sources. | |
13 | ||
14 | External clocks: | |
15 | ||
16 | There are several clocks that are generated outside the SoC. It | |
17 | is expected that they are defined using standard clock bindings | |
18 | with following clock-output-names: | |
19 | ||
20 | - "fin_pll" - PLL input clock from XXTI | |
21 | - "xrtcxti" - input clock from XRTCXTI | |
22 | - "ioclk_pcm_extclk" - pcm external operation clock | |
23 | - "ioclk_spdif_extclk" - spdif external operation clock | |
24 | - "ioclk_i2s_cdclk" - i2s0 codec clock | |
25 | ||
26 | Phy clocks: | |
27 | ||
28 | There are several clocks which are generated by specific PHYs. | |
29 | These clocks are fed into the clock controller and then routed to | |
30 | the hardware blocks. These clocks are defined as fixed clocks in the | |
31 | driver with following names: | |
32 | ||
33 | - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 | |
34 | - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 | |
35 | - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1 | |
36 | - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0 | |
37 | - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock | |
38 | - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock | |
39 | - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link | |
40 | - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock | |
41 | - "phyclk_dptx_phy_clk_div2" | |
42 | - "phyclk_mipi_dphy_4l_m_rxclkesc0" | |
43 | - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock | |
44 | - "phyclk_usbhost20_phy_freeclk" | |
45 | - "phyclk_usbhost20_phy_clk48mohci" | |
46 | - "phyclk_usbdrd30_udrd30_pipe_pclk" | |
47 | - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock | |
48 | ||
49 | Required Properties for Clock Controller: | |
50 | ||
51 | - compatible: should be one of the following. | |
52 | 1) "samsung,exynos5260-clock-top" | |
53 | 2) "samsung,exynos5260-clock-peri" | |
54 | 3) "samsung,exynos5260-clock-egl" | |
55 | 4) "samsung,exynos5260-clock-kfc" | |
56 | 5) "samsung,exynos5260-clock-g2d" | |
57 | 6) "samsung,exynos5260-clock-mif" | |
58 | 7) "samsung,exynos5260-clock-mfc" | |
59 | 8) "samsung,exynos5260-clock-g3d" | |
60 | 9) "samsung,exynos5260-clock-fsys" | |
61 | 10) "samsung,exynos5260-clock-aud" | |
62 | 11) "samsung,exynos5260-clock-isp" | |
63 | 12) "samsung,exynos5260-clock-gscl" | |
64 | 13) "samsung,exynos5260-clock-disp" | |
65 | ||
66 | - reg: physical base address of the controller and the length of | |
67 | memory mapped region. | |
68 | ||
69 | - #clock-cells: should be 1. | |
70 | ||
71 | - clocks: list of clock identifiers which are fed as the input to | |
72 | the given clock controller. Please refer the next section to find | |
73 | the input clocks for a given controller. | |
74 | ||
75 | - clock-names: list of names of clocks which are fed as the input | |
76 | to the given clock controller. | |
77 | ||
78 | Input clocks for top clock controller: | |
79 | - fin_pll | |
80 | - dout_mem_pll | |
81 | - dout_bus_pll | |
82 | - dout_media_pll | |
83 | ||
84 | Input clocks for peri clock controller: | |
85 | - fin_pll | |
86 | - ioclk_pcm_extclk | |
87 | - ioclk_i2s_cdclk | |
88 | - ioclk_spdif_extclk | |
89 | - phyclk_hdmi_phy_ref_cko | |
90 | - dout_aclk_peri_66 | |
91 | - dout_sclk_peri_uart0 | |
92 | - dout_sclk_peri_uart1 | |
93 | - dout_sclk_peri_uart2 | |
94 | - dout_sclk_peri_spi0_b | |
95 | - dout_sclk_peri_spi1_b | |
96 | - dout_sclk_peri_spi2_b | |
97 | - dout_aclk_peri_aud | |
98 | - dout_sclk_peri_spi0_b | |
99 | ||
100 | Input clocks for egl clock controller: | |
101 | - fin_pll | |
102 | - dout_bus_pll | |
103 | ||
104 | Input clocks for kfc clock controller: | |
105 | - fin_pll | |
106 | - dout_media_pll | |
107 | ||
108 | Input clocks for g2d clock controller: | |
109 | - fin_pll | |
110 | - dout_aclk_g2d_333 | |
111 | ||
112 | Input clocks for mif clock controller: | |
113 | - fin_pll | |
114 | ||
115 | Input clocks for mfc clock controller: | |
116 | - fin_pll | |
117 | - dout_aclk_mfc_333 | |
118 | ||
119 | Input clocks for g3d clock controller: | |
120 | - fin_pll | |
121 | ||
122 | Input clocks for fsys clock controller: | |
123 | - fin_pll | |
124 | - phyclk_usbhost20_phy_phyclock | |
125 | - phyclk_usbhost20_phy_freeclk | |
126 | - phyclk_usbhost20_phy_clk48mohci | |
127 | - phyclk_usbdrd30_udrd30_pipe_pclk | |
128 | - phyclk_usbdrd30_udrd30_phyclock | |
129 | - dout_aclk_fsys_200 | |
130 | ||
131 | Input clocks for aud clock controller: | |
132 | - fin_pll | |
133 | - fout_aud_pll | |
134 | - ioclk_i2s_cdclk | |
135 | - ioclk_pcm_extclk | |
136 | ||
137 | Input clocks for isp clock controller: | |
138 | - fin_pll | |
139 | - dout_aclk_isp1_266 | |
140 | - dout_aclk_isp1_400 | |
141 | - mout_aclk_isp1_266 | |
142 | ||
143 | Input clocks for gscl clock controller: | |
144 | - fin_pll | |
145 | - dout_aclk_gscl_400 | |
146 | - dout_aclk_gscl_333 | |
147 | ||
148 | Input clocks for disp clock controller: | |
149 | - fin_pll | |
150 | - phyclk_dptx_phy_ch3_txd_clk | |
151 | - phyclk_dptx_phy_ch2_txd_clk | |
152 | - phyclk_dptx_phy_ch1_txd_clk | |
153 | - phyclk_dptx_phy_ch0_txd_clk | |
154 | - phyclk_hdmi_phy_tmds_clko | |
155 | - phyclk_hdmi_phy_ref_clko | |
156 | - phyclk_hdmi_phy_pixel_clko | |
157 | - phyclk_hdmi_link_o_tmds_clkhi | |
158 | - phyclk_mipi_dphy_4l_m_txbyte_clkhs | |
159 | - phyclk_dptx_phy_o_ref_clk_24m | |
160 | - phyclk_dptx_phy_clk_div2 | |
161 | - phyclk_mipi_dphy_4l_m_rxclkesc0 | |
162 | - phyclk_hdmi_phy_ref_cko | |
163 | - ioclk_spdif_extclk | |
164 | - dout_aclk_peri_aud | |
165 | - dout_aclk_disp_222 | |
166 | - dout_sclk_disp_pixel | |
167 | - dout_aclk_disp_333 | |
168 | ||
169 | Example 1: An example of a clock controller node is listed below. | |
170 | ||
171 | clock_mfc: clock-controller@11090000 { | |
172 | compatible = "samsung,exynos5260-clock-mfc"; | |
173 | clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>; | |
174 | clock-names = "fin_pll", "dout_aclk_mfc_333"; | |
175 | reg = <0x11090000 0x10000>; | |
176 | #clock-cells = <1>; | |
177 | }; | |
178 | ||
179 | Example 2: UART controller node that consumes the clock generated by the | |
180 | peri clock controller. Refer to the standard clock bindings for | |
181 | information about 'clocks' and 'clock-names' property. | |
182 | ||
afc3bca4 | 183 | serial@12c00000 { |
5a989cf6 RS |
184 | compatible = "samsung,exynos4210-uart"; |
185 | reg = <0x12C00000 0x100>; | |
186 | interrupts = <0 146 0>; | |
187 | clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>; | |
188 | clock-names = "uart", "clk_uart_baud0"; | |
189 | }; | |
190 |