Commit | Line | Data |
---|---|---|
d17adfdb SW |
1 | NVIDIA Tegra Power Management Controller (PMC) |
2 | ||
3 | Properties: | |
4 | - name : Should be pmc | |
5 | - compatible : Should contain "nvidia,tegra<chip>-pmc". | |
6 | - reg : Offset and length of the register set for the device | |
7 | - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. | |
8 | The PMU is an external Power Management Unit, whose interrupt output | |
9 | signal is fed into the PMC. This signal is optionally inverted, and then | |
10 | fed into the ARM GIC. The PMC is not involved in the detection or | |
11 | handling of this interrupt signal, merely its inversion. | |
12 | ||
13 | Example: | |
14 | ||
15 | pmc@7000f400 { | |
16 | compatible = "nvidia,tegra20-pmc"; | |
17 | reg = <0x7000e400 0x400>; | |
18 | nvidia,invert-interrupt; | |
19 | }; |