[linux-block.git] / Documentation / devicetree / bindings / arm / tegra / nvidia,tegra20-pmc.txt

NVIDIA Tegra Power Management Controller (PMC)

== Power Management Controller Node ==

The PMC block interacts with an external Power Management Unit. The PMC
mostly controls the entry and exit of the system from different sleep
modes. It provides power-gating controllers for SoC and CPU power-islands.

Required properties:
- name : Should be pmc
- compatible : Should contain one of the following:
	For Tegra20 must contain "nvidia,tegra20-pmc".
	For Tegra30 must contain "nvidia,tegra30-pmc".
	For Tegra114 must contain "nvidia,tegra114-pmc"
	For Tegra124 must contain "nvidia,tegra124-pmc"
	For Tegra132 must contain "nvidia,tegra124-pmc"
	For Tegra210 must contain "nvidia,tegra210-pmc"
- reg : Offset and length of the register set for the device
- clocks : Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
  "pclk" (The Tegra clock of that name),
  "clk32k_in" (The 32KHz clock input to Tegra).

Optional properties:
- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
  The PMU is an external Power Management Unit, whose interrupt output
  signal is fed into the PMC. This signal is optionally inverted, and then
  fed into the ARM GIC. The PMC is not involved in the detection or
  handling of this interrupt signal, merely its inversion.
- nvidia,suspend-mode : The suspend mode that the platform should use.
  Valid values are 0, 1 and 2:
  0 (LP0): CPU + Core voltage off and DRAM in self-refresh
  1 (LP1): CPU voltage off and DRAM in self-refresh
  2 (LP2): CPU voltage off
- nvidia,core-power-req-active-high : Boolean, core power request active-high
- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
			   is enabled.

Required properties when nvidia,suspend-mode is specified:
- nvidia,cpu-pwr-good-time : CPU power good time in uS.
- nvidia,cpu-pwr-off-time : CPU power off time in uS.
- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
			      Core power good time in uS.
- nvidia,core-pwr-off-time : Core power off time in uS.

Required properties when nvidia,suspend-mode=<0>:
- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
  The LP0 vector contains the warm boot code that is executed by AVP when
  resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
  processor and always being the first boot processor when chip is power on
  or resume from deep sleep mode. When the system is resumed from the deep
  sleep mode, the warm boot code will restore some PLLs, clocks and then
  bring up CPU0 for resuming the system.

Hardware-triggered thermal reset:
On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
hardware-triggered thermal reset will be enabled.

Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
                             described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
                             Tegra K1 Technical Reference Manual.
- nvidia,bus-addr : Bus address of the PMU on the I2C bus
- nvidia,reg-addr : I2C register address to write poweroff command to
- nvidia,reg-data : Poweroff command to write to PMU

Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
                     Defaults to 0. Valid values are described in section 12.5.2
                     "Pinmux Support" of the Tegra4 Technical Reference Manual.

Optional nodes:
- powergates : This node contains a hierarchy of power domain nodes, which
	       should match the powergates on the Tegra SoC. See "Powergate
	       Nodes" below.

Example:

/ SoC dts including file
pmc@7000f400 {
	compatible = "nvidia,tegra20-pmc";
	reg = <0x7000e400 0x400>;
	clocks = <&tegra_car 110>, <&clk32k_in>;
	clock-names = "pclk", "clk32k_in";
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <2000>;
	nvidia,cpu-pwr-off-time = <100>;
	nvidia,core-pwr-good-time = <3845 3845>;
	nvidia,core-pwr-off-time = <458>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;
	nvidia,lp0-vec = <0xbdffd000 0x2000>;
};

/ Tegra board dts file
{
	...
	pmc@7000f400 {
		i2c-thermtrip {
			nvidia,i2c-controller-id = <4>;
			nvidia,bus-addr = <0x40>;
			nvidia,reg-addr = <0x36>;
			nvidia,reg-data = <0x2>;
		};
	};
	...
	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		clk32k_in: clock {
			compatible = "fixed-clock";
			reg=<0>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};
	...
};


== Powergate Nodes ==

Each of the powergate nodes represents a power-domain on the Tegra SoC
that can be power-gated by the Tegra PMC. The name of the powergate node
should be one of the below. Note that not every powergate is applicable
to all Tegra devices and the following list shows which powergates are
applicable to which devices. Please refer to the Tegra TRM for more
details on the various powergates.

 Name		Description			Devices Applicable
 3d		3D Graphics			Tegra20/114/124/210
 3d0		3D Graphics 0			Tegra30
 3d1		3D Graphics 1			Tegra30
 aud		Audio				Tegra210
 dfd		Debug				Tegra210
 dis		Display A			Tegra114/124/210
 disb		Display B			Tegra114/124/210
 heg		2D Graphics			Tegra30/114/124/210
 iram		Internal RAM			Tegra124/210
 mpe		MPEG Encode			All
 nvdec		NVIDIA Video Decode Engine	Tegra210
 nvjpg		NVIDIA JPEG Engine		Tegra210
 pcie		PCIE				Tegra20/30/124/210
 sata		SATA				Tegra30/124/210
 sor		Display interfaces		Tegra124/210
 ve2		Video Encode Engine 2		Tegra210
 venc		Video Encode Engine		All
 vdec		Video Decode Engine		Tegra20/30/114/124
 vic		Video Imaging Compositor	Tegra124/210
 xusba		USB Partition A			Tegra114/124/210
 xusbb		USB Partition B 		Tegra114/124/210
 xusbc		USB Partition C			Tegra114/124/210

Required properties:
  - clocks: Must contain an entry for each clock required by the PMC for
    controlling a power-gate. See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each reset required by the PMC for
    controlling a power-gate. See ../reset/reset.txt for details.
  - #power-domain-cells: Must be 0.

Example:

	pmc: pmc@7000e400 {
		compatible = "nvidia,tegra210-pmc";
		reg = <0x0 0x7000e400 0x0 0x400>;
		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";

		powergates {
			pd_audio: aud {
				clocks = <&tegra_car TEGRA210_CLK_APE>,
					 <&tegra_car TEGRA210_CLK_APB2APE>;
				resets = <&tegra_car 198>;
				#power-domain-cells = <0>;
			};
		};
	};


== Powergate Clients ==

Hardware blocks belonging to a power domain should contain a "power-domains"
property that is a phandle pointing to the corresponding powergate node.

Example:

	adma: adma@702e2000 {
		...
		power-domains = <&pd_audio>;
		...
	};

== Pad Control ==

On Tegra SoCs a pad is a set of pins which are configured as a group.
The pin grouping is a fixed attribute of the hardware. The PMC can be
used to set pad power state and signaling voltage. A pad can be either
in active or power down mode. The support for power state and signaling
voltage configuration varies depending on the pad in question. 3.3 V and
1.8 V signaling voltages are supported on pins where software
controllable signaling voltage switching is available.

The pad configuration state nodes are placed under the pmc node and they
are referred to by the pinctrl client properties. For more information
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
The pad name should be used as the value of the pins property in pin
configuration nodes.

The following pads are present on Tegra124 and Tegra132:
audio		bb		cam		comp
csia		csb		cse		dsi
dsib		dsic		dsid		hdmi
hsic		hv		lvds		mipi-bias
nand		pex-bias	pex-clk1	pex-clk2
pex-cntrl	sdmmc1		sdmmc3		sdmmc4
sys_ddc		uart		usb0		usb1
usb2		usb_bias

The following pads are present on Tegra210:
audio		audio-hv	cam		csia
csib		csic		csid		csie
csif		dbg		debug-nonao	dmic
dp		dsi		dsib		dsic
dsid		emmc		emmc2		gpio
hdmi		hsic		lvds		mipi-bias
pex-bias	pex-clk1	pex-clk2	pex-cntrl
sdmmc1		sdmmc3		spi		spi-hv
uart		usb0		usb1		usb2
usb3		usb-bias

Required pin configuration properties:
  - pins: Must contain name of the pad(s) to be configured.

Optional pin configuration properties:
  - low-power-enable: Configure the pad into power down mode
  - low-power-disable: Configure the pad into active mode
  - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
    or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
    The values are defined in
    include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.

Note: The power state can be configured on all of the Tegra124 and
      Tegra132 pads. None of the Tegra124 or Tegra132 pads support
      signaling voltage switching.

Note: All of the listed Tegra210 pads except pex-cntrl support power
      state configuration. Signaling voltage switching is supported on
      following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
      pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.

Pad configuration state example:
	pmc: pmc@7000e400 {
		compatible = "nvidia,tegra210-pmc";
		reg = <0x0 0x7000e400 0x0 0x400>;
		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";

		...

		sdmmc1_3v3: sdmmc1-3v3 {
			pins = "sdmmc1";
			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
		};

		sdmmc1_1v8: sdmmc1-1v8 {
			pins = "sdmmc1";
			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
		};

		hdmi_off: hdmi-off {
			pins = "hdmi";
			low-power-enable;
		}

		hdmi_on: hdmi-on {
			pins = "hdmi";
			low-power-disable;
		}
	};

Pinctrl client example:
	sdmmc1: sdhci@700b0000 {
		...
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
		pinctrl-0 = <&sdmmc1_3v3>;
		pinctrl-1 = <&sdmmc1_1v8>;
	};
	...
	sor@54540000 {
		...
		pinctrl-0 = <&hdmi_off>;
		pinctrl-1 = <&hdmi_on>;
		pinctrl-names = "hdmi-on", "hdmi-off";
	};
Commit	Line	Data
d17adfdb SW	1	NVIDIA Tegra Power Management Controller (PMC)
d17adfdb SW	2
b5c46cef JH	3	== Power Management Controller Node ==
b5c46cef JH	4
4b51ccbc JL	5	The PMC block interacts with an external Power Management Unit. The PMC
	6	mostly controls the entry and exit of the system from different sleep
	7	modes. It provides power-gating controllers for SoC and CPU power-islands.
	8
7021d122	9	Required properties:
d17adfdb	10	- name : Should be pmc
605aa5e4 JH	11	- compatible : Should contain one of the following:
	12	For Tegra20 must contain "nvidia,tegra20-pmc".
	13	For Tegra30 must contain "nvidia,tegra30-pmc".
	14	For Tegra114 must contain "nvidia,tegra114-pmc"
	15	For Tegra124 must contain "nvidia,tegra124-pmc"
	16	For Tegra132 must contain "nvidia,tegra124-pmc"
	17	For Tegra210 must contain "nvidia,tegra210-pmc"
d17adfdb	18	- reg : Offset and length of the register set for the device
7021d122	19	- clocks : Must contain an entry for each entry in clock-names.
d8f64797	20	See ../clocks/clock-bindings.txt for details.
7021d122 JL	21	- clock-names : Must include the following entries:
	22	"pclk" (The Tegra clock of that name),
	23	"clk32k_in" (The 32KHz clock input to Tegra).
	24
	25	Optional properties:
d17adfdb SW	26	- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
	27	The PMU is an external Power Management Unit, whose interrupt output
	28	signal is fed into the PMC. This signal is optionally inverted, and then
	29	fed into the ARM GIC. The PMC is not involved in the detection or
	30	handling of this interrupt signal, merely its inversion.
4b51ccbc JL	31	- nvidia,suspend-mode : The suspend mode that the platform should use.
	32	Valid values are 0, 1 and 2:
	33	0 (LP0): CPU + Core voltage off and DRAM in self-refresh
	34	1 (LP1): CPU voltage off and DRAM in self-refresh
	35	2 (LP2): CPU voltage off
	36	- nvidia,core-power-req-active-high : Boolean, core power request active-high
	37	- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
	38	- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
	39	- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
	40	is enabled.
	41
	42	Required properties when nvidia,suspend-mode is specified:
	43	- nvidia,cpu-pwr-good-time : CPU power good time in uS.
	44	- nvidia,cpu-pwr-off-time : CPU power off time in uS.
	45	- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
	46	Core power good time in uS.
	47	- nvidia,core-pwr-off-time : Core power off time in uS.
	48
	49	Required properties when nvidia,suspend-mode=<0>:
	50	- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
	51	The LP0 vector contains the warm boot code that is executed by AVP when
	52	resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
	53	processor and always being the first boot processor when chip is power on
	54	or resume from deep sleep mode. When the system is resumed from the deep
	55	sleep mode, the warm boot code will restore some PLLs, clocks and then
	56	bring up CPU0 for resuming the system.
d17adfdb	57
f58d4725 MP	58	Hardware-triggered thermal reset:
	59	On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
	60	hardware-triggered thermal reset will be enabled.
	61
	62	Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
	63	- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
	64	described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
	65	Tegra K1 Technical Reference Manual.
	66	- nvidia,bus-addr : Bus address of the PMU on the I2C bus
	67	- nvidia,reg-addr : I2C register address to write poweroff command to
	68	- nvidia,reg-data : Poweroff command to write to PMU
	69
	70	Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
	71	- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
	72	Defaults to 0. Valid values are described in section 12.5.2
	73	"Pinmux Support" of the Tegra4 Technical Reference Manual.
	74
b5c46cef JH	75	Optional nodes:
	76	- powergates : This node contains a hierarchy of power domain nodes, which
	77	should match the powergates on the Tegra SoC. See "Powergate
	78	Nodes" below.
	79
d17adfdb SW	80	Example:
d17adfdb SW	81
7021d122	82	/ SoC dts including file
d17adfdb SW	83	pmc@7000f400 {
	84	compatible = "nvidia,tegra20-pmc";
	85	reg = <0x7000e400 0x400>;
7021d122 JL	86	clocks = <&tegra_car 110>, <&clk32k_in>;
7021d122 JL	87	clock-names = "pclk", "clk32k_in";
d17adfdb	88	nvidia,invert-interrupt;
4b51ccbc JL	89	nvidia,suspend-mode = <1>;
	90	nvidia,cpu-pwr-good-time = <2000>;
	91	nvidia,cpu-pwr-off-time = <100>;
	92	nvidia,core-pwr-good-time = <3845 3845>;
	93	nvidia,core-pwr-off-time = <458>;
	94	nvidia,core-power-req-active-high;
	95	nvidia,sys-clock-req-active-high;
	96	nvidia,lp0-vec = <0xbdffd000 0x2000>;
d17adfdb	97	};
7021d122 JL	98
	99	/ Tegra board dts file
	100	{
f58d4725 MP	101	...
	102	pmc@7000f400 {
	103	i2c-thermtrip {
	104	nvidia,i2c-controller-id = <4>;
	105	nvidia,bus-addr = <0x40>;
	106	nvidia,reg-addr = <0x36>;
	107	nvidia,reg-data = <0x2>;
	108	};
	109	};
7021d122 JL	110	...
	111	clocks {
	112	compatible = "simple-bus";
	113	#address-cells = <1>;
	114	#size-cells = <0>;
	115
	116	clk32k_in: clock {
	117	compatible = "fixed-clock";
	118	reg=<0>;
	119	#clock-cells = <0>;
	120	clock-frequency = <32768>;
	121	};
	122	};
	123	...
	124	};
b5c46cef JH	125
	126
	127	== Powergate Nodes ==
	128
	129	Each of the powergate nodes represents a power-domain on the Tegra SoC
	130	that can be power-gated by the Tegra PMC. The name of the powergate node
	131	should be one of the below. Note that not every powergate is applicable
	132	to all Tegra devices and the following list shows which powergates are
	133	applicable to which devices. Please refer to the Tegra TRM for more
	134	details on the various powergates.
	135
	136	Name Description Devices Applicable
	137	3d 3D Graphics Tegra20/114/124/210
	138	3d0 3D Graphics 0 Tegra30
	139	3d1 3D Graphics 1 Tegra30
	140	aud Audio Tegra210
	141	dfd Debug Tegra210
	142	dis Display A Tegra114/124/210
	143	disb Display B Tegra114/124/210
	144	heg 2D Graphics Tegra30/114/124/210
	145	iram Internal RAM Tegra124/210
	146	mpe MPEG Encode All
	147	nvdec NVIDIA Video Decode Engine Tegra210
	148	nvjpg NVIDIA JPEG Engine Tegra210
	149	pcie PCIE Tegra20/30/124/210
	150	sata SATA Tegra30/124/210
	151	sor Display interfaces Tegra124/210
	152	ve2 Video Encode Engine 2 Tegra210
	153	venc Video Encode Engine All
	154	vdec Video Decode Engine Tegra20/30/114/124
	155	vic Video Imaging Compositor Tegra124/210
	156	xusba USB Partition A Tegra114/124/210
	157	xusbb USB Partition B Tegra114/124/210
	158	xusbc USB Partition C Tegra114/124/210
	159
	160	Required properties:
	161	- clocks: Must contain an entry for each clock required by the PMC for
	162	controlling a power-gate. See ../clocks/clock-bindings.txt for details.
	163	- resets: Must contain an entry for each reset required by the PMC for
	164	controlling a power-gate. See ../reset/reset.txt for details.
	165	- #power-domain-cells: Must be 0.
	166
	167	Example:
	168
	169	pmc: pmc@7000e400 {
	170	compatible = "nvidia,tegra210-pmc";
	171	reg = <0x0 0x7000e400 0x0 0x400>;
	172	clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
	173	clock-names = "pclk", "clk32k_in";
	174
	175	powergates {
	176	pd_audio: aud {
	177	clocks = <&tegra_car TEGRA210_CLK_APE>,
	178	<&tegra_car TEGRA210_CLK_APB2APE>;
	179	resets = <&tegra_car 198>;
	180	#power-domain-cells = <0>;
	181	};
	182	};
	183	};
	184
	185
	186	== Powergate Clients ==
	187
	188	Hardware blocks belonging to a power domain should contain a "power-domains"
189	property that is a phandle pointing to the corresponding powergate node.
190
191	Example:
192
193	adma: adma@702e2000 {
194	...
195	power-domains = <&pd_audio>;
196	...
197	};
d9be10ed AV	198
	199	== Pad Control ==
	200
	201	On Tegra SoCs a pad is a set of pins which are configured as a group.
	202	The pin grouping is a fixed attribute of the hardware. The PMC can be
	203	used to set pad power state and signaling voltage. A pad can be either
	204	in active or power down mode. The support for power state and signaling
	205	voltage configuration varies depending on the pad in question. 3.3 V and
	206	1.8 V signaling voltages are supported on pins where software
	207	controllable signaling voltage switching is available.
	208
	209	The pad configuration state nodes are placed under the pmc node and they
	210	are referred to by the pinctrl client properties. For more information
	211	see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
	212	The pad name should be used as the value of the pins property in pin
	213	configuration nodes.
	214
	215	The following pads are present on Tegra124 and Tegra132:
	216	audio bb cam comp
	217	csia csb cse dsi
	218	dsib dsic dsid hdmi
	219	hsic hv lvds mipi-bias
	220	nand pex-bias pex-clk1 pex-clk2
	221	pex-cntrl sdmmc1 sdmmc3 sdmmc4
	222	sys_ddc uart usb0 usb1
	223	usb2 usb_bias
	224
	225	The following pads are present on Tegra210:
	226	audio audio-hv cam csia
	227	csib csic csid csie
	228	csif dbg debug-nonao dmic
	229	dp dsi dsib dsic
	230	dsid emmc emmc2 gpio
	231	hdmi hsic lvds mipi-bias
	232	pex-bias pex-clk1 pex-clk2 pex-cntrl
	233	sdmmc1 sdmmc3 spi spi-hv
	234	uart usb0 usb1 usb2
	235	usb3 usb-bias
	236
	237	Required pin configuration properties:
	238	- pins: Must contain name of the pad(s) to be configured.
	239
	240	Optional pin configuration properties:
	241	- low-power-enable: Configure the pad into power down mode
	242	- low-power-disable: Configure the pad into active mode
	243	- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
	244	or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
	245	The values are defined in
	246	include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
	247
	248	Note: The power state can be configured on all of the Tegra124 and
	249	Tegra132 pads. None of the Tegra124 or Tegra132 pads support
	250	signaling voltage switching.
	251
	252	Note: All of the listed Tegra210 pads except pex-cntrl support power
	253	state configuration. Signaling voltage switching is supported on
	254	following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
	255	pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.
	256
	257	Pad configuration state example:
	258	pmc: pmc@7000e400 {
	259	compatible = "nvidia,tegra210-pmc";
	260	reg = <0x0 0x7000e400 0x0 0x400>;
	261	clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
262	clock-names = "pclk", "clk32k_in";
263
264	...
265
266	sdmmc1_3v3: sdmmc1-3v3 {
267	pins = "sdmmc1";
268	power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
269	};
270
271	sdmmc1_1v8: sdmmc1-1v8 {
272	pins = "sdmmc1";
273	power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
274	};
275
276	hdmi_off: hdmi-off {
277	pins = "hdmi";
278	low-power-enable;
279	}
280
281	hdmi_on: hdmi-on {
282	pins = "hdmi";
283	low-power-disable;
284	}
285	};
286
287	Pinctrl client example:
288	sdmmc1: sdhci@700b0000 {
289	...
290	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
291	pinctrl-0 = <&sdmmc1_3v3>;
292	pinctrl-1 = <&sdmmc1_1v8>;
293	};
294	...
295	sor@54540000 {
296	...
297	pinctrl-0 = <&hdmi_off>;
298	pinctrl-1 = <&hdmi_on>;
299	pinctrl-names = "hdmi-on", "hdmi-off";
300	};