Commit | Line | Data |
---|---|---|
e73c34c3 MR |
1 | * ARM Performance Monitor Units |
2 | ||
3 | ARM cores often have a PMU for counting cpu and cache events like cache misses | |
4 | and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU | |
5 | representation in the device tree should be done as under:- | |
6 | ||
7 | Required properties: | |
8 | ||
9 | - compatible : should be one of | |
f04bda90 | 10 | "arm,armv8-pmuv3" |
50243efd | 11 | "arm,cortex-a15-pmu" |
e73c34c3 MR |
12 | "arm,cortex-a9-pmu" |
13 | "arm,cortex-a8-pmu" | |
50243efd WD |
14 | "arm,cortex-a7-pmu" |
15 | "arm,cortex-a5-pmu" | |
16 | "arm,arm11mpcore-pmu" | |
e73c34c3 MR |
17 | "arm,arm1176-pmu" |
18 | "arm,arm1136-pmu" | |
19 | - interrupts : 1 combined interrupt or 1 per core. | |
20 | ||
21 | Example: | |
22 | ||
23 | pmu { | |
24 | compatible = "arm,cortex-a9-pmu"; | |
25 | interrupts = <100 101>; | |
26 | }; |