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9eb67f10 SH |
1 | Mediatek topckgen controller |
2 | ============================ | |
3 | ||
4 | The Mediatek topckgen controller provides various clocks to the system. | |
5 | ||
6 | Required Properties: | |
7 | ||
6a588703 JL |
8 | - compatible: Should be one of: |
9 | - "mediatek,mt2701-topckgen" | |
eb522df4 | 10 | - "mediatek,mt2712-topckgen", "syscon" |
2b51f514 | 11 | - "mediatek,mt6797-topckgen" |
808ecf4a | 12 | - "mediatek,mt7622-topckgen" |
9eb67f10 SH |
13 | - "mediatek,mt8135-topckgen" |
14 | - "mediatek,mt8173-topckgen" | |
15 | - #clock-cells: Must be 1 | |
16 | ||
17 | The topckgen controller uses the common clk binding from | |
18 | Documentation/devicetree/bindings/clock/clock-bindings.txt | |
19 | The available clocks are defined in dt-bindings/clock/mt*-clk.h. | |
20 | ||
21 | Example: | |
22 | ||
c4b6c26e | 23 | topckgen: power-controller@10000000 { |
9eb67f10 SH |
24 | compatible = "mediatek,mt8173-topckgen"; |
25 | reg = <0 0x10000000 0 0x1000>; | |
26 | #clock-cells = <1>; | |
27 | }; |