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9eb67f10 SH |
1 | Mediatek pericfg controller |
2 | =========================== | |
3 | ||
4 | The Mediatek pericfg controller provides various clocks and reset | |
5 | outputs to the system. | |
6 | ||
7 | Required Properties: | |
8 | ||
6a588703 JL |
9 | - compatible: Should be one of: |
10 | - "mediatek,mt2701-pericfg", "syscon" | |
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11 | - "mediatek,mt8135-pericfg", "syscon" |
12 | - "mediatek,mt8173-pericfg", "syscon" | |
13 | - #clock-cells: Must be 1 | |
14 | - #reset-cells: Must be 1 | |
15 | ||
16 | The pericfg controller uses the common clk binding from | |
17 | Documentation/devicetree/bindings/clock/clock-bindings.txt | |
18 | The available clocks are defined in dt-bindings/clock/mt*-clk.h. | |
19 | Also it uses the common reset controller binding from | |
20 | Documentation/devicetree/bindings/reset/reset.txt. | |
21 | The available reset outputs are defined in | |
967313e2 | 22 | dt-bindings/reset/mt*-resets.h |
9eb67f10 SH |
23 | |
24 | Example: | |
25 | ||
c4b6c26e | 26 | pericfg: power-controller@10003000 { |
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27 | compatible = "mediatek,mt8173-pericfg", "syscon"; |
28 | reg = <0 0x10003000 0 0x1000>; | |
29 | #clock-cells = <1>; | |
30 | #reset-cells = <1>; | |
31 | }; |