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c6c2ee00 DA |
1 | NXP i.MX System Controller Firmware (SCFW) |
2 | -------------------------------------------------------------------- | |
3 | ||
4 | The System Controller Firmware (SCFW) is a low-level system function | |
5 | which runs on a dedicated Cortex-M core to provide power, clock, and | |
6 | resource management. It exists on some i.MX8 processors. e.g. i.MX8QM | |
7 | (QM, QP), and i.MX8QX (QXP, DX). | |
8 | ||
9 | The AP communicates with the SC using a multi-ported MU module found | |
10 | in the LSIO subsystem. The current definition of this MU module provides | |
11 | 5 remote AP connections to the SC to support up to 5 execution environments | |
12 | (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces | |
13 | with the LSIO DSC IP bus. The SC firmware will communicate with this MU | |
14 | using the MSI bus. | |
15 | ||
16 | System Controller Device Node: | |
17 | ============================================================ | |
18 | ||
19 | The scu node with the following properties shall be under the /firmware/ node. | |
20 | ||
21 | Required properties: | |
22 | ------------------- | |
23 | - compatible: should be "fsl,imx-scu". | |
24 | - mbox-names: should include "tx0", "tx1", "tx2", "tx3", | |
9ad593bc AH |
25 | "rx0", "rx1", "rx2", "rx3"; |
26 | include "gip3" if want to support general MU interrupt. | |
27 | - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for | |
28 | rx, and 1 optional MU channel for general interrupt. | |
29 | All MU channels must be in the same MU instance. | |
c6c2ee00 DA |
30 | Cross instances are not allowed. The MU instance can only |
31 | be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need | |
32 | to make sure use the one which is not conflict with other | |
33 | execution environments. e.g. ATF. | |
34 | Note: | |
35 | Channel 0 must be "tx0" or "rx0". | |
36 | Channel 1 must be "tx1" or "rx1". | |
37 | Channel 2 must be "tx2" or "rx2". | |
38 | Channel 3 must be "tx3" or "rx3". | |
9ad593bc | 39 | General interrupt rx channel must be "gip3". |
c6c2ee00 DA |
40 | e.g. |
41 | mboxes = <&lsio_mu1 0 0 | |
42 | &lsio_mu1 0 1 | |
43 | &lsio_mu1 0 2 | |
44 | &lsio_mu1 0 3 | |
45 | &lsio_mu1 1 0 | |
46 | &lsio_mu1 1 1 | |
47 | &lsio_mu1 1 2 | |
9ad593bc AH |
48 | &lsio_mu1 1 3 |
49 | &lsio_mu1 3 3>; | |
c6c2ee00 DA |
50 | See Documentation/devicetree/bindings/mailbox/fsl,mu.txt |
51 | for detailed mailbox binding. | |
52 | ||
9ad593bc AH |
53 | Note: Each mu which supports general interrupt should have an alias correctly |
54 | numbered in "aliases" node. | |
55 | e.g. | |
56 | aliases { | |
57 | mu1 = &lsio_mu1; | |
58 | }; | |
59 | ||
c6c2ee00 DA |
60 | i.MX SCU Client Device Node: |
61 | ============================================================ | |
62 | ||
63 | Client nodes are maintained as children of the relevant IMX-SCU device node. | |
64 | ||
65 | Power domain bindings based on SCU Message Protocol | |
66 | ------------------------------------------------------------ | |
67 | ||
68 | This binding for the SCU power domain providers uses the generic power | |
69 | domain binding[2]. | |
70 | ||
71 | Required properties: | |
d80eebeb | 72 | - compatible: Should be one of: |
8ae170cf | 73 | "fsl,imx8qm-scu-pd", |
d80eebeb AD |
74 | "fsl,imx8qxp-scu-pd" |
75 | followed by "fsl,scu-pd" | |
76 | ||
d357b313 D |
77 | - #power-domain-cells: Must be 1. Contains the Resource ID used by |
78 | SCU commands. | |
c6c2ee00 | 79 | See detailed Resource ID list from: |
d357b313 | 80 | include/dt-bindings/firmware/imx/rsrc.h |
c6c2ee00 DA |
81 | |
82 | Clock bindings based on SCU Message Protocol | |
83 | ------------------------------------------------------------ | |
84 | ||
85 | This binding uses the common clock binding[1]. | |
86 | ||
87 | Required properties: | |
95f2aac6 | 88 | - compatible: Should be one of: |
2a005397 | 89 | "fsl,imx8qm-clock" |
95f2aac6 AD |
90 | "fsl,imx8qxp-clock" |
91 | followed by "fsl,scu-clk" | |
c6c2ee00 DA |
92 | - #clock-cells: Should be 1. Contains the Clock ID value. |
93 | - clocks: List of clock specifiers, must contain an entry for | |
94 | each required entry in clock-names | |
95 | - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" | |
96 | ||
97 | The clock consumer should specify the desired clock by having the clock | |
98 | ID in its "clocks" phandle cell. | |
99 | ||
100 | See the full list of clock IDs from: | |
101 | include/dt-bindings/clock/imx8qxp-clock.h | |
102 | ||
103 | Pinctrl bindings based on SCU Message Protocol | |
104 | ------------------------------------------------------------ | |
105 | ||
106 | This binding uses the i.MX common pinctrl binding[3]. | |
107 | ||
108 | Required properties: | |
88cc9fc4 AD |
109 | - compatible: Should be one of: |
110 | "fsl,imx8qm-iomuxc", | |
111 | "fsl,imx8qxp-iomuxc". | |
c6c2ee00 DA |
112 | |
113 | Required properties for Pinctrl sub nodes: | |
114 | - fsl,pins: Each entry consists of 3 integers which represents | |
115 | the mux and config setting for one pin. The first 2 | |
116 | integers <pin_id mux_mode> are specified using a | |
117 | PIN_FUNC_ID macro, which can be found in | |
88cc9fc4 | 118 | <dt-bindings/pinctrl/pads-imx8qm.h>, |
c6c2ee00 DA |
119 | <dt-bindings/pinctrl/pads-imx8qxp.h>. |
120 | The last integer CONFIG is the pad setting value like | |
121 | pull-up on this pin. | |
122 | ||
123 | Please refer to i.MX8QXP Reference Manual for detailed | |
124 | CONFIG settings. | |
125 | ||
126 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
127 | [2] Documentation/devicetree/bindings/power/power_domain.txt | |
128 | [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt | |
129 | ||
2ea44ca1 AH |
130 | RTC bindings based on SCU Message Protocol |
131 | ------------------------------------------------------------ | |
132 | ||
133 | Required properties: | |
134 | - compatible: should be "fsl,imx8qxp-sc-rtc"; | |
135 | ||
c2a6ea23 PF |
136 | OCOTP bindings based on SCU Message Protocol |
137 | ------------------------------------------------------------ | |
138 | Required properties: | |
e3fd9d36 FD |
139 | - compatible: Should be one of: |
140 | "fsl,imx8qm-scu-ocotp", | |
141 | "fsl,imx8qxp-scu-ocotp". | |
c2a6ea23 PF |
142 | - #address-cells: Must be 1. Contains byte index |
143 | - #size-cells: Must be 1. Contains byte length | |
144 | ||
145 | Optional Child nodes: | |
146 | ||
147 | - Data cells of ocotp: | |
148 | Detailed bindings are described in bindings/nvmem/nvmem.txt | |
149 | ||
8c21ead3 AH |
150 | Watchdog bindings based on SCU Message Protocol |
151 | ------------------------------------------------------------ | |
152 | ||
153 | Required properties: | |
154 | - compatible: should be: | |
155 | "fsl,imx8qxp-sc-wdt" | |
156 | followed by "fsl,imx-sc-wdt"; | |
157 | Optional properties: | |
158 | - timeout-sec: contains the watchdog timeout in seconds. | |
159 | ||
688f1dfb AH |
160 | SCU key bindings based on SCU Message Protocol |
161 | ------------------------------------------------------------ | |
162 | ||
163 | Required properties: | |
164 | - compatible: should be: | |
165 | "fsl,imx8qxp-sc-key" | |
166 | followed by "fsl,imx-sc-key"; | |
167 | - linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt | |
168 | ||
c6c2ee00 DA |
169 | Example (imx8qxp): |
170 | ------------- | |
9ad593bc AH |
171 | aliases { |
172 | mu1 = &lsio_mu1; | |
173 | }; | |
174 | ||
c6c2ee00 DA |
175 | lsio_mu1: mailbox@5d1c0000 { |
176 | ... | |
177 | #mbox-cells = <2>; | |
178 | }; | |
179 | ||
180 | firmware { | |
181 | scu { | |
182 | compatible = "fsl,imx-scu"; | |
183 | mbox-names = "tx0", "tx1", "tx2", "tx3", | |
9ad593bc AH |
184 | "rx0", "rx1", "rx2", "rx3", |
185 | "gip3"; | |
c6c2ee00 DA |
186 | mboxes = <&lsio_mu1 0 0 |
187 | &lsio_mu1 0 1 | |
188 | &lsio_mu1 0 2 | |
189 | &lsio_mu1 0 3 | |
190 | &lsio_mu1 1 0 | |
191 | &lsio_mu1 1 1 | |
192 | &lsio_mu1 1 2 | |
9ad593bc AH |
193 | &lsio_mu1 1 3 |
194 | &lsio_mu1 3 3>; | |
c6c2ee00 DA |
195 | |
196 | clk: clk { | |
95f2aac6 | 197 | compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; |
c6c2ee00 DA |
198 | #clock-cells = <1>; |
199 | }; | |
200 | ||
201 | iomuxc { | |
202 | compatible = "fsl,imx8qxp-iomuxc"; | |
203 | ||
204 | pinctrl_lpuart0: lpuart0grp { | |
205 | fsl,pins = < | |
206 | SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 | |
207 | SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 | |
208 | >; | |
209 | }; | |
210 | ... | |
211 | }; | |
212 | ||
c2a6ea23 PF |
213 | ocotp: imx8qx-ocotp { |
214 | compatible = "fsl,imx8qxp-scu-ocotp"; | |
215 | #address-cells = <1>; | |
216 | #size-cells = <1>; | |
217 | ||
218 | fec_mac0: mac@2c4 { | |
219 | reg = <0x2c4 8>; | |
220 | }; | |
221 | }; | |
222 | ||
d357b313 | 223 | pd: imx8qx-pd { |
d80eebeb | 224 | compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; |
d357b313 | 225 | #power-domain-cells = <1>; |
c6c2ee00 | 226 | }; |
2ea44ca1 AH |
227 | |
228 | rtc: rtc { | |
229 | compatible = "fsl,imx8qxp-sc-rtc"; | |
230 | }; | |
8c21ead3 | 231 | |
688f1dfb AH |
232 | scu_key: scu-key { |
233 | compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; | |
234 | linux,keycodes = <KEY_POWER>; | |
235 | }; | |
236 | ||
8c21ead3 AH |
237 | watchdog { |
238 | compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; | |
239 | timeout-sec = <60>; | |
240 | }; | |
c6c2ee00 DA |
241 | }; |
242 | }; | |
243 | ||
244 | serial@5a060000 { | |
245 | ... | |
246 | pinctrl-names = "default"; | |
247 | pinctrl-0 = <&pinctrl_lpuart0>; | |
248 | clocks = <&clk IMX8QXP_UART0_CLK>, | |
249 | <&clk IMX8QXP_UART0_IPG_CLK>; | |
250 | clock-names = "per", "ipg"; | |
d357b313 | 251 | power-domains = <&pd IMX_SC_R_UART_0>; |
c6c2ee00 | 252 | }; |