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5a8921ba DT |
1 | .. contents:: |
2 | .. sectnum:: | |
3 | ||
4 | ======================================== | |
5 | eBPF Instruction Set Specification, v1.0 | |
6 | ======================================== | |
7 | ||
8 | This document specifies version 1.0 of the eBPF instruction set. | |
88691e9e | 9 | |
d00d5b82 DT |
10 | Documentation conventions |
11 | ========================= | |
12 | ||
2369e526 WH |
13 | For brevity and consistency, this document refers to families |
14 | of types using a shorthand syntax and refers to several expository, | |
15 | mnemonic functions when describing the semantics of instructions. | |
16 | The range of valid values for those types and the semantics of those | |
17 | functions are defined in the following subsections. | |
18 | ||
19 | Types | |
20 | ----- | |
21 | This document refers to integer types with the notation `SN` to specify | |
22 | a type's signedness (`S`) and bit width (`N`), respectively. | |
23 | ||
24 | .. table:: Meaning of signedness notation. | |
25 | ||
26 | ==== ========= | |
27 | `S` Meaning | |
28 | ==== ========= | |
29 | `u` unsigned | |
30 | `s` signed | |
31 | ==== ========= | |
32 | ||
33 | .. table:: Meaning of bit-width notation. | |
34 | ||
35 | ===== ========= | |
36 | `N` Bit width | |
37 | ===== ========= | |
38 | `8` 8 bits | |
39 | `16` 16 bits | |
40 | `32` 32 bits | |
41 | `64` 64 bits | |
42 | `128` 128 bits | |
43 | ===== ========= | |
44 | ||
45 | For example, `u32` is a type whose valid values are all the 32-bit unsigned | |
46 | numbers and `s16` is a types whose valid values are all the 16-bit signed | |
47 | numbers. | |
48 | ||
49 | Functions | |
50 | --------- | |
51 | * `htobe16`: Takes an unsigned 16-bit number in host-endian format and | |
52 | returns the equivalent number as an unsigned 16-bit number in big-endian | |
53 | format. | |
54 | * `htobe32`: Takes an unsigned 32-bit number in host-endian format and | |
55 | returns the equivalent number as an unsigned 32-bit number in big-endian | |
56 | format. | |
57 | * `htobe64`: Takes an unsigned 64-bit number in host-endian format and | |
58 | returns the equivalent number as an unsigned 64-bit number in big-endian | |
59 | format. | |
60 | * `htole16`: Takes an unsigned 16-bit number in host-endian format and | |
61 | returns the equivalent number as an unsigned 16-bit number in little-endian | |
62 | format. | |
63 | * `htole32`: Takes an unsigned 32-bit number in host-endian format and | |
64 | returns the equivalent number as an unsigned 32-bit number in little-endian | |
65 | format. | |
66 | * `htole64`: Takes an unsigned 64-bit number in host-endian format and | |
67 | returns the equivalent number as an unsigned 64-bit number in little-endian | |
68 | format. | |
69 | * `bswap16`: Takes an unsigned 16-bit number in either big- or little-endian | |
70 | format and returns the equivalent number with the same bit width but | |
71 | opposite endianness. | |
72 | * `bswap32`: Takes an unsigned 32-bit number in either big- or little-endian | |
73 | format and returns the equivalent number with the same bit width but | |
74 | opposite endianness. | |
75 | * `bswap64`: Takes an unsigned 64-bit number in either big- or little-endian | |
76 | format and returns the equivalent number with the same bit width but | |
77 | opposite endianness. | |
88691e9e | 78 | |
41db511a CH |
79 | Registers and calling convention |
80 | ================================ | |
81 | ||
82 | eBPF has 10 general purpose registers and a read-only frame pointer register, | |
83 | all of which are 64-bits wide. | |
84 | ||
85 | The eBPF calling convention is defined as: | |
86 | ||
5a8921ba DT |
87 | * R0: return value from function calls, and exit value for eBPF programs |
88 | * R1 - R5: arguments for function calls | |
89 | * R6 - R9: callee saved registers that function calls will preserve | |
90 | * R10: read-only frame pointer to access stack | |
41db511a CH |
91 | |
92 | R0 - R5 are scratch registers and eBPF programs needs to spill/fill them if | |
93 | necessary across calls. | |
88691e9e | 94 | |
62e46838 CH |
95 | Instruction encoding |
96 | ==================== | |
97 | ||
5ca15b8a CH |
98 | eBPF has two instruction encodings: |
99 | ||
5a8921ba | 100 | * the basic instruction encoding, which uses 64 bits to encode an instruction |
a92adde8 DT |
101 | * the wide instruction encoding, which appends a second 64-bit immediate (i.e., |
102 | constant) value after the basic instruction for a total of 128 bits. | |
5ca15b8a | 103 | |
ae256f95 JM |
104 | The fields conforming an encoded basic instruction are stored in the |
105 | following order:: | |
62e46838 | 106 | |
ae256f95 JM |
107 | opcode:8 src_reg:4 dst_reg:4 offset:16 imm:32 // In little-endian BPF. |
108 | opcode:8 dst_reg:4 src_reg:4 offset:16 imm:32 // In big-endian BPF. | |
a92adde8 DT |
109 | |
110 | **imm** | |
111 | signed integer immediate value | |
112 | ||
113 | **offset** | |
114 | signed integer offset used with pointer arithmetic | |
115 | ||
116 | **src_reg** | |
117 | the source register number (0-10), except where otherwise specified | |
118 | (`64-bit immediate instructions`_ reuse this field for other purposes) | |
119 | ||
120 | **dst_reg** | |
121 | destination register number (0-10) | |
122 | ||
123 | **opcode** | |
124 | operation to perform | |
62e46838 | 125 | |
ae256f95 JM |
126 | Note that the contents of multi-byte fields ('imm' and 'offset') are |
127 | stored using big-endian byte ordering in big-endian BPF and | |
128 | little-endian byte ordering in little-endian BPF. | |
746ce767 | 129 | |
ae256f95 | 130 | For example:: |
746ce767 | 131 | |
ae256f95 JM |
132 | opcode offset imm assembly |
133 | src_reg dst_reg | |
134 | 07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little | |
135 | dst_reg src_reg | |
136 | 07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big | |
746ce767 | 137 | |
62e46838 CH |
138 | Note that most instructions do not use all of the fields. |
139 | Unused fields shall be cleared to zero. | |
140 | ||
a92adde8 DT |
141 | As discussed below in `64-bit immediate instructions`_, a 64-bit immediate |
142 | instruction uses a 64-bit immediate value that is constructed as follows. | |
143 | The 64 bits following the basic instruction contain a pseudo instruction | |
144 | using the same format but with opcode, dst_reg, src_reg, and offset all set to zero, | |
145 | and imm containing the high 32 bits of the immediate value. | |
146 | ||
ae256f95 JM |
147 | This is depicted in the following figure:: |
148 | ||
149 | basic_instruction | |
150 | .-----------------------------. | |
151 | | | | |
152 | code:8 regs:8 offset:16 imm:32 unused:32 imm:32 | |
153 | | | | |
154 | '--------------' | |
155 | pseudo instruction | |
a92adde8 DT |
156 | |
157 | Thus the 64-bit immediate value is constructed as follows: | |
158 | ||
159 | imm64 = (next_imm << 32) | imm | |
160 | ||
161 | where 'next_imm' refers to the imm value of the pseudo instruction | |
ae256f95 JM |
162 | following the basic instruction. The unused bytes in the pseudo |
163 | instruction are reserved and shall be cleared to zero. | |
a92adde8 | 164 | |
5e4dd19f | 165 | Instruction classes |
62e46838 | 166 | ------------------- |
88691e9e | 167 | |
5e4dd19f | 168 | The three LSB bits of the 'opcode' field store the instruction class: |
88691e9e | 169 | |
5a8921ba DT |
170 | ========= ===== =============================== =================================== |
171 | class value description reference | |
172 | ========= ===== =============================== =================================== | |
173 | BPF_LD 0x00 non-standard load operations `Load and store instructions`_ | |
174 | BPF_LDX 0x01 load into register operations `Load and store instructions`_ | |
175 | BPF_ST 0x02 store from immediate operations `Load and store instructions`_ | |
176 | BPF_STX 0x03 store from register operations `Load and store instructions`_ | |
177 | BPF_ALU 0x04 32-bit arithmetic operations `Arithmetic and jump instructions`_ | |
178 | BPF_JMP 0x05 64-bit jump operations `Arithmetic and jump instructions`_ | |
179 | BPF_JMP32 0x06 32-bit jump operations `Arithmetic and jump instructions`_ | |
180 | BPF_ALU64 0x07 64-bit arithmetic operations `Arithmetic and jump instructions`_ | |
181 | ========= ===== =============================== =================================== | |
88691e9e | 182 | |
5e4dd19f CH |
183 | Arithmetic and jump instructions |
184 | ================================ | |
185 | ||
5a8921ba DT |
186 | For arithmetic and jump instructions (``BPF_ALU``, ``BPF_ALU64``, ``BPF_JMP`` and |
187 | ``BPF_JMP32``), the 8-bit 'opcode' field is divided into three parts: | |
88691e9e | 188 | |
5a8921ba DT |
189 | ============== ====== ================= |
190 | 4 bits (MSB) 1 bit 3 bits (LSB) | |
191 | ============== ====== ================= | |
a92adde8 | 192 | code source instruction class |
5a8921ba | 193 | ============== ====== ================= |
88691e9e | 194 | |
a92adde8 DT |
195 | **code** |
196 | the operation code, whose meaning varies by instruction class | |
88691e9e | 197 | |
a92adde8 DT |
198 | **source** |
199 | the source operand location, which unless otherwise specified is one of: | |
88691e9e | 200 | |
a92adde8 DT |
201 | ====== ===== ============================================== |
202 | source value description | |
203 | ====== ===== ============================================== | |
204 | BPF_K 0x00 use 32-bit 'imm' value as source operand | |
205 | BPF_X 0x08 use 'src_reg' register value as source operand | |
206 | ====== ===== ============================================== | |
88691e9e | 207 | |
a92adde8 DT |
208 | **instruction class** |
209 | the instruction class (see `Instruction classes`_) | |
be3193cd CH |
210 | |
211 | Arithmetic instructions | |
212 | ----------------------- | |
213 | ||
5a8921ba | 214 | ``BPF_ALU`` uses 32-bit wide operands while ``BPF_ALU64`` uses 64-bit wide operands for |
be3193cd | 215 | otherwise identical operations. |
a92adde8 DT |
216 | The 'code' field encodes the operation as below, where 'src' and 'dst' refer |
217 | to the values of the source and destination registers, respectively. | |
5a8921ba | 218 | |
fb213ecb YS |
219 | ========= ===== ======= ========================================================== |
220 | code value offset description | |
221 | ========= ===== ======= ========================================================== | |
222 | BPF_ADD 0x00 0 dst += src | |
223 | BPF_SUB 0x10 0 dst -= src | |
224 | BPF_MUL 0x20 0 dst \*= src | |
225 | BPF_DIV 0x30 0 dst = (src != 0) ? (dst / src) : 0 | |
226 | BPF_SDIV 0x30 1 dst = (src != 0) ? (dst s/ src) : 0 | |
227 | BPF_OR 0x40 0 dst \|= src | |
228 | BPF_AND 0x50 0 dst &= src | |
229 | BPF_LSH 0x60 0 dst <<= (src & mask) | |
230 | BPF_RSH 0x70 0 dst >>= (src & mask) | |
231 | BPF_NEG 0x80 0 dst = -dst | |
232 | BPF_MOD 0x90 0 dst = (src != 0) ? (dst % src) : dst | |
233 | BPF_SMOD 0x90 1 dst = (src != 0) ? (dst s% src) : dst | |
234 | BPF_XOR 0xa0 0 dst ^= src | |
235 | BPF_MOV 0xb0 0 dst = src | |
236 | BPF_MOVSX 0xb0 8/16/32 dst = (s8,s16,s32)src | |
237 | BPF_ARSH 0xc0 0 sign extending dst >>= (src & mask) | |
238 | BPF_END 0xd0 0 byte swap operations (see `Byte swap instructions`_ below) | |
239 | ========= ===== ======= ========================================================== | |
5a8921ba | 240 | |
0eb9d19e DT |
241 | Underflow and overflow are allowed during arithmetic operations, meaning |
242 | the 64-bit or 32-bit value will wrap. If eBPF program execution would | |
243 | result in division by zero, the destination register is instead set to zero. | |
244 | If execution would result in modulo by zero, for ``BPF_ALU64`` the value of | |
245 | the destination register is unchanged whereas for ``BPF_ALU`` the upper | |
246 | 32 bits of the destination register are zeroed. | |
247 | ||
5a8921ba | 248 | ``BPF_ADD | BPF_X | BPF_ALU`` means:: |
be3193cd | 249 | |
a92adde8 | 250 | dst = (u32) ((u32) dst + (u32) src) |
be3193cd | 251 | |
d00d5b82 DT |
252 | where '(u32)' indicates that the upper 32 bits are zeroed. |
253 | ||
5a8921ba | 254 | ``BPF_ADD | BPF_X | BPF_ALU64`` means:: |
be3193cd | 255 | |
a92adde8 | 256 | dst = dst + src |
be3193cd | 257 | |
5a8921ba | 258 | ``BPF_XOR | BPF_K | BPF_ALU`` means:: |
be3193cd | 259 | |
a92adde8 | 260 | dst = (u32) dst ^ (u32) imm32 |
be3193cd | 261 | |
5a8921ba | 262 | ``BPF_XOR | BPF_K | BPF_ALU64`` means:: |
be3193cd | 263 | |
a92adde8 | 264 | dst = dst ^ imm32 |
be3193cd | 265 | |
ee932bf9 YS |
266 | Note that most instructions have instruction offset of 0. Only three instructions |
267 | (``BPF_SDIV``, ``BPF_SMOD``, ``BPF_MOVSX``) have a non-zero offset. | |
245d4c40 YS |
268 | |
269 | The devision and modulo operations support both unsigned and signed flavors. | |
245d4c40 | 270 | |
ee932bf9 YS |
271 | For unsigned operations (``BPF_DIV`` and ``BPF_MOD``), for ``BPF_ALU``, |
272 | 'imm' is interpreted as a 32-bit unsigned value. For ``BPF_ALU64``, | |
273 | 'imm' is first sign extended from 32 to 64 bits, and then interpreted as | |
274 | a 64-bit unsigned value. | |
275 | ||
276 | For signed operations (``BPF_SDIV`` and ``BPF_SMOD``), for ``BPF_ALU``, | |
277 | 'imm' is interpreted as a 32-bit signed value. For ``BPF_ALU64``, 'imm' | |
278 | is first sign extended from 32 to 64 bits, and then interpreted as a | |
279 | 64-bit signed value. | |
280 | ||
281 | The ``BPF_MOVSX`` instruction does a move operation with sign extension. | |
282 | ``BPF_ALU | BPF_MOVSX`` sign extends 8-bit and 16-bit operands into 32 | |
283 | bit operands, and zeroes the remaining upper 32 bits. | |
284 | ``BPF_ALU64 | BPF_MOVSX`` sign extends 8-bit, 16-bit, and 32-bit | |
285 | operands into 64 bit operands. | |
be3193cd | 286 | |
8819495a DT |
287 | Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31) |
288 | for 32-bit operations. | |
289 | ||
dd33fb57 | 290 | Byte swap instructions |
ee932bf9 | 291 | ---------------------- |
dd33fb57 | 292 | |
245d4c40 YS |
293 | The byte swap instructions use instruction classes of ``BPF_ALU`` and ``BPF_ALU64`` |
294 | and a 4-bit 'code' field of ``BPF_END``. | |
dd33fb57 | 295 | |
67b97e58 | 296 | The byte swap instructions operate on the destination register |
dd33fb57 CH |
297 | only and do not use a separate source register or immediate value. |
298 | ||
ee932bf9 YS |
299 | For ``BPF_ALU``, the 1-bit source operand field in the opcode is used to |
300 | select what byte order the operation converts from or to. For | |
301 | ``BPF_ALU64``, the 1-bit source operand field in the opcode is reserved | |
302 | and must be set to 0. | |
dd33fb57 | 303 | |
245d4c40 YS |
304 | ========= ========= ===== ================================================= |
305 | class source value description | |
306 | ========= ========= ===== ================================================= | |
307 | BPF_ALU BPF_TO_LE 0x00 convert between host byte order and little endian | |
308 | BPF_ALU BPF_TO_BE 0x08 convert between host byte order and big endian | |
ee932bf9 | 309 | BPF_ALU64 Reserved 0x00 do byte swap unconditionally |
245d4c40 | 310 | ========= ========= ===== ================================================= |
dd33fb57 | 311 | |
5a8921ba | 312 | The 'imm' field encodes the width of the swap operations. The following widths |
dd33fb57 CH |
313 | are supported: 16, 32 and 64. |
314 | ||
315 | Examples: | |
316 | ||
2369e526 | 317 | ``BPF_ALU | BPF_TO_LE | BPF_END`` with imm = 16/32/64 means:: |
dd33fb57 | 318 | |
a92adde8 | 319 | dst = htole16(dst) |
2369e526 WH |
320 | dst = htole32(dst) |
321 | dst = htole64(dst) | |
dd33fb57 | 322 | |
2369e526 | 323 | ``BPF_ALU | BPF_TO_BE | BPF_END`` with imm = 16/32/64 means:: |
dd33fb57 | 324 | |
2369e526 WH |
325 | dst = htobe16(dst) |
326 | dst = htobe32(dst) | |
a92adde8 | 327 | dst = htobe64(dst) |
dd33fb57 | 328 | |
245d4c40 YS |
329 | ``BPF_ALU64 | BPF_TO_LE | BPF_END`` with imm = 16/32/64 means:: |
330 | ||
2369e526 WH |
331 | dst = bswap16(dst) |
332 | dst = bswap32(dst) | |
333 | dst = bswap64(dst) | |
245d4c40 | 334 | |
be3193cd CH |
335 | Jump instructions |
336 | ----------------- | |
337 | ||
5a8921ba | 338 | ``BPF_JMP32`` uses 32-bit wide operands while ``BPF_JMP`` uses 64-bit wide operands for |
be3193cd | 339 | otherwise identical operations. |
5a8921ba DT |
340 | The 'code' field encodes the operation as below: |
341 | ||
8cfee110 DT |
342 | ======== ===== === =========================================== ========================================= |
343 | code value src description notes | |
344 | ======== ===== === =========================================== ========================================= | |
245d4c40 YS |
345 | BPF_JA 0x0 0x0 PC += offset BPF_JMP class |
346 | BPF_JA 0x0 0x0 PC += imm BPF_JMP32 class | |
8cfee110 DT |
347 | BPF_JEQ 0x1 any PC += offset if dst == src |
348 | BPF_JGT 0x2 any PC += offset if dst > src unsigned | |
349 | BPF_JGE 0x3 any PC += offset if dst >= src unsigned | |
350 | BPF_JSET 0x4 any PC += offset if dst & src | |
351 | BPF_JNE 0x5 any PC += offset if dst != src | |
352 | BPF_JSGT 0x6 any PC += offset if dst > src signed | |
353 | BPF_JSGE 0x7 any PC += offset if dst >= src signed | |
354 | BPF_CALL 0x8 0x0 call helper function by address see `Helper functions`_ | |
355 | BPF_CALL 0x8 0x1 call PC += offset see `Program-local functions`_ | |
356 | BPF_CALL 0x8 0x2 call helper function by BTF ID see `Helper functions`_ | |
357 | BPF_EXIT 0x9 0x0 return BPF_JMP only | |
358 | BPF_JLT 0xa any PC += offset if dst < src unsigned | |
359 | BPF_JLE 0xb any PC += offset if dst <= src unsigned | |
360 | BPF_JSLT 0xc any PC += offset if dst < src signed | |
361 | BPF_JSLE 0xd any PC += offset if dst <= src signed | |
362 | ======== ===== === =========================================== ========================================= | |
41db511a | 363 | |
be3193cd | 364 | The eBPF program needs to store the return value into register R0 before doing a |
8cfee110 | 365 | ``BPF_EXIT``. |
88691e9e | 366 | |
b9fe8e8d DT |
367 | Example: |
368 | ||
369 | ``BPF_JSGE | BPF_X | BPF_JMP32`` (0x7e) means:: | |
370 | ||
371 | if (s32)dst s>= (s32)src goto +offset | |
372 | ||
373 | where 's>=' indicates a signed '>=' comparison. | |
374 | ||
245d4c40 YS |
375 | ``BPF_JA | BPF_K | BPF_JMP32`` (0x06) means:: |
376 | ||
377 | gotol +imm | |
378 | ||
379 | where 'imm' means the branch offset comes from insn 'imm' field. | |
380 | ||
ee932bf9 YS |
381 | Note that there are two flavors of ``BPF_JA`` instructions. The |
382 | ``BPF_JMP`` class permits a 16-bit jump offset specified by the 'offset' | |
383 | field, whereas the ``BPF_JMP32`` class permits a 32-bit jump offset | |
384 | specified by the 'imm' field. A > 16-bit conditional jump may be | |
385 | converted to a < 16-bit conditional jump plus a 32-bit unconditional | |
386 | jump. | |
245d4c40 | 387 | |
c1f9e14e DT |
388 | Helper functions |
389 | ~~~~~~~~~~~~~~~~ | |
390 | ||
391 | Helper functions are a concept whereby BPF programs can call into a | |
8cfee110 DT |
392 | set of function calls exposed by the underlying platform. |
393 | ||
394 | Historically, each helper function was identified by an address | |
395 | encoded in the imm field. The available helper functions may differ | |
396 | for each program type, but address values are unique across all program types. | |
397 | ||
398 | Platforms that support the BPF Type Format (BTF) support identifying | |
399 | a helper function by a BTF ID encoded in the imm field, where the BTF ID | |
400 | identifies the helper name and type. | |
401 | ||
402 | Program-local functions | |
403 | ~~~~~~~~~~~~~~~~~~~~~~~ | |
404 | Program-local functions are functions exposed by the same BPF program as the | |
405 | caller, and are referenced by offset from the call instruction, similar to | |
406 | ``BPF_JA``. A ``BPF_EXIT`` within the program-local function will return to | |
407 | the caller. | |
88691e9e | 408 | |
5e4dd19f CH |
409 | Load and store instructions |
410 | =========================== | |
411 | ||
5a8921ba | 412 | For load and store instructions (``BPF_LD``, ``BPF_LDX``, ``BPF_ST``, and ``BPF_STX``), the |
5e4dd19f CH |
413 | 8-bit 'opcode' field is divided as: |
414 | ||
5a8921ba DT |
415 | ============ ====== ================= |
416 | 3 bits (MSB) 2 bits 3 bits (LSB) | |
417 | ============ ====== ================= | |
418 | mode size instruction class | |
419 | ============ ====== ================= | |
420 | ||
421 | The mode modifier is one of: | |
422 | ||
423 | ============= ===== ==================================== ============= | |
424 | mode modifier value description reference | |
425 | ============= ===== ==================================== ============= | |
426 | BPF_IMM 0x00 64-bit immediate instructions `64-bit immediate instructions`_ | |
427 | BPF_ABS 0x20 legacy BPF packet access (absolute) `Legacy BPF Packet access instructions`_ | |
428 | BPF_IND 0x40 legacy BPF packet access (indirect) `Legacy BPF Packet access instructions`_ | |
429 | BPF_MEM 0x60 regular load and store operations `Regular load and store operations`_ | |
245d4c40 | 430 | BPF_MEMSX 0x80 sign-extension load operations `Sign-extension load operations`_ |
5a8921ba DT |
431 | BPF_ATOMIC 0xc0 atomic operations `Atomic operations`_ |
432 | ============= ===== ==================================== ============= | |
5e4dd19f CH |
433 | |
434 | The size modifier is one of: | |
88691e9e | 435 | |
5e4dd19f CH |
436 | ============= ===== ===================== |
437 | size modifier value description | |
438 | ============= ===== ===================== | |
439 | BPF_W 0x00 word (4 bytes) | |
440 | BPF_H 0x08 half word (2 bytes) | |
441 | BPF_B 0x10 byte | |
442 | BPF_DW 0x18 double word (8 bytes) | |
443 | ============= ===== ===================== | |
88691e9e | 444 | |
63d8c242 CH |
445 | Regular load and store operations |
446 | --------------------------------- | |
447 | ||
448 | The ``BPF_MEM`` mode modifier is used to encode regular load and store | |
449 | instructions that transfer data between a register and memory. | |
450 | ||
451 | ``BPF_MEM | <size> | BPF_STX`` means:: | |
88691e9e | 452 | |
a92adde8 | 453 | *(size *) (dst + offset) = src |
88691e9e | 454 | |
63d8c242 | 455 | ``BPF_MEM | <size> | BPF_ST`` means:: |
88691e9e | 456 | |
a92adde8 | 457 | *(size *) (dst + offset) = imm32 |
5e4dd19f | 458 | |
63d8c242 | 459 | ``BPF_MEM | <size> | BPF_LDX`` means:: |
5e4dd19f | 460 | |
245d4c40 YS |
461 | dst = *(unsigned size *) (src + offset) |
462 | ||
463 | Where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW`` and | |
ee932bf9 | 464 | 'unsigned size' is one of u8, u16, u32 or u64. |
245d4c40 | 465 | |
fb213ecb YS |
466 | Sign-extension load operations |
467 | ------------------------------ | |
468 | ||
245d4c40 YS |
469 | The ``BPF_MEMSX`` mode modifier is used to encode sign-extension load |
470 | instructions that transfer data between a register and memory. | |
471 | ||
472 | ``BPF_MEMSX | <size> | BPF_LDX`` means:: | |
473 | ||
474 | dst = *(signed size *) (src + offset) | |
5e4dd19f | 475 | |
245d4c40 | 476 | Where size is one of: ``BPF_B``, ``BPF_H`` or ``BPF_W``, and |
ee932bf9 | 477 | 'signed size' is one of s8, s16 or s32. |
5e4dd19f | 478 | |
5e4dd19f CH |
479 | Atomic operations |
480 | ----------------- | |
88691e9e | 481 | |
594d3234 CH |
482 | Atomic operations are operations that operate on memory and can not be |
483 | interrupted or corrupted by other access to the same memory region | |
484 | by other eBPF programs or means outside of this specification. | |
88691e9e | 485 | |
594d3234 CH |
486 | All atomic operations supported by eBPF are encoded as store operations |
487 | that use the ``BPF_ATOMIC`` mode modifier as follows: | |
88691e9e | 488 | |
5a8921ba DT |
489 | * ``BPF_ATOMIC | BPF_W | BPF_STX`` for 32-bit operations |
490 | * ``BPF_ATOMIC | BPF_DW | BPF_STX`` for 64-bit operations | |
491 | * 8-bit and 16-bit wide atomic operations are not supported. | |
88691e9e | 492 | |
5a8921ba | 493 | The 'imm' field is used to encode the actual atomic operation. |
594d3234 | 494 | Simple atomic operation use a subset of the values defined to encode |
5a8921ba | 495 | arithmetic operations in the 'imm' field to encode the atomic operation: |
88691e9e | 496 | |
5a8921ba DT |
497 | ======== ===== =========== |
498 | imm value description | |
499 | ======== ===== =========== | |
500 | BPF_ADD 0x00 atomic add | |
501 | BPF_OR 0x40 atomic or | |
502 | BPF_AND 0x50 atomic and | |
503 | BPF_XOR 0xa0 atomic xor | |
504 | ======== ===== =========== | |
88691e9e | 505 | |
88691e9e | 506 | |
5a8921ba | 507 | ``BPF_ATOMIC | BPF_W | BPF_STX`` with 'imm' = BPF_ADD means:: |
88691e9e | 508 | |
a92adde8 | 509 | *(u32 *)(dst + offset) += src |
88691e9e | 510 | |
5a8921ba | 511 | ``BPF_ATOMIC | BPF_DW | BPF_STX`` with 'imm' = BPF ADD means:: |
88691e9e | 512 | |
a92adde8 | 513 | *(u64 *)(dst + offset) += src |
88691e9e | 514 | |
594d3234 CH |
515 | In addition to the simple atomic operations, there also is a modifier and |
516 | two complex atomic operations: | |
517 | ||
5a8921ba DT |
518 | =========== ================ =========================== |
519 | imm value description | |
520 | =========== ================ =========================== | |
521 | BPF_FETCH 0x01 modifier: return old value | |
522 | BPF_XCHG 0xe0 | BPF_FETCH atomic exchange | |
523 | BPF_CMPXCHG 0xf0 | BPF_FETCH atomic compare and exchange | |
524 | =========== ================ =========================== | |
594d3234 CH |
525 | |
526 | The ``BPF_FETCH`` modifier is optional for simple atomic operations, and | |
527 | always set for the complex atomic operations. If the ``BPF_FETCH`` flag | |
a92adde8 | 528 | is set, then the operation also overwrites ``src`` with the value that |
594d3234 CH |
529 | was in memory before it was modified. |
530 | ||
a92adde8 DT |
531 | The ``BPF_XCHG`` operation atomically exchanges ``src`` with the value |
532 | addressed by ``dst + offset``. | |
594d3234 CH |
533 | |
534 | The ``BPF_CMPXCHG`` operation atomically compares the value addressed by | |
a92adde8 DT |
535 | ``dst + offset`` with ``R0``. If they match, the value addressed by |
536 | ``dst + offset`` is replaced with ``src``. In either case, the | |
537 | value that was at ``dst + offset`` before the operation is zero-extended | |
594d3234 | 538 | and loaded back to ``R0``. |
88691e9e | 539 | |
5ca15b8a CH |
540 | 64-bit immediate instructions |
541 | ----------------------------- | |
542 | ||
5a8921ba | 543 | Instructions with the ``BPF_IMM`` 'mode' modifier use the wide instruction |
16b7c970 DT |
544 | encoding defined in `Instruction encoding`_, and use the 'src' field of the |
545 | basic instruction to hold an opcode subtype. | |
546 | ||
547 | The following table defines a set of ``BPF_IMM | BPF_DW | BPF_LD`` instructions | |
548 | with opcode subtypes in the 'src' field, using new terms such as "map" | |
549 | defined further below: | |
550 | ||
551 | ========================= ====== === ========================================= =========== ============== | |
552 | opcode construction opcode src pseudocode imm type dst type | |
553 | ========================= ====== === ========================================= =========== ============== | |
554 | BPF_IMM | BPF_DW | BPF_LD 0x18 0x0 dst = imm64 integer integer | |
555 | BPF_IMM | BPF_DW | BPF_LD 0x18 0x1 dst = map_by_fd(imm) map fd map | |
556 | BPF_IMM | BPF_DW | BPF_LD 0x18 0x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data pointer | |
557 | BPF_IMM | BPF_DW | BPF_LD 0x18 0x3 dst = var_addr(imm) variable id data pointer | |
558 | BPF_IMM | BPF_DW | BPF_LD 0x18 0x4 dst = code_addr(imm) integer code pointer | |
559 | BPF_IMM | BPF_DW | BPF_LD 0x18 0x5 dst = map_by_idx(imm) map index map | |
560 | BPF_IMM | BPF_DW | BPF_LD 0x18 0x6 dst = map_val(map_by_idx(imm)) + next_imm map index data pointer | |
561 | ========================= ====== === ========================================= =========== ============== | |
562 | ||
563 | where | |
564 | ||
565 | * map_by_fd(imm) means to convert a 32-bit file descriptor into an address of a map (see `Maps`_) | |
566 | * map_by_idx(imm) means to convert a 32-bit index into an address of a map | |
567 | * map_val(map) gets the address of the first value in a given map | |
568 | * var_addr(imm) gets the address of a platform variable (see `Platform Variables`_) with a given id | |
569 | * code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions | |
570 | * the 'imm type' can be used by disassemblers for display | |
571 | * the 'dst type' can be used for verification and JIT compilation purposes | |
572 | ||
573 | Maps | |
574 | ~~~~ | |
575 | ||
576 | Maps are shared memory regions accessible by eBPF programs on some platforms. | |
577 | A map can have various semantics as defined in a separate document, and may or | |
578 | may not have a single contiguous memory region, but the 'map_val(map)' is | |
579 | currently only defined for maps that do have a single contiguous memory region. | |
580 | ||
581 | Each map can have a file descriptor (fd) if supported by the platform, where | |
582 | 'map_by_fd(imm)' means to get the map with the specified file descriptor. Each | |
583 | BPF program can also be defined to use a set of maps associated with the | |
584 | program at load time, and 'map_by_idx(imm)' means to get the map with the given | |
585 | index in the set associated with the BPF program containing the instruction. | |
586 | ||
587 | Platform Variables | |
588 | ~~~~~~~~~~~~~~~~~~ | |
589 | ||
590 | Platform variables are memory regions, identified by integer ids, exposed by | |
591 | the runtime and accessible by BPF programs on some platforms. The | |
592 | 'var_addr(imm)' operation means to get the address of the memory region | |
593 | identified by the given id. | |
63d000c3 | 594 | |
15175336 CH |
595 | Legacy BPF Packet access instructions |
596 | ------------------------------------- | |
63d000c3 | 597 | |
6166da0a DT |
598 | eBPF previously introduced special instructions for access to packet data that were |
599 | carried over from classic BPF. However, these instructions are | |
600 | deprecated and should no longer be used. |