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1 | .. _elf_hwcaps_index: |
2 | ||
b693d0b3 | 3 | ================ |
611a7bc7 MR |
4 | ARM64 ELF hwcaps |
5 | ================ | |
6 | ||
7 | This document describes the usage and semantics of the arm64 ELF hwcaps. | |
8 | ||
9 | ||
10 | 1. Introduction | |
11 | --------------- | |
12 | ||
13 | Some hardware or software features are only available on some CPU | |
14 | implementations, and/or with certain kernel configurations, but have no | |
15 | architected discovery mechanism available to userspace code at EL0. The | |
16 | kernel exposes the presence of these features to userspace through a set | |
17 | of flags called hwcaps, exposed in the auxilliary vector. | |
18 | ||
aaba098f AM |
19 | Userspace software can test for features by acquiring the AT_HWCAP or |
20 | AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant | |
b693d0b3 | 21 | flags are set, e.g.:: |
611a7bc7 | 22 | |
b693d0b3 MCC |
23 | bool floating_point_is_present(void) |
24 | { | |
25 | unsigned long hwcaps = getauxval(AT_HWCAP); | |
26 | if (hwcaps & HWCAP_FP) | |
27 | return true; | |
611a7bc7 | 28 | |
b693d0b3 MCC |
29 | return false; |
30 | } | |
611a7bc7 MR |
31 | |
32 | Where software relies on a feature described by a hwcap, it should check | |
33 | the relevant hwcap flag to verify that the feature is present before | |
34 | attempting to make use of the feature. | |
35 | ||
36 | Features cannot be probed reliably through other means. When a feature | |
37 | is not available, attempting to use it may result in unpredictable | |
38 | behaviour, and is not guaranteed to result in any reliable indication | |
39 | that the feature is unavailable, such as a SIGILL. | |
40 | ||
41 | ||
42 | 2. Interpretation of hwcaps | |
43 | --------------------------- | |
44 | ||
45 | The majority of hwcaps are intended to indicate the presence of features | |
46 | which are described by architected ID registers inaccessible to | |
47 | userspace code at EL0. These hwcaps are defined in terms of ID register | |
48 | fields, and should be interpreted with reference to the definition of | |
49 | these fields in the ARM Architecture Reference Manual (ARM ARM). | |
50 | ||
b693d0b3 | 51 | Such hwcaps are described below in the form:: |
611a7bc7 MR |
52 | |
53 | Functionality implied by idreg.field == val. | |
54 | ||
55 | Such hwcaps indicate the availability of functionality that the ARM ARM | |
56 | defines as being present when idreg.field has value val, but do not | |
57 | indicate that idreg.field is precisely equal to val, nor do they | |
58 | indicate the absence of functionality implied by other values of | |
59 | idreg.field. | |
60 | ||
61 | Other hwcaps may indicate the presence of features which cannot be | |
62 | described by ID registers alone. These may be described without | |
63 | reference to ID registers, and may refer to other documentation. | |
64 | ||
65 | ||
66 | 3. The hwcaps exposed in AT_HWCAP | |
67 | --------------------------------- | |
68 | ||
69 | HWCAP_FP | |
611a7bc7 MR |
70 | Functionality implied by ID_AA64PFR0_EL1.FP == 0b0000. |
71 | ||
72 | HWCAP_ASIMD | |
611a7bc7 MR |
73 | Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0000. |
74 | ||
75 | HWCAP_EVTSTRM | |
611a7bc7 | 76 | The generic timer is configured to generate events at a frequency of |
5d8505fd | 77 | approximately 10KHz. |
611a7bc7 MR |
78 | |
79 | HWCAP_AES | |
4bfbe5ee | 80 | Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001. |
611a7bc7 MR |
81 | |
82 | HWCAP_PMULL | |
4bfbe5ee | 83 | Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0010. |
611a7bc7 MR |
84 | |
85 | HWCAP_SHA1 | |
611a7bc7 MR |
86 | Functionality implied by ID_AA64ISAR0_EL1.SHA1 == 0b0001. |
87 | ||
88 | HWCAP_SHA2 | |
611a7bc7 MR |
89 | Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0001. |
90 | ||
91 | HWCAP_CRC32 | |
611a7bc7 MR |
92 | Functionality implied by ID_AA64ISAR0_EL1.CRC32 == 0b0001. |
93 | ||
94 | HWCAP_ATOMICS | |
611a7bc7 MR |
95 | Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0010. |
96 | ||
97 | HWCAP_FPHP | |
611a7bc7 MR |
98 | Functionality implied by ID_AA64PFR0_EL1.FP == 0b0001. |
99 | ||
100 | HWCAP_ASIMDHP | |
611a7bc7 MR |
101 | Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0001. |
102 | ||
103 | HWCAP_CPUID | |
611a7bc7 | 104 | EL0 access to certain ID registers is available, to the extent |
b693d0b3 | 105 | described by Documentation/arm64/cpu-feature-registers.rst. |
611a7bc7 MR |
106 | |
107 | These ID registers may imply the availability of features. | |
108 | ||
109 | HWCAP_ASIMDRDM | |
611a7bc7 MR |
110 | Functionality implied by ID_AA64ISAR0_EL1.RDM == 0b0001. |
111 | ||
112 | HWCAP_JSCVT | |
611a7bc7 MR |
113 | Functionality implied by ID_AA64ISAR1_EL1.JSCVT == 0b0001. |
114 | ||
115 | HWCAP_FCMA | |
611a7bc7 MR |
116 | Functionality implied by ID_AA64ISAR1_EL1.FCMA == 0b0001. |
117 | ||
118 | HWCAP_LRCPC | |
611a7bc7 MR |
119 | Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0001. |
120 | ||
121 | HWCAP_DCPOP | |
611a7bc7 MR |
122 | Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001. |
123 | ||
124 | HWCAP_SHA3 | |
611a7bc7 MR |
125 | Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001. |
126 | ||
127 | HWCAP_SM3 | |
611a7bc7 MR |
128 | Functionality implied by ID_AA64ISAR0_EL1.SM3 == 0b0001. |
129 | ||
130 | HWCAP_SM4 | |
611a7bc7 MR |
131 | Functionality implied by ID_AA64ISAR0_EL1.SM4 == 0b0001. |
132 | ||
133 | HWCAP_ASIMDDP | |
611a7bc7 MR |
134 | Functionality implied by ID_AA64ISAR0_EL1.DP == 0b0001. |
135 | ||
136 | HWCAP_SHA512 | |
4bfbe5ee | 137 | Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0010. |
43994d82 DM |
138 | |
139 | HWCAP_SVE | |
43994d82 | 140 | Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001. |
3b3b6810 DG |
141 | |
142 | HWCAP_ASIMDFHM | |
3b3b6810 | 143 | Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001. |
7206dc93 SP |
144 | |
145 | HWCAP_DIT | |
7206dc93 SP |
146 | Functionality implied by ID_AA64PFR0_EL1.DIT == 0b0001. |
147 | ||
148 | HWCAP_USCAT | |
7206dc93 SP |
149 | Functionality implied by ID_AA64MMFR2_EL1.AT == 0b0001. |
150 | ||
151 | HWCAP_ILRCPC | |
4bfbe5ee | 152 | Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0010. |
7206dc93 SP |
153 | |
154 | HWCAP_FLAGM | |
7206dc93 | 155 | Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001. |
ee911761 WD |
156 | |
157 | HWCAP_SSBS | |
ee911761 | 158 | Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010. |
fbedc599 | 159 | |
0f6e4c40 JG |
160 | HWCAP_SB |
161 | Functionality implied by ID_AA64ISAR1_EL1.SB == 0b0001. | |
162 | ||
fbedc599 | 163 | HWCAP_PACA |
fbedc599 MR |
164 | Functionality implied by ID_AA64ISAR1_EL1.APA == 0b0001 or |
165 | ID_AA64ISAR1_EL1.API == 0b0001, as described by | |
b693d0b3 | 166 | Documentation/arm64/pointer-authentication.rst. |
fbedc599 MR |
167 | |
168 | HWCAP_PACG | |
fbedc599 MR |
169 | Functionality implied by ID_AA64ISAR1_EL1.GPA == 0b0001 or |
170 | ID_AA64ISAR1_EL1.GPI == 0b0001, as described by | |
b693d0b3 | 171 | Documentation/arm64/pointer-authentication.rst. |
aaba098f | 172 | |
3a25e46c JG |
173 | HWCAP2_DCPODP |
174 | ||
175 | Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010. | |
176 | ||
177 | HWCAP2_SVE2 | |
178 | ||
179 | Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001. | |
180 | ||
181 | HWCAP2_SVEAES | |
182 | ||
183 | Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001. | |
184 | ||
185 | HWCAP2_SVEPMULL | |
186 | ||
187 | Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010. | |
188 | ||
189 | HWCAP2_SVEBITPERM | |
190 | ||
191 | Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001. | |
192 | ||
193 | HWCAP2_SVESHA3 | |
194 | ||
195 | Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001. | |
196 | ||
197 | HWCAP2_SVESM4 | |
198 | ||
199 | Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001. | |
200 | ||
201 | HWCAP2_FLAGM2 | |
202 | ||
203 | Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010. | |
204 | ||
ca9503fc MB |
205 | HWCAP2_FRINT |
206 | ||
207 | Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001. | |
208 | ||
d4209d8b SP |
209 | HWCAP2_SVEI8MM |
210 | ||
211 | Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001. | |
212 | ||
213 | HWCAP2_SVEF32MM | |
214 | ||
215 | Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001. | |
216 | ||
217 | HWCAP2_SVEF64MM | |
218 | ||
219 | Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001. | |
220 | ||
221 | HWCAP2_SVEBF16 | |
222 | ||
223 | Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001. | |
224 | ||
225 | HWCAP2_I8MM | |
226 | ||
227 | Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001. | |
228 | ||
229 | HWCAP2_BF16 | |
230 | ||
231 | Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001. | |
232 | ||
233 | HWCAP2_DGH | |
234 | ||
235 | Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001. | |
aaba098f | 236 | |
1a50ec0b RH |
237 | HWCAP2_RNG |
238 | ||
239 | Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001. | |
240 | ||
8ef8f360 DM |
241 | HWCAP2_BTI |
242 | ||
243 | Functionality implied by ID_AA64PFR0_EL1.BT == 0b0001. | |
244 | ||
df9d7a22 VF |
245 | HWCAP2_MTE |
246 | ||
247 | Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described | |
248 | by Documentation/arm64/memory-tagging-extension.rst. | |
8ef8f360 | 249 | |
fee29f00 MZ |
250 | HWCAP2_ECV |
251 | ||
252 | Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. | |
253 | ||
5c13f042 JG |
254 | HWCAP2_AFP |
255 | ||
256 | Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001. | |
257 | ||
1175011a JG |
258 | HWCAP2_RPRES |
259 | ||
260 | Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001. | |
261 | ||
aaba098f AM |
262 | 4. Unused AT_HWCAP bits |
263 | ----------------------- | |
264 | ||
265 | For interoperation with userspace, the kernel guarantees that bits 62 | |
266 | and 63 of AT_HWCAP will always be returned as 0. |