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1 | =========================== |
2 | ARM64 CPU Feature Registers | |
3 | =========================== | |
4aa8a472 SP |
4 | |
5 | Author: Suzuki K Poulose <suzuki.poulose@arm.com> | |
6 | ||
7 | ||
8 | This file describes the ABI for exporting the AArch64 CPU ID/feature | |
9 | registers to userspace. The availability of this ABI is advertised | |
10 | via the HWCAP_CPUID in HWCAPs. | |
11 | ||
12 | 1. Motivation | |
b693d0b3 | 13 | ------------- |
4aa8a472 SP |
14 | |
15 | The ARM architecture defines a set of feature registers, which describe | |
16 | the capabilities of the CPU/system. Access to these system registers is | |
17 | restricted from EL0 and there is no reliable way for an application to | |
18 | extract this information to make better decisions at runtime. There is | |
19 | limited information available to the application via HWCAPs, however | |
20 | there are some issues with their usage. | |
21 | ||
22 | a) Any change to the HWCAPs requires an update to userspace (e.g libc) | |
23 | to detect the new changes, which can take a long time to appear in | |
24 | distributions. Exposing the registers allows applications to get the | |
25 | information without requiring updates to the toolchains. | |
26 | ||
27 | b) Access to HWCAPs is sometimes limited (e.g prior to libc, or | |
28 | when ld is initialised at startup time). | |
29 | ||
30 | c) HWCAPs cannot represent non-boolean information effectively. The | |
31 | architecture defines a canonical format for representing features | |
32 | in the ID registers; this is well defined and is capable of | |
33 | representing all valid architecture variations. | |
34 | ||
35 | ||
36 | 2. Requirements | |
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37 | --------------- |
38 | ||
39 | a) Safety: | |
4aa8a472 | 40 | |
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41 | Applications should be able to use the information provided by the |
42 | infrastructure to run safely across the system. This has greater | |
43 | implications on a system with heterogeneous CPUs. | |
44 | The infrastructure exports a value that is safe across all the | |
45 | available CPU on the system. | |
46 | ||
47 | e.g, If at least one CPU doesn't implement CRC32 instructions, while | |
48 | others do, we should report that the CRC32 is not implemented. | |
49 | Otherwise an application could crash when scheduled on the CPU | |
50 | which doesn't support CRC32. | |
51 | ||
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52 | b) Security: |
53 | ||
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54 | Applications should only be able to receive information that is |
55 | relevant to the normal operation in userspace. Hence, some of the | |
56 | fields are masked out(i.e, made invisible) and their values are set to | |
57 | indicate the feature is 'not supported'. See Section 4 for the list | |
58 | of visible features. Also, the kernel may manipulate the fields | |
59 | based on what it supports. e.g, If FP is not supported by the | |
60 | kernel, the values could indicate that the FP is not available | |
61 | (even when the CPU provides it). | |
62 | ||
63 | c) Implementation Defined Features | |
b693d0b3 | 64 | |
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65 | The infrastructure doesn't expose any register which is |
66 | IMPLEMENTATION DEFINED as per ARMv8-A Architecture. | |
67 | ||
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68 | d) CPU Identification: |
69 | ||
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70 | MIDR_EL1 is exposed to help identify the processor. On a |
71 | heterogeneous system, this could be racy (just like getcpu()). The | |
72 | process could be migrated to another CPU by the time it uses the | |
73 | register value, unless the CPU affinity is set. Hence, there is no | |
74 | guarantee that the value reflects the processor that it is | |
75 | currently executing on. The REVIDR is not exposed due to this | |
76 | constraint, as REVIDR makes sense only in conjunction with the | |
77 | MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs | |
b693d0b3 | 78 | at:: |
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79 | |
80 | /sys/devices/system/cpu/cpu$ID/regs/identification/ | |
81 | \- midr | |
82 | \- revidr | |
83 | ||
84 | 3. Implementation | |
85 | -------------------- | |
86 | ||
87 | The infrastructure is built on the emulation of the 'MRS' instruction. | |
88 | Accessing a restricted system register from an application generates an | |
89 | exception and ends up in SIGILL being delivered to the process. | |
90 | The infrastructure hooks into the exception handler and emulates the | |
91 | operation if the source belongs to the supported system register space. | |
92 | ||
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93 | The infrastructure emulates only the following system register space:: |
94 | ||
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95 | Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 |
96 | ||
97 | (See Table C5-6 'System instruction encodings for non-Debug System | |
98 | register accesses' in ARMv8 ARM DDI 0487A.h, for the list of | |
99 | registers). | |
100 | ||
101 | The following rules are applied to the value returned by the | |
102 | infrastructure: | |
103 | ||
104 | a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0. | |
105 | b) The value of a reserved field is populated with the reserved | |
106 | value as defined by the architecture. | |
107 | c) The value of a 'visible' field holds the system wide safe value | |
108 | for the particular feature (except for MIDR_EL1, see section 4). | |
109 | d) All other fields (i.e, invisible fields) are set to indicate | |
110 | the feature is missing (as defined by the architecture). | |
111 | ||
112 | 4. List of registers with visible features | |
113 | ------------------------------------------- | |
114 | ||
115 | 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 | |
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116 | |
117 | +------------------------------+---------+---------+ | |
4aa8a472 | 118 | | Name | bits | visible | |
b693d0b3 | 119 | +------------------------------+---------+---------+ |
7206dc93 | 120 | | TS | [55-52] | y | |
b693d0b3 | 121 | +------------------------------+---------+---------+ |
3b3b6810 | 122 | | FHM | [51-48] | y | |
b693d0b3 | 123 | +------------------------------+---------+---------+ |
f5e035f8 | 124 | | DP | [47-44] | y | |
b693d0b3 | 125 | +------------------------------+---------+---------+ |
f5e035f8 | 126 | | SM4 | [43-40] | y | |
b693d0b3 | 127 | +------------------------------+---------+---------+ |
f5e035f8 | 128 | | SM3 | [39-36] | y | |
b693d0b3 | 129 | +------------------------------+---------+---------+ |
f5e035f8 | 130 | | SHA3 | [35-32] | y | |
b693d0b3 | 131 | +------------------------------+---------+---------+ |
4aa8a472 | 132 | | RDM | [31-28] | y | |
b693d0b3 | 133 | +------------------------------+---------+---------+ |
4aa8a472 | 134 | | ATOMICS | [23-20] | y | |
b693d0b3 | 135 | +------------------------------+---------+---------+ |
4aa8a472 | 136 | | CRC32 | [19-16] | y | |
b693d0b3 | 137 | +------------------------------+---------+---------+ |
4aa8a472 | 138 | | SHA2 | [15-12] | y | |
b693d0b3 | 139 | +------------------------------+---------+---------+ |
4aa8a472 | 140 | | SHA1 | [11-8] | y | |
b693d0b3 | 141 | +------------------------------+---------+---------+ |
4aa8a472 | 142 | | AES | [7-4] | y | |
b693d0b3 | 143 | +------------------------------+---------+---------+ |
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144 | |
145 | ||
146 | 2) ID_AA64PFR0_EL1 - Processor Feature Register 0 | |
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147 | |
148 | +------------------------------+---------+---------+ | |
4aa8a472 | 149 | | Name | bits | visible | |
b693d0b3 | 150 | +------------------------------+---------+---------+ |
7206dc93 | 151 | | DIT | [51-48] | y | |
b693d0b3 | 152 | +------------------------------+---------+---------+ |
43994d82 | 153 | | SVE | [35-32] | y | |
b693d0b3 | 154 | +------------------------------+---------+---------+ |
4aa8a472 | 155 | | GIC | [27-24] | n | |
b693d0b3 | 156 | +------------------------------+---------+---------+ |
4aa8a472 | 157 | | AdvSIMD | [23-20] | y | |
b693d0b3 | 158 | +------------------------------+---------+---------+ |
4aa8a472 | 159 | | FP | [19-16] | y | |
b693d0b3 | 160 | +------------------------------+---------+---------+ |
4aa8a472 | 161 | | EL3 | [15-12] | n | |
b693d0b3 | 162 | +------------------------------+---------+---------+ |
4aa8a472 | 163 | | EL2 | [11-8] | n | |
b693d0b3 | 164 | +------------------------------+---------+---------+ |
4aa8a472 | 165 | | EL1 | [7-4] | n | |
b693d0b3 | 166 | +------------------------------+---------+---------+ |
4aa8a472 | 167 | | EL0 | [3-0] | n | |
b693d0b3 | 168 | +------------------------------+---------+---------+ |
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169 | |
170 | ||
171 | 3) MIDR_EL1 - Main ID Register | |
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172 | |
173 | +------------------------------+---------+---------+ | |
4aa8a472 | 174 | | Name | bits | visible | |
b693d0b3 | 175 | +------------------------------+---------+---------+ |
4aa8a472 | 176 | | Implementer | [31-24] | y | |
b693d0b3 | 177 | +------------------------------+---------+---------+ |
4aa8a472 | 178 | | Variant | [23-20] | y | |
b693d0b3 | 179 | +------------------------------+---------+---------+ |
4aa8a472 | 180 | | Architecture | [19-16] | y | |
b693d0b3 | 181 | +------------------------------+---------+---------+ |
4aa8a472 | 182 | | PartNum | [15-4] | y | |
b693d0b3 | 183 | +------------------------------+---------+---------+ |
4aa8a472 | 184 | | Revision | [3-0] | y | |
b693d0b3 | 185 | +------------------------------+---------+---------+ |
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186 | |
187 | NOTE: The 'visible' fields of MIDR_EL1 will contain the value | |
188 | as available on the CPU where it is fetched and is not a system | |
189 | wide safe value. | |
190 | ||
c8c3798d SP |
191 | 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 |
192 | ||
b693d0b3 | 193 | +------------------------------+---------+---------+ |
c8c3798d | 194 | | Name | bits | visible | |
b693d0b3 | 195 | +------------------------------+---------+---------+ |
fbedc599 | 196 | | GPI | [31-28] | y | |
b693d0b3 | 197 | +------------------------------+---------+---------+ |
fbedc599 | 198 | | GPA | [27-24] | y | |
b693d0b3 | 199 | +------------------------------+---------+---------+ |
c651aae5 | 200 | | LRCPC | [23-20] | y | |
b693d0b3 | 201 | +------------------------------+---------+---------+ |
cb567e79 | 202 | | FCMA | [19-16] | y | |
b693d0b3 | 203 | +------------------------------+---------+---------+ |
c8c3798d | 204 | | JSCVT | [15-12] | y | |
b693d0b3 | 205 | +------------------------------+---------+---------+ |
fbedc599 | 206 | | API | [11-8] | y | |
b693d0b3 | 207 | +------------------------------+---------+---------+ |
fbedc599 | 208 | | APA | [7-4] | y | |
b693d0b3 | 209 | +------------------------------+---------+---------+ |
7aac405e | 210 | | DPB | [3-0] | y | |
b693d0b3 | 211 | +------------------------------+---------+---------+ |
c8c3798d | 212 | |
7206dc93 SP |
213 | 5) ID_AA64MMFR2_EL1 - Memory model feature register 2 |
214 | ||
b693d0b3 | 215 | +------------------------------+---------+---------+ |
7206dc93 | 216 | | Name | bits | visible | |
b693d0b3 | 217 | +------------------------------+---------+---------+ |
7206dc93 | 218 | | AT | [35-32] | y | |
b693d0b3 | 219 | +------------------------------+---------+---------+ |
7206dc93 | 220 | |
06a916fe DM |
221 | 6) ID_AA64ZFR0_EL1 - SVE feature ID register 0 |
222 | ||
b693d0b3 | 223 | +------------------------------+---------+---------+ |
06a916fe | 224 | | Name | bits | visible | |
b693d0b3 | 225 | +------------------------------+---------+---------+ |
06a916fe | 226 | | SM4 | [43-40] | y | |
b693d0b3 | 227 | +------------------------------+---------+---------+ |
06a916fe | 228 | | SHA3 | [35-32] | y | |
b693d0b3 | 229 | +------------------------------+---------+---------+ |
06a916fe | 230 | | BitPerm | [19-16] | y | |
b693d0b3 | 231 | +------------------------------+---------+---------+ |
06a916fe | 232 | | AES | [7-4] | y | |
b693d0b3 | 233 | +------------------------------+---------+---------+ |
06a916fe | 234 | | SVEVer | [3-0] | y | |
b693d0b3 | 235 | +------------------------------+---------+---------+ |
06a916fe | 236 | |
4aa8a472 | 237 | Appendix I: Example |
b693d0b3 MCC |
238 | ------------------- |
239 | ||
240 | :: | |
241 | ||
242 | /* | |
243 | * Sample program to demonstrate the MRS emulation ABI. | |
244 | * | |
245 | * Copyright (C) 2015-2016, ARM Ltd | |
246 | * | |
247 | * Author: Suzuki K Poulose <suzuki.poulose@arm.com> | |
248 | * | |
249 | * This program is free software; you can redistribute it and/or modify | |
250 | * it under the terms of the GNU General Public License version 2 as | |
251 | * published by the Free Software Foundation. | |
252 | * | |
253 | * This program is distributed in the hope that it will be useful, | |
254 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
255 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
256 | * GNU General Public License for more details. | |
257 | * This program is free software; you can redistribute it and/or modify | |
258 | * it under the terms of the GNU General Public License version 2 as | |
259 | * published by the Free Software Foundation. | |
260 | * | |
261 | * This program is distributed in the hope that it will be useful, | |
262 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
263 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
264 | * GNU General Public License for more details. | |
265 | */ | |
266 | ||
267 | #include <asm/hwcap.h> | |
268 | #include <stdio.h> | |
269 | #include <sys/auxv.h> | |
270 | ||
271 | #define get_cpu_ftr(id) ({ \ | |
4aa8a472 SP |
272 | unsigned long __val; \ |
273 | asm("mrs %0, "#id : "=r" (__val)); \ | |
274 | printf("%-20s: 0x%016lx\n", #id, __val); \ | |
275 | }) | |
276 | ||
b693d0b3 MCC |
277 | int main(void) |
278 | { | |
4aa8a472 SP |
279 | |
280 | if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { | |
281 | fputs("CPUID registers unavailable\n", stderr); | |
282 | return 1; | |
283 | } | |
284 | ||
285 | get_cpu_ftr(ID_AA64ISAR0_EL1); | |
286 | get_cpu_ftr(ID_AA64ISAR1_EL1); | |
287 | get_cpu_ftr(ID_AA64MMFR0_EL1); | |
288 | get_cpu_ftr(ID_AA64MMFR1_EL1); | |
289 | get_cpu_ftr(ID_AA64PFR0_EL1); | |
290 | get_cpu_ftr(ID_AA64PFR1_EL1); | |
291 | get_cpu_ftr(ID_AA64DFR0_EL1); | |
292 | get_cpu_ftr(ID_AA64DFR1_EL1); | |
293 | ||
294 | get_cpu_ftr(MIDR_EL1); | |
295 | get_cpu_ftr(MPIDR_EL1); | |
296 | get_cpu_ftr(REVIDR_EL1); | |
297 | ||
b693d0b3 | 298 | #if 0 |
4aa8a472 SP |
299 | /* Unexposed register access causes SIGILL */ |
300 | get_cpu_ftr(ID_MMFR0_EL1); | |
b693d0b3 | 301 | #endif |
4aa8a472 SP |
302 | |
303 | return 0; | |
b693d0b3 | 304 | } |