[linux-block.git] / Documentation / admin-guide / perf / qcom_l3_pmu.rst

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Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
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This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
by all cores within a socket. Each slice is exposed as a separate uncore perf
PMU with device name l3cache_<socket>_<instance>. User space is responsible
for aggregating across slices.

The driver provides a description of its available events and configuration
options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
the driver also exposes a "cpumask" sysfs attribute which contains a mask
consisting of one CPU per socket which will be used to handle all the PMU
events on that socket.

The hardware implements 32bit event counters and has a flat 8bit event space
exposed via the "event" format attribute. In addition to the 32bit physical
counters the driver supports virtual 64bit hardware counters by using hardware
counter chaining. This feature is exposed via the "lc" (long counter) format
flag. E.g.::

  perf stat -e l3cache_0_0/read-miss,lc/

Given that these are uncore PMUs the driver does not support sampling, therefore
"perf record" will not work. Per-task perf sessions are not supported.
Commit	Line	Data
6baec315	1	===========================================================================
3071f13d AVF	2	Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
	3	===========================================================================
	4
	5	This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
	6	Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
	7	by all cores within a socket. Each slice is exposed as a separate uncore perf
	8	PMU with device name l3cache_<socket>_<instance>. User space is responsible
	9	for aggregating across slices.
	10
	11	The driver provides a description of its available events and configuration
	12	options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
	13	the driver also exposes a "cpumask" sysfs attribute which contains a mask
	14	consisting of one CPU per socket which will be used to handle all the PMU
	15	events on that socket.
	16
	17	The hardware implements 32bit event counters and has a flat 8bit event space
	18	exposed via the "event" format attribute. In addition to the 32bit physical
	19	counters the driver supports virtual 64bit hardware counters by using hardware
	20	counter chaining. This feature is exposed via the "lc" (long counter) format
6baec315	21	flag. E.g.::
3071f13d AVF	22
	23	perf stat -e l3cache_0_0/read-miss,lc/
	24
	25	Given that these are uncore PMUs the driver does not support sampling, therefore
	26	"perf record" will not work. Per-task perf sessions are not supported.