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1 | ===================================================== |
2 | Freescale i.MX8 DDR Performance Monitoring Unit (PMU) | |
3 | ===================================================== | |
4 | ||
5 | There are no performance counters inside the DRAM controller, so performance | |
6 | signals are brought out to the edge of the controller where a set of 4 x 32 bit | |
751d5b27 | 7 | counters is implemented. This is controlled by the CSV modes programmed in counter |
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8 | control register which causes a large number of PERF signals to be generated. |
9 | ||
10 | Selection of the value for each counter is done via the config registers. There | |
11 | is one register for each counter. Counter 0 is special in that it always counts | |
12 | “time” and when expired causes a lock on itself and the other counters and an | |
13 | interrupt is raised. If any other counter overflows, it continues counting, and | |
14 | no interrupt is raised. | |
15 | ||
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16 | The "format" directory describes format of the config (event ID) and config1/2 |
17 | (AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/ | |
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18 | devices/imx8_ddr0/format/. The "events" directory describes the events types |
19 | hardware supported that can be used with perf tool, see /sys/bus/event_source/ | |
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20 | devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented |
21 | in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/. | |
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22 | |
23 | .. code-block:: bash | |
24 | ||
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25 | perf stat -a -e imx8_ddr0/cycles/ cmd |
26 | perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd | |
27 | ||
28 | AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) | |
29 | to count reading or writing matches filter setting. Filter setting is various | |
30 | from different DRAM controller implementations, which is distinguished by quirks | |
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31 | in the driver. You also can dump info from userspace, "caps" directory show the |
32 | type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for | |
33 | un-supported, and value 1 for supported. | |
3724e186 | 34 | |
97452953 | 35 | * With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0, super_filter: 0). |
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36 | Filter is defined with two configuration parts: |
37 | --AXI_ID defines AxID matching value. | |
38 | --AXI_MASKING defines which bits of AxID are meaningful for the matching. | |
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39 | |
40 | - 0: corresponding bit is masked. | |
41 | - 1: corresponding bit is not masked, i.e. used to do the matching. | |
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42 | |
43 | AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter. | |
44 | When non-masked bits are matching corresponding AXI_ID bits then counter is | |
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45 | incremented. Perf counter is incremented if:: |
46 | ||
0522e130 | 47 | AxID && AXI_MASKING == AXI_ID && AXI_MASKING |
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48 | |
49 | This filter doesn't support filter different AXI ID for axid-read and axid-write | |
50 | event at the same time as this filter is shared between counters. | |
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51 | |
52 | .. code-block:: bash | |
53 | ||
54 | perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd | |
55 | perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd | |
56 | ||
57 | .. note:: | |
58 | ||
59 | axi_mask is inverted in userspace(i.e. set bits are bits to mask), and | |
60 | it will be reverted in driver automatically. so that the user can just specify | |
61 | axi_id to monitor a specific id, rather than having to specify axi_mask. | |
62 | ||
63 | .. code-block:: bash | |
64 | ||
3724e186 | 65 | perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12 |
76d835fc | 66 | |
97452953 | 67 | * With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1, super_filter: 0). |
76d835fc JZ |
68 | This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits |
69 | counting the number of bytes (as opposed to the number of bursts) from DDR | |
70 | read and write transactions concurrently with another set of data counters. | |
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71 | |
72 | * With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk(filter: 0, enhanced_filter: 0, super_filter: 1). | |
73 | There is a limitation in previous AXI filter, it cannot filter different IDs | |
74 | at the same time as the filter is shared between counters. This quirk is the | |
75 | extension of AXI ID filter. One improvement is that counter 1-3 has their own | |
76 | filter, means that it supports concurrently filter various IDs. Another | |
77 | improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support | |
78 | selecting address channel or data channel. | |
79 | ||
80 | Filter is defined with 2 configuration registers per counter 1-3. | |
81 | --Counter N MASK COMP register - including AXI_ID and AXI_MASKING. | |
82 | --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT. | |
83 | ||
84 | - 0: address channel | |
85 | - 1: data channel | |
86 | ||
87 | PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved | |
88 | which should be 0. | |
89 | ||
90 | .. code-block:: bash | |
91 | ||
92 | perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd | |
93 | perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd | |
94 | ||
95 | .. note:: | |
96 | ||
97 | axi_channel is inverted in userspace, and it will be reverted in driver | |
98 | automatically. So that users do not need specify axi_channel if want to | |
99 | monitor data channel from DDR transactions, since data channel is more | |
100 | meaningful. |