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3724e186 JZ |
1 | ===================================================== |
2 | Freescale i.MX8 DDR Performance Monitoring Unit (PMU) | |
3 | ===================================================== | |
4 | ||
5 | There are no performance counters inside the DRAM controller, so performance | |
6 | signals are brought out to the edge of the controller where a set of 4 x 32 bit | |
751d5b27 | 7 | counters is implemented. This is controlled by the CSV modes programmed in counter |
3724e186 JZ |
8 | control register which causes a large number of PERF signals to be generated. |
9 | ||
10 | Selection of the value for each counter is done via the config registers. There | |
11 | is one register for each counter. Counter 0 is special in that it always counts | |
12 | “time” and when expired causes a lock on itself and the other counters and an | |
13 | interrupt is raised. If any other counter overflows, it continues counting, and | |
14 | no interrupt is raised. | |
15 | ||
16 | The "format" directory describes format of the config (event ID) and config1 | |
17 | (AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/ | |
18 | devices/imx8_ddr0/format/. The "events" directory describes the events types | |
19 | hardware supported that can be used with perf tool, see /sys/bus/event_source/ | |
ed0207a3 JZ |
20 | devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented |
21 | in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/. | |
0522e130 AZ |
22 | |
23 | .. code-block:: bash | |
24 | ||
3724e186 JZ |
25 | perf stat -a -e imx8_ddr0/cycles/ cmd |
26 | perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd | |
27 | ||
28 | AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) | |
29 | to count reading or writing matches filter setting. Filter setting is various | |
30 | from different DRAM controller implementations, which is distinguished by quirks | |
ed0207a3 JZ |
31 | in the driver. You also can dump info from userspace, filter in "caps" directory |
32 | indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates | |
33 | whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and | |
34 | value 1 for supported. | |
3724e186 | 35 | |
ed0207a3 | 36 | * With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0). |
3724e186 JZ |
37 | Filter is defined with two configuration parts: |
38 | --AXI_ID defines AxID matching value. | |
39 | --AXI_MASKING defines which bits of AxID are meaningful for the matching. | |
0522e130 AZ |
40 | |
41 | - 0: corresponding bit is masked. | |
42 | - 1: corresponding bit is not masked, i.e. used to do the matching. | |
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43 | |
44 | AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter. | |
45 | When non-masked bits are matching corresponding AXI_ID bits then counter is | |
2b008dc6 MCC |
46 | incremented. Perf counter is incremented if:: |
47 | ||
0522e130 | 48 | AxID && AXI_MASKING == AXI_ID && AXI_MASKING |
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49 | |
50 | This filter doesn't support filter different AXI ID for axid-read and axid-write | |
51 | event at the same time as this filter is shared between counters. | |
0522e130 AZ |
52 | |
53 | .. code-block:: bash | |
54 | ||
55 | perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd | |
56 | perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd | |
57 | ||
58 | .. note:: | |
59 | ||
60 | axi_mask is inverted in userspace(i.e. set bits are bits to mask), and | |
61 | it will be reverted in driver automatically. so that the user can just specify | |
62 | axi_id to monitor a specific id, rather than having to specify axi_mask. | |
63 | ||
64 | .. code-block:: bash | |
65 | ||
3724e186 | 66 | perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12 |
76d835fc | 67 | |
ed0207a3 | 68 | * With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1). |
76d835fc JZ |
69 | This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits |
70 | counting the number of bytes (as opposed to the number of bursts) from DDR | |
71 | read and write transactions concurrently with another set of data counters. |