Commit | Line | Data |
---|---|---|
6baec315 | 1 | ================================== |
7520fa99 SP |
2 | ARM DynamIQ Shared Unit (DSU) PMU |
3 | ================================== | |
4 | ||
5 | ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system, | |
6 | control logic and external interfaces to form a multicore cluster. The PMU | |
7 | allows counting the various events related to the L3 cache, Snoop Control Unit | |
8 | etc, using 32bit independent counters. It also provides a 64bit cycle counter. | |
9 | ||
10 | The PMU can only be accessed via CPU system registers and are common to the | |
11 | cores connected to the same DSU. Like most of the other uncore PMUs, DSU | |
12 | PMU doesn't support process specific events and cannot be used in sampling mode. | |
13 | ||
14 | The DSU provides a bitmap for a subset of implemented events via hardware | |
15 | registers. There is no way for the driver to determine if the other events | |
16 | are available or not. Hence the driver exposes only those events advertised | |
6baec315 | 17 | by the DSU, in "events" directory under:: |
7520fa99 SP |
18 | |
19 | /sys/bus/event_sources/devices/arm_dsu_<N>/ | |
20 | ||
21 | The user should refer to the TRM of the product to figure out the supported events | |
22 | and use the raw event code for the unlisted events. | |
23 | ||
24 | The driver also exposes the CPUs connected to the DSU instance in "associated_cpus". | |
25 | ||
26 | ||
6baec315 | 27 | e.g usage:: |
7520fa99 SP |
28 | |
29 | perf stat -a -e arm_dsu_0/cycles/ |