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IB/mlx4: Display misc device information under /sys/class/infiniband/
[linux-block.git] / drivers / net / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
41
42#include <linux/mlx4/device.h>
43#include <linux/mlx4/doorbell.h>
44
45#include "mlx4.h"
46#include "fw.h"
47#include "icm.h"
48
49MODULE_AUTHOR("Roland Dreier");
50MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51MODULE_LICENSE("Dual BSD/GPL");
52MODULE_VERSION(DRV_VERSION);
53
54#ifdef CONFIG_MLX4_DEBUG
55
56int mlx4_debug_level = 0;
57module_param_named(debug_level, mlx4_debug_level, int, 0644);
58MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
59
60#endif /* CONFIG_MLX4_DEBUG */
61
62#ifdef CONFIG_PCI_MSI
63
08fb1055 64static int msi_x = 1;
225c7b1f
RD		 65module_param(msi_x, int, 0444);
66MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
67
68#else /* CONFIG_PCI_MSI */
69
70#define msi_x (0)
71
72#endif /* CONFIG_PCI_MSI */
73
74static const char mlx4_version[] __devinitdata =
75 DRV_NAME ": Mellanox ConnectX core driver v"
76 DRV_VERSION " (" DRV_RELDATE ")\n";
77
78static struct mlx4_profile default_profile = {
79 .num_qp = 1 << 16,
80 .num_srq = 1 << 16,
c9f2ba5e 81 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 82 .num_cq = 1 << 16,
83 .num_mcg = 1 << 13,
84 .num_mpt = 1 << 17,
85 .num_mtt = 1 << 20,
86};
87
88static int __devinit mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
89{
90 int err;
5ae2a7a8 91 int i;
225c7b1f
RD		 92
93 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
94 if (err) {
95 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
96 return err;
97 }
98
99 if (dev_cap->min_page_sz > PAGE_SIZE) {
100 mlx4_err(dev, "HCA minimum page size of %d bigger than "
101 "kernel PAGE_SIZE of %ld, aborting.\n",
102 dev_cap->min_page_sz, PAGE_SIZE);
103 return -ENODEV;
104 }
105 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
106 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
107 "aborting.\n",
108 dev_cap->num_ports, MLX4_MAX_PORTS);
109 return -ENODEV;
110 }
111
112 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
113 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
114 "PCI resource 2 size of 0x%llx, aborting.\n",
115 dev_cap->uar_size,
116 (unsigned long long) pci_resource_len(dev->pdev, 2));
117 return -ENODEV;
118 }
119
120 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 121 for (i = 1; i <= dev->caps.num_ports; ++i) {
122 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
123 dev->caps.mtu_cap[i] = dev_cap->max_mtu[i];
124 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
125 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
126 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
127 }
128
225c7b1f 129 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 130 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
131 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
132 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
133 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
134 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
135 dev->caps.max_wqes = dev_cap->max_qp_sz;
136 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
137 dev->caps.reserved_qps = dev_cap->reserved_qps;
138 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
139 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
140 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
141 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
142 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
143 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
144 /*
145 * Subtract 1 from the limit because we need to allocate a
146 * spare CQE so the HCA HW can tell the difference between an
147 * empty CQ and a full CQ.
148 */
149 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
150 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
151 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
152 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
153 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
154 dev->caps.reserved_uars = dev_cap->reserved_uars;
155 dev->caps.reserved_pds = dev_cap->reserved_pds;
225c7b1f 156 dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
149983af 157 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 158 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
159 dev->caps.flags = dev_cap->flags;
160 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
161
162 return 0;
163}
164
165static int __devinit mlx4_load_fw(struct mlx4_dev *dev)
166{
167 struct mlx4_priv *priv = mlx4_priv(dev);
168 int err;
169
170 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
171 GFP_HIGHUSER | __GFP_NOWARN);
172 if (!priv->fw.fw_icm) {
173 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
174 return -ENOMEM;
175 }
176
177 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
178 if (err) {
179 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
180 goto err_free;
181 }
182
183 err = mlx4_RUN_FW(dev);
184 if (err) {
185 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
186 goto err_unmap_fa;
187 }
188
189 return 0;
190
191err_unmap_fa:
192 mlx4_UNMAP_FA(dev);
193
194err_free:
195 mlx4_free_icm(dev, priv->fw.fw_icm);
196 return err;
197}
198
199static int __devinit mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
200 int cmpt_entry_sz)
201{
202 struct mlx4_priv *priv = mlx4_priv(dev);
203 int err;
204
205 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
206 cmpt_base +
207 ((u64) (MLX4_CMPT_TYPE_QP *
208 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
209 cmpt_entry_sz, dev->caps.num_qps,
210 dev->caps.reserved_qps, 0);
211 if (err)
212 goto err;
213
214 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
215 cmpt_base +
216 ((u64) (MLX4_CMPT_TYPE_SRQ *
217 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
218 cmpt_entry_sz, dev->caps.num_srqs,
219 dev->caps.reserved_srqs, 0);
220 if (err)
221 goto err_qp;
222
223 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
224 cmpt_base +
225 ((u64) (MLX4_CMPT_TYPE_CQ *
226 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
227 cmpt_entry_sz, dev->caps.num_cqs,
228 dev->caps.reserved_cqs, 0);
229 if (err)
230 goto err_srq;
231
232 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
233 cmpt_base +
234 ((u64) (MLX4_CMPT_TYPE_EQ *
235 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
236 cmpt_entry_sz,
237 roundup_pow_of_two(MLX4_NUM_EQ +
238 dev->caps.reserved_eqs),
239 MLX4_NUM_EQ + dev->caps.reserved_eqs, 0);
240 if (err)
241 goto err_cq;
242
243 return 0;
244
245err_cq:
246 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
247
248err_srq:
249 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
250
251err_qp:
252 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
253
254err:
255 return err;
256}
257
258static int __devinit mlx4_init_icm(struct mlx4_dev *dev,
259 struct mlx4_dev_cap *dev_cap,
260 struct mlx4_init_hca_param *init_hca,
261 u64 icm_size)
262{
263 struct mlx4_priv *priv = mlx4_priv(dev);
264 u64 aux_pages;
265 int err;
266
267 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
268 if (err) {
269 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
270 return err;
271 }
272
273 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
274 (unsigned long long) icm_size >> 10,
275 (unsigned long long) aux_pages << 2);
276
277 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
278 GFP_HIGHUSER | __GFP_NOWARN);
279 if (!priv->fw.aux_icm) {
280 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
281 return -ENOMEM;
282 }
283
284 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
285 if (err) {
286 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
287 goto err_free_aux;
288 }
289
290 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
291 if (err) {
292 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
293 goto err_unmap_aux;
294 }
295
296 err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
297 if (err) {
298 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
299 goto err_unmap_cmpt;
300 }
301
302 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
303 init_hca->mtt_base,
304 dev->caps.mtt_entry_sz,
305 dev->caps.num_mtt_segs,
306 dev->caps.reserved_mtts, 1);
307 if (err) {
308 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
309 goto err_unmap_eq;
310 }
311
312 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
313 init_hca->dmpt_base,
314 dev_cap->dmpt_entry_sz,
315 dev->caps.num_mpts,
316 dev->caps.reserved_mrws, 1);
317 if (err) {
318 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
319 goto err_unmap_mtt;
320 }
321
322 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
323 init_hca->qpc_base,
324 dev_cap->qpc_entry_sz,
325 dev->caps.num_qps,
326 dev->caps.reserved_qps, 0);
327 if (err) {
328 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
329 goto err_unmap_dmpt;
330 }
331
332 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
333 init_hca->auxc_base,
334 dev_cap->aux_entry_sz,
335 dev->caps.num_qps,
336 dev->caps.reserved_qps, 0);
337 if (err) {
338 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
339 goto err_unmap_qp;
340 }
341
342 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
343 init_hca->altc_base,
344 dev_cap->altc_entry_sz,
345 dev->caps.num_qps,
346 dev->caps.reserved_qps, 0);
347 if (err) {
348 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
349 goto err_unmap_auxc;
350 }
351
352 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
353 init_hca->rdmarc_base,
354 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
355 dev->caps.num_qps,
356 dev->caps.reserved_qps, 0);
357 if (err) {
358 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
359 goto err_unmap_altc;
360 }
361
362 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
363 init_hca->cqc_base,
364 dev_cap->cqc_entry_sz,
365 dev->caps.num_cqs,
366 dev->caps.reserved_cqs, 0);
367 if (err) {
368 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
369 goto err_unmap_rdmarc;
370 }
371
372 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
373 init_hca->srqc_base,
374 dev_cap->srq_entry_sz,
375 dev->caps.num_srqs,
376 dev->caps.reserved_srqs, 0);
377 if (err) {
378 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
379 goto err_unmap_cq;
380 }
381
382 /*
383 * It's not strictly required, but for simplicity just map the
384 * whole multicast group table now. The table isn't very big
385 * and it's a lot easier than trying to track ref counts.
386 */
387 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
388 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
389 dev->caps.num_mgms + dev->caps.num_amgms,
390 dev->caps.num_mgms + dev->caps.num_amgms,
391 0);
392 if (err) {
393 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
394 goto err_unmap_srq;
395 }
396
397 return 0;
398
399err_unmap_srq:
400 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
401
402err_unmap_cq:
403 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
404
405err_unmap_rdmarc:
406 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
407
408err_unmap_altc:
409 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
410
411err_unmap_auxc:
412 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
413
414err_unmap_qp:
415 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
416
417err_unmap_dmpt:
418 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
419
420err_unmap_mtt:
421 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
422
423err_unmap_eq:
424 mlx4_unmap_eq_icm(dev);
425
426err_unmap_cmpt:
427 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
428 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
429 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
430 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
431
432err_unmap_aux:
433 mlx4_UNMAP_ICM_AUX(dev);
434
435err_free_aux:
436 mlx4_free_icm(dev, priv->fw.aux_icm);
437
438 return err;
439}
440
441static void mlx4_free_icms(struct mlx4_dev *dev)
442{
443 struct mlx4_priv *priv = mlx4_priv(dev);
444
445 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
446 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
447 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
448 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
449 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
450 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
451 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
452 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
453 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
454 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
455 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
456 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
457 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
458 mlx4_unmap_eq_icm(dev);
459
460 mlx4_UNMAP_ICM_AUX(dev);
461 mlx4_free_icm(dev, priv->fw.aux_icm);
462}
463
464static void mlx4_close_hca(struct mlx4_dev *dev)
465{
466 mlx4_CLOSE_HCA(dev, 0);
467 mlx4_free_icms(dev);
468 mlx4_UNMAP_FA(dev);
469 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm);
470}
471
472static int __devinit mlx4_init_hca(struct mlx4_dev *dev)
473{
474 struct mlx4_priv *priv = mlx4_priv(dev);
475 struct mlx4_adapter adapter;
476 struct mlx4_dev_cap dev_cap;
477 struct mlx4_profile profile;
478 struct mlx4_init_hca_param init_hca;
479 u64 icm_size;
480 int err;
481
482 err = mlx4_QUERY_FW(dev);
483 if (err) {
484 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
485 return err;
486 }
487
488 err = mlx4_load_fw(dev);
489 if (err) {
490 mlx4_err(dev, "Failed to start FW, aborting.\n");
491 return err;
492 }
493
494 err = mlx4_dev_cap(dev, &dev_cap);
495 if (err) {
496 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
497 goto err_stop_fw;
498 }
499
500 profile = default_profile;
501
502 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
503 if ((long long) icm_size < 0) {
504 err = icm_size;
505 goto err_stop_fw;
506 }
507
508 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
509
510 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
511 if (err)
512 goto err_stop_fw;
513
514 err = mlx4_INIT_HCA(dev, &init_hca);
515 if (err) {
516 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
517 goto err_free_icm;
518 }
519
520 err = mlx4_QUERY_ADAPTER(dev, &adapter);
521 if (err) {
522 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
523 goto err_close;
524 }
525
526 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8
JM		 527 dev->rev_id = adapter.revision_id;
528 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 529
530 return 0;
531
532err_close:
533 mlx4_close_hca(dev);
534
535err_free_icm:
536 mlx4_free_icms(dev);
537
538err_stop_fw:
539 mlx4_UNMAP_FA(dev);
540 mlx4_free_icm(dev, priv->fw.fw_icm);
541
542 return err;
543}
544
545static int __devinit mlx4_setup_hca(struct mlx4_dev *dev)
546{
547 struct mlx4_priv *priv = mlx4_priv(dev);
548 int err;
549
225c7b1f
RD		 550 err = mlx4_init_uar_table(dev);
551 if (err) {
552 mlx4_err(dev, "Failed to initialize "
553 "user access region table, aborting.\n");
554 return err;
555 }
556
557 err = mlx4_uar_alloc(dev, &priv->driver_uar);
558 if (err) {
559 mlx4_err(dev, "Failed to allocate driver access region, "
560 "aborting.\n");
561 goto err_uar_table_free;
562 }
563
564 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
565 if (!priv->kar) {
566 mlx4_err(dev, "Couldn't map kernel access region, "
567 "aborting.\n");
568 err = -ENOMEM;
569 goto err_uar_free;
570 }
571
572 err = mlx4_init_pd_table(dev);
573 if (err) {
574 mlx4_err(dev, "Failed to initialize "
575 "protection domain table, aborting.\n");
576 goto err_kar_unmap;
577 }
578
579 err = mlx4_init_mr_table(dev);
580 if (err) {
581 mlx4_err(dev, "Failed to initialize "
582 "memory region table, aborting.\n");
583 goto err_pd_table_free;
584 }
585
225c7b1f
RD		 586 err = mlx4_init_eq_table(dev);
587 if (err) {
588 mlx4_err(dev, "Failed to initialize "
589 "event queue table, aborting.\n");
ee49bd93 590 goto err_mr_table_free;
225c7b1f
RD		 591 }
592
593 err = mlx4_cmd_use_events(dev);
594 if (err) {
595 mlx4_err(dev, "Failed to switch to event-driven "
596 "firmware commands, aborting.\n");
597 goto err_eq_table_free;
598 }
599
600 err = mlx4_NOP(dev);
601 if (err) {
08fb1055
MT		 602 if (dev->flags & MLX4_FLAG_MSI_X) {
603 mlx4_warn(dev, "NOP command failed to generate MSI-X "
604 "interrupt IRQ %d).\n",
605 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
606 mlx4_warn(dev, "Trying again without MSI-X.\n");
607 } else {
608 mlx4_err(dev, "NOP command failed to generate interrupt "
609 "(IRQ %d), aborting.\n",
610 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 611 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 612 }
225c7b1f
RD		 613
614 goto err_cmd_poll;
615 }
616
617 mlx4_dbg(dev, "NOP command IRQ test passed\n");
618
619 err = mlx4_init_cq_table(dev);
620 if (err) {
621 mlx4_err(dev, "Failed to initialize "
622 "completion queue table, aborting.\n");
623 goto err_cmd_poll;
624 }
625
626 err = mlx4_init_srq_table(dev);
627 if (err) {
628 mlx4_err(dev, "Failed to initialize "
629 "shared receive queue table, aborting.\n");
630 goto err_cq_table_free;
631 }
632
633 err = mlx4_init_qp_table(dev);
634 if (err) {
635 mlx4_err(dev, "Failed to initialize "
636 "queue pair table, aborting.\n");
637 goto err_srq_table_free;
638 }
639
640 err = mlx4_init_mcg_table(dev);
641 if (err) {
642 mlx4_err(dev, "Failed to initialize "
643 "multicast group table, aborting.\n");
644 goto err_qp_table_free;
645 }
646
647 return 0;
648
649err_qp_table_free:
650 mlx4_cleanup_qp_table(dev);
651
652err_srq_table_free:
653 mlx4_cleanup_srq_table(dev);
654
655err_cq_table_free:
656 mlx4_cleanup_cq_table(dev);
657
658err_cmd_poll:
659 mlx4_cmd_use_polling(dev);
660
661err_eq_table_free:
662 mlx4_cleanup_eq_table(dev);
663
ee49bd93 664err_mr_table_free:
225c7b1f
RD		 665 mlx4_cleanup_mr_table(dev);
666
667err_pd_table_free:
668 mlx4_cleanup_pd_table(dev);
669
670err_kar_unmap:
671 iounmap(priv->kar);
672
673err_uar_free:
674 mlx4_uar_free(dev, &priv->driver_uar);
675
676err_uar_table_free:
677 mlx4_cleanup_uar_table(dev);
678 return err;
679}
680
681static void __devinit mlx4_enable_msi_x(struct mlx4_dev *dev)
682{
683 struct mlx4_priv *priv = mlx4_priv(dev);
684 struct msix_entry entries[MLX4_NUM_EQ];
685 int err;
686 int i;
687
688 if (msi_x) {
689 for (i = 0; i < MLX4_NUM_EQ; ++i)
690 entries[i].entry = i;
691
692 err = pci_enable_msix(dev->pdev, entries, ARRAY_SIZE(entries));
693 if (err) {
694 if (err > 0)
695 mlx4_info(dev, "Only %d MSI-X vectors available, "
696 "not using MSI-X\n", err);
697 goto no_msi;
698 }
699
700 for (i = 0; i < MLX4_NUM_EQ; ++i)
701 priv->eq_table.eq[i].irq = entries[i].vector;
702
703 dev->flags |= MLX4_FLAG_MSI_X;
704 return;
705 }
706
707no_msi:
708 for (i = 0; i < MLX4_NUM_EQ; ++i)
709 priv->eq_table.eq[i].irq = dev->pdev->irq;
710}
711
712static int __devinit mlx4_init_one(struct pci_dev *pdev,
713 const struct pci_device_id *id)
714{
715 static int mlx4_version_printed;
716 struct mlx4_priv *priv;
717 struct mlx4_dev *dev;
718 int err;
719
720 if (!mlx4_version_printed) {
721 printk(KERN_INFO "%s", mlx4_version);
722 ++mlx4_version_printed;
723 }
724
725 printk(KERN_INFO PFX "Initializing %s\n",
726 pci_name(pdev));
727
728 err = pci_enable_device(pdev);
729 if (err) {
730 dev_err(&pdev->dev, "Cannot enable PCI device, "
731 "aborting.\n");
732 return err;
733 }
734
735 /*
736 * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
737 * be present)
738 */
739 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
740 pci_resource_len(pdev, 0) != 1 << 20) {
741 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
742 err = -ENODEV;
743 goto err_disable_pdev;
744 }
745 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
746 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
747 err = -ENODEV;
748 goto err_disable_pdev;
749 }
750
751 err = pci_request_region(pdev, 0, DRV_NAME);
752 if (err) {
753 dev_err(&pdev->dev, "Cannot request control region, aborting.\n");
754 goto err_disable_pdev;
755 }
756
757 err = pci_request_region(pdev, 2, DRV_NAME);
758 if (err) {
759 dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n");
760 goto err_release_bar0;
761 }
762
763 pci_set_master(pdev);
764
765 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
766 if (err) {
767 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
768 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
769 if (err) {
770 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
771 goto err_release_bar2;
772 }
773 }
774 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
775 if (err) {
776 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
777 "consistent PCI DMA mask.\n");
778 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
779 if (err) {
780 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
781 "aborting.\n");
782 goto err_release_bar2;
783 }
784 }
785
786 priv = kzalloc(sizeof *priv, GFP_KERNEL);
787 if (!priv) {
788 dev_err(&pdev->dev, "Device struct alloc failed, "
789 "aborting.\n");
790 err = -ENOMEM;
791 goto err_release_bar2;
792 }
793
794 dev = &priv->dev;
795 dev->pdev = pdev;
b581401e
RD		 796 INIT_LIST_HEAD(&priv->ctx_list);
797 spin_lock_init(&priv->ctx_lock);
225c7b1f
RD		 798
799 /*
800 * Now reset the HCA before we touch the PCI capabilities or
801 * attempt a firmware command, since a boot ROM may have left
802 * the HCA in an undefined state.
803 */
804 err = mlx4_reset(dev);
805 if (err) {
806 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
807 goto err_free_dev;
808 }
809
225c7b1f
RD		 810 if (mlx4_cmd_init(dev)) {
811 mlx4_err(dev, "Failed to init command interface, aborting.\n");
812 goto err_free_dev;
813 }
814
815 err = mlx4_init_hca(dev);
816 if (err)
817 goto err_cmd;
818
08fb1055
MT		 819 mlx4_enable_msi_x(dev);
820
225c7b1f 821 err = mlx4_setup_hca(dev);
08fb1055
MT		 822 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
823 dev->flags &= ~MLX4_FLAG_MSI_X;
824 pci_disable_msix(pdev);
825 err = mlx4_setup_hca(dev);
826 }
827
225c7b1f
RD		 828 if (err)
829 goto err_close;
830
831 err = mlx4_register_device(dev);
832 if (err)
833 goto err_cleanup;
834
835 pci_set_drvdata(pdev, dev);
836
837 return 0;
838
839err_cleanup:
840 mlx4_cleanup_mcg_table(dev);
841 mlx4_cleanup_qp_table(dev);
842 mlx4_cleanup_srq_table(dev);
843 mlx4_cleanup_cq_table(dev);
844 mlx4_cmd_use_polling(dev);
845 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 846 mlx4_cleanup_mr_table(dev);
847 mlx4_cleanup_pd_table(dev);
848 mlx4_cleanup_uar_table(dev);
849
850err_close:
08fb1055
MT		 851 if (dev->flags & MLX4_FLAG_MSI_X)
852 pci_disable_msix(pdev);
853
225c7b1f
RD		 854 mlx4_close_hca(dev);
855
856err_cmd:
857 mlx4_cmd_cleanup(dev);
858
859err_free_dev:
225c7b1f
RD		 860 kfree(priv);
861
862err_release_bar2:
863 pci_release_region(pdev, 2);
864
865err_release_bar0:
866 pci_release_region(pdev, 0);
867
868err_disable_pdev:
869 pci_disable_device(pdev);
870 pci_set_drvdata(pdev, NULL);
871 return err;
872}
873
874static void __devexit mlx4_remove_one(struct pci_dev *pdev)
875{
876 struct mlx4_dev *dev = pci_get_drvdata(pdev);
877 struct mlx4_priv *priv = mlx4_priv(dev);
878 int p;
879
880 if (dev) {
881 mlx4_unregister_device(dev);
882
883 for (p = 1; p <= dev->caps.num_ports; ++p)
884 mlx4_CLOSE_PORT(dev, p);
885
886 mlx4_cleanup_mcg_table(dev);
887 mlx4_cleanup_qp_table(dev);
888 mlx4_cleanup_srq_table(dev);
889 mlx4_cleanup_cq_table(dev);
890 mlx4_cmd_use_polling(dev);
891 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 892 mlx4_cleanup_mr_table(dev);
893 mlx4_cleanup_pd_table(dev);
894
895 iounmap(priv->kar);
896 mlx4_uar_free(dev, &priv->driver_uar);
897 mlx4_cleanup_uar_table(dev);
898 mlx4_close_hca(dev);
899 mlx4_cmd_cleanup(dev);
900
901 if (dev->flags & MLX4_FLAG_MSI_X)
902 pci_disable_msix(pdev);
903
904 kfree(priv);
905 pci_release_region(pdev, 2);
906 pci_release_region(pdev, 0);
907 pci_disable_device(pdev);
908 pci_set_drvdata(pdev, NULL);
909 }
910}
911
ee49bd93
JM		 912int mlx4_restart_one(struct pci_dev *pdev)
913{
914 mlx4_remove_one(pdev);
915 return mlx4_init_one(pdev, NULL);
916}
917
225c7b1f
RD		 918static struct pci_device_id mlx4_pci_table[] = {
919 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
920 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
921 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
786f238e
JM		 922 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
923 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
225c7b1f
RD		 924 { 0, }
925};
926
927MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
928
929static struct pci_driver mlx4_driver = {
930 .name = DRV_NAME,
931 .id_table = mlx4_pci_table,
932 .probe = mlx4_init_one,
933 .remove = __devexit_p(mlx4_remove_one)
934};
935
936static int __init mlx4_init(void)
937{
938 int ret;
939
ee49bd93
JM		 940 ret = mlx4_catas_init();
941 if (ret)
942 return ret;
943
225c7b1f
RD		 944 ret = pci_register_driver(&mlx4_driver);
945 return ret < 0 ? ret : 0;
946}
947
948static void __exit mlx4_cleanup(void)
949{
950 pci_unregister_driver(&mlx4_driver);
ee49bd93 951 mlx4_catas_cleanup();
225c7b1f
RD		 952}
953
954module_init(mlx4_init);
955module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)