Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
2a1d9b7f | 3 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. |
3d155f8c | 4 | * Copyright (c) 2005 Cisco Systems. All rights reserved. |
1da177e4 LT |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | * | |
34 | * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $ | |
35 | */ | |
36 | ||
37 | #include <linux/sched.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/errno.h> | |
40 | #include <asm/io.h> | |
a4d61e84 | 41 | #include <rdma/ib_mad.h> |
1da177e4 LT |
42 | |
43 | #include "mthca_dev.h" | |
44 | #include "mthca_config_reg.h" | |
45 | #include "mthca_cmd.h" | |
46 | #include "mthca_memfree.h" | |
47 | ||
48 | #define CMD_POLL_TOKEN 0xffff | |
49 | ||
50 | enum { | |
51 | HCR_IN_PARAM_OFFSET = 0x00, | |
52 | HCR_IN_MODIFIER_OFFSET = 0x08, | |
53 | HCR_OUT_PARAM_OFFSET = 0x0c, | |
54 | HCR_TOKEN_OFFSET = 0x14, | |
55 | HCR_STATUS_OFFSET = 0x18, | |
56 | ||
57 | HCR_OPMOD_SHIFT = 12, | |
58 | HCA_E_BIT = 22, | |
59 | HCR_GO_BIT = 23 | |
60 | }; | |
61 | ||
62 | enum { | |
63 | /* initialization and general commands */ | |
64 | CMD_SYS_EN = 0x1, | |
65 | CMD_SYS_DIS = 0x2, | |
66 | CMD_MAP_FA = 0xfff, | |
67 | CMD_UNMAP_FA = 0xffe, | |
68 | CMD_RUN_FW = 0xff6, | |
69 | CMD_MOD_STAT_CFG = 0x34, | |
70 | CMD_QUERY_DEV_LIM = 0x3, | |
71 | CMD_QUERY_FW = 0x4, | |
72 | CMD_ENABLE_LAM = 0xff8, | |
73 | CMD_DISABLE_LAM = 0xff7, | |
74 | CMD_QUERY_DDR = 0x5, | |
75 | CMD_QUERY_ADAPTER = 0x6, | |
76 | CMD_INIT_HCA = 0x7, | |
77 | CMD_CLOSE_HCA = 0x8, | |
78 | CMD_INIT_IB = 0x9, | |
79 | CMD_CLOSE_IB = 0xa, | |
80 | CMD_QUERY_HCA = 0xb, | |
81 | CMD_SET_IB = 0xc, | |
82 | CMD_ACCESS_DDR = 0x2e, | |
83 | CMD_MAP_ICM = 0xffa, | |
84 | CMD_UNMAP_ICM = 0xff9, | |
85 | CMD_MAP_ICM_AUX = 0xffc, | |
86 | CMD_UNMAP_ICM_AUX = 0xffb, | |
87 | CMD_SET_ICM_SIZE = 0xffd, | |
88 | ||
89 | /* TPT commands */ | |
90 | CMD_SW2HW_MPT = 0xd, | |
91 | CMD_QUERY_MPT = 0xe, | |
92 | CMD_HW2SW_MPT = 0xf, | |
93 | CMD_READ_MTT = 0x10, | |
94 | CMD_WRITE_MTT = 0x11, | |
95 | CMD_SYNC_TPT = 0x2f, | |
96 | ||
97 | /* EQ commands */ | |
98 | CMD_MAP_EQ = 0x12, | |
99 | CMD_SW2HW_EQ = 0x13, | |
100 | CMD_HW2SW_EQ = 0x14, | |
101 | CMD_QUERY_EQ = 0x15, | |
102 | ||
103 | /* CQ commands */ | |
104 | CMD_SW2HW_CQ = 0x16, | |
105 | CMD_HW2SW_CQ = 0x17, | |
106 | CMD_QUERY_CQ = 0x18, | |
107 | CMD_RESIZE_CQ = 0x2c, | |
108 | ||
109 | /* SRQ commands */ | |
110 | CMD_SW2HW_SRQ = 0x35, | |
111 | CMD_HW2SW_SRQ = 0x36, | |
112 | CMD_QUERY_SRQ = 0x37, | |
ec34a922 | 113 | CMD_ARM_SRQ = 0x40, |
1da177e4 LT |
114 | |
115 | /* QP/EE commands */ | |
116 | CMD_RST2INIT_QPEE = 0x19, | |
117 | CMD_INIT2RTR_QPEE = 0x1a, | |
118 | CMD_RTR2RTS_QPEE = 0x1b, | |
119 | CMD_RTS2RTS_QPEE = 0x1c, | |
120 | CMD_SQERR2RTS_QPEE = 0x1d, | |
121 | CMD_2ERR_QPEE = 0x1e, | |
122 | CMD_RTS2SQD_QPEE = 0x1f, | |
123 | CMD_SQD2SQD_QPEE = 0x38, | |
124 | CMD_SQD2RTS_QPEE = 0x20, | |
125 | CMD_ERR2RST_QPEE = 0x21, | |
126 | CMD_QUERY_QPEE = 0x22, | |
127 | CMD_INIT2INIT_QPEE = 0x2d, | |
128 | CMD_SUSPEND_QPEE = 0x32, | |
129 | CMD_UNSUSPEND_QPEE = 0x33, | |
130 | /* special QPs and management commands */ | |
131 | CMD_CONF_SPECIAL_QP = 0x23, | |
132 | CMD_MAD_IFC = 0x24, | |
133 | ||
134 | /* multicast commands */ | |
135 | CMD_READ_MGM = 0x25, | |
136 | CMD_WRITE_MGM = 0x26, | |
137 | CMD_MGID_HASH = 0x27, | |
138 | ||
139 | /* miscellaneous commands */ | |
140 | CMD_DIAG_RPRT = 0x30, | |
141 | CMD_NOP = 0x31, | |
142 | ||
143 | /* debug commands */ | |
144 | CMD_QUERY_DEBUG_MSG = 0x2a, | |
145 | CMD_SET_DEBUG_MSG = 0x2b, | |
146 | }; | |
147 | ||
148 | /* | |
149 | * According to Mellanox code, FW may be starved and never complete | |
150 | * commands. So we can't use strict timeouts described in PRM -- we | |
151 | * just arbitrarily select 60 seconds for now. | |
152 | */ | |
153 | #if 0 | |
154 | /* | |
155 | * Round up and add 1 to make sure we get the full wait time (since we | |
156 | * will be starting in the middle of a jiffy) | |
157 | */ | |
158 | enum { | |
159 | CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1, | |
160 | CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1, | |
161 | CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1 | |
162 | }; | |
163 | #else | |
164 | enum { | |
165 | CMD_TIME_CLASS_A = 60 * HZ, | |
166 | CMD_TIME_CLASS_B = 60 * HZ, | |
167 | CMD_TIME_CLASS_C = 60 * HZ | |
168 | }; | |
169 | #endif | |
170 | ||
171 | enum { | |
172 | GO_BIT_TIMEOUT = HZ * 10 | |
173 | }; | |
174 | ||
175 | struct mthca_cmd_context { | |
176 | struct completion done; | |
177 | struct timer_list timer; | |
178 | int result; | |
179 | int next; | |
180 | u64 out_param; | |
181 | u16 token; | |
182 | u8 status; | |
183 | }; | |
184 | ||
185 | static inline int go_bit(struct mthca_dev *dev) | |
186 | { | |
187 | return readl(dev->hcr + HCR_STATUS_OFFSET) & | |
188 | swab32(1 << HCR_GO_BIT); | |
189 | } | |
190 | ||
191 | static int mthca_cmd_post(struct mthca_dev *dev, | |
192 | u64 in_param, | |
193 | u64 out_param, | |
194 | u32 in_modifier, | |
195 | u8 op_modifier, | |
196 | u16 op, | |
197 | u16 token, | |
198 | int event) | |
199 | { | |
200 | int err = 0; | |
201 | ||
202 | if (down_interruptible(&dev->cmd.hcr_sem)) | |
203 | return -EINTR; | |
204 | ||
205 | if (event) { | |
206 | unsigned long end = jiffies + GO_BIT_TIMEOUT; | |
207 | ||
208 | while (go_bit(dev) && time_before(jiffies, end)) { | |
209 | set_current_state(TASK_RUNNING); | |
210 | schedule(); | |
211 | } | |
212 | } | |
213 | ||
214 | if (go_bit(dev)) { | |
215 | err = -EAGAIN; | |
216 | goto out; | |
217 | } | |
218 | ||
219 | /* | |
220 | * We use writel (instead of something like memcpy_toio) | |
221 | * because writes of less than 32 bits to the HCR don't work | |
222 | * (and some architectures such as ia64 implement memcpy_toio | |
223 | * in terms of writeb). | |
224 | */ | |
97f52eb4 SH |
225 | __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); |
226 | __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); | |
227 | __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); | |
228 | __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4); | |
229 | __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4); | |
230 | __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4); | |
1da177e4 LT |
231 | |
232 | /* __raw_writel may not order writes. */ | |
233 | wmb(); | |
234 | ||
97f52eb4 SH |
235 | __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | |
236 | (event ? (1 << HCA_E_BIT) : 0) | | |
237 | (op_modifier << HCR_OPMOD_SHIFT) | | |
238 | op), dev->hcr + 6 * 4); | |
1da177e4 LT |
239 | |
240 | out: | |
241 | up(&dev->cmd.hcr_sem); | |
242 | return err; | |
243 | } | |
244 | ||
245 | static int mthca_cmd_poll(struct mthca_dev *dev, | |
246 | u64 in_param, | |
247 | u64 *out_param, | |
248 | int out_is_imm, | |
249 | u32 in_modifier, | |
250 | u8 op_modifier, | |
251 | u16 op, | |
252 | unsigned long timeout, | |
253 | u8 *status) | |
254 | { | |
255 | int err = 0; | |
256 | unsigned long end; | |
257 | ||
258 | if (down_interruptible(&dev->cmd.poll_sem)) | |
259 | return -EINTR; | |
260 | ||
261 | err = mthca_cmd_post(dev, in_param, | |
262 | out_param ? *out_param : 0, | |
263 | in_modifier, op_modifier, | |
264 | op, CMD_POLL_TOKEN, 0); | |
265 | if (err) | |
266 | goto out; | |
267 | ||
268 | end = timeout + jiffies; | |
269 | while (go_bit(dev) && time_before(jiffies, end)) { | |
270 | set_current_state(TASK_RUNNING); | |
271 | schedule(); | |
272 | } | |
273 | ||
274 | if (go_bit(dev)) { | |
275 | err = -EBUSY; | |
276 | goto out; | |
277 | } | |
278 | ||
97f52eb4 SH |
279 | if (out_is_imm) |
280 | *out_param = | |
281 | (u64) be32_to_cpu((__force __be32) | |
282 | __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | | |
283 | (u64) be32_to_cpu((__force __be32) | |
284 | __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); | |
1da177e4 | 285 | |
97f52eb4 | 286 | *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24; |
1da177e4 LT |
287 | |
288 | out: | |
289 | up(&dev->cmd.poll_sem); | |
290 | return err; | |
291 | } | |
292 | ||
293 | void mthca_cmd_event(struct mthca_dev *dev, | |
294 | u16 token, | |
295 | u8 status, | |
296 | u64 out_param) | |
297 | { | |
298 | struct mthca_cmd_context *context = | |
299 | &dev->cmd.context[token & dev->cmd.token_mask]; | |
300 | ||
301 | /* previously timed out command completing at long last */ | |
302 | if (token != context->token) | |
303 | return; | |
304 | ||
305 | context->result = 0; | |
306 | context->status = status; | |
307 | context->out_param = out_param; | |
308 | ||
309 | context->token += dev->cmd.token_mask + 1; | |
310 | ||
311 | complete(&context->done); | |
312 | } | |
313 | ||
314 | static void event_timeout(unsigned long context_ptr) | |
315 | { | |
316 | struct mthca_cmd_context *context = | |
317 | (struct mthca_cmd_context *) context_ptr; | |
318 | ||
319 | context->result = -EBUSY; | |
320 | complete(&context->done); | |
321 | } | |
322 | ||
323 | static int mthca_cmd_wait(struct mthca_dev *dev, | |
324 | u64 in_param, | |
325 | u64 *out_param, | |
326 | int out_is_imm, | |
327 | u32 in_modifier, | |
328 | u8 op_modifier, | |
329 | u16 op, | |
330 | unsigned long timeout, | |
331 | u8 *status) | |
332 | { | |
333 | int err = 0; | |
334 | struct mthca_cmd_context *context; | |
335 | ||
336 | if (down_interruptible(&dev->cmd.event_sem)) | |
337 | return -EINTR; | |
338 | ||
339 | spin_lock(&dev->cmd.context_lock); | |
340 | BUG_ON(dev->cmd.free_head < 0); | |
341 | context = &dev->cmd.context[dev->cmd.free_head]; | |
342 | dev->cmd.free_head = context->next; | |
343 | spin_unlock(&dev->cmd.context_lock); | |
344 | ||
345 | init_completion(&context->done); | |
346 | ||
347 | err = mthca_cmd_post(dev, in_param, | |
348 | out_param ? *out_param : 0, | |
349 | in_modifier, op_modifier, | |
350 | op, context->token, 1); | |
351 | if (err) | |
352 | goto out; | |
353 | ||
354 | context->timer.expires = jiffies + timeout; | |
355 | add_timer(&context->timer); | |
356 | ||
357 | wait_for_completion(&context->done); | |
358 | del_timer_sync(&context->timer); | |
359 | ||
360 | err = context->result; | |
361 | if (err) | |
362 | goto out; | |
363 | ||
364 | *status = context->status; | |
365 | if (*status) | |
366 | mthca_dbg(dev, "Command %02x completed with status %02x\n", | |
367 | op, *status); | |
368 | ||
369 | if (out_is_imm) | |
370 | *out_param = context->out_param; | |
371 | ||
372 | out: | |
373 | spin_lock(&dev->cmd.context_lock); | |
374 | context->next = dev->cmd.free_head; | |
375 | dev->cmd.free_head = context - dev->cmd.context; | |
376 | spin_unlock(&dev->cmd.context_lock); | |
377 | ||
378 | up(&dev->cmd.event_sem); | |
379 | return err; | |
380 | } | |
381 | ||
382 | /* Invoke a command with an output mailbox */ | |
383 | static int mthca_cmd_box(struct mthca_dev *dev, | |
384 | u64 in_param, | |
385 | u64 out_param, | |
386 | u32 in_modifier, | |
387 | u8 op_modifier, | |
388 | u16 op, | |
389 | unsigned long timeout, | |
390 | u8 *status) | |
391 | { | |
392 | if (dev->cmd.use_events) | |
393 | return mthca_cmd_wait(dev, in_param, &out_param, 0, | |
394 | in_modifier, op_modifier, op, | |
395 | timeout, status); | |
396 | else | |
397 | return mthca_cmd_poll(dev, in_param, &out_param, 0, | |
398 | in_modifier, op_modifier, op, | |
399 | timeout, status); | |
400 | } | |
401 | ||
402 | /* Invoke a command with no output parameter */ | |
403 | static int mthca_cmd(struct mthca_dev *dev, | |
404 | u64 in_param, | |
405 | u32 in_modifier, | |
406 | u8 op_modifier, | |
407 | u16 op, | |
408 | unsigned long timeout, | |
409 | u8 *status) | |
410 | { | |
411 | return mthca_cmd_box(dev, in_param, 0, in_modifier, | |
412 | op_modifier, op, timeout, status); | |
413 | } | |
414 | ||
415 | /* | |
416 | * Invoke a command with an immediate output parameter (and copy the | |
417 | * output into the caller's out_param pointer after the command | |
418 | * executes). | |
419 | */ | |
420 | static int mthca_cmd_imm(struct mthca_dev *dev, | |
421 | u64 in_param, | |
422 | u64 *out_param, | |
423 | u32 in_modifier, | |
424 | u8 op_modifier, | |
425 | u16 op, | |
426 | unsigned long timeout, | |
427 | u8 *status) | |
428 | { | |
429 | if (dev->cmd.use_events) | |
430 | return mthca_cmd_wait(dev, in_param, out_param, 1, | |
431 | in_modifier, op_modifier, op, | |
432 | timeout, status); | |
433 | else | |
434 | return mthca_cmd_poll(dev, in_param, out_param, 1, | |
435 | in_modifier, op_modifier, op, | |
436 | timeout, status); | |
437 | } | |
438 | ||
80fd8238 RD |
439 | int mthca_cmd_init(struct mthca_dev *dev) |
440 | { | |
441 | sema_init(&dev->cmd.hcr_sem, 1); | |
442 | sema_init(&dev->cmd.poll_sem, 1); | |
443 | dev->cmd.use_events = 0; | |
444 | ||
445 | dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE, | |
446 | MTHCA_HCR_SIZE); | |
447 | if (!dev->hcr) { | |
448 | mthca_err(dev, "Couldn't map command register."); | |
449 | return -ENOMEM; | |
450 | } | |
451 | ||
ed878458 RD |
452 | dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev, |
453 | MTHCA_MAILBOX_SIZE, | |
454 | MTHCA_MAILBOX_SIZE, 0); | |
455 | if (!dev->cmd.pool) { | |
456 | iounmap(dev->hcr); | |
457 | return -ENOMEM; | |
458 | } | |
459 | ||
80fd8238 RD |
460 | return 0; |
461 | } | |
462 | ||
463 | void mthca_cmd_cleanup(struct mthca_dev *dev) | |
464 | { | |
ed878458 | 465 | pci_pool_destroy(dev->cmd.pool); |
80fd8238 RD |
466 | iounmap(dev->hcr); |
467 | } | |
468 | ||
1da177e4 LT |
469 | /* |
470 | * Switch to using events to issue FW commands (should be called after | |
471 | * event queue to command events has been initialized). | |
472 | */ | |
473 | int mthca_cmd_use_events(struct mthca_dev *dev) | |
474 | { | |
475 | int i; | |
476 | ||
477 | dev->cmd.context = kmalloc(dev->cmd.max_cmds * | |
478 | sizeof (struct mthca_cmd_context), | |
479 | GFP_KERNEL); | |
480 | if (!dev->cmd.context) | |
481 | return -ENOMEM; | |
482 | ||
483 | for (i = 0; i < dev->cmd.max_cmds; ++i) { | |
484 | dev->cmd.context[i].token = i; | |
485 | dev->cmd.context[i].next = i + 1; | |
486 | init_timer(&dev->cmd.context[i].timer); | |
487 | dev->cmd.context[i].timer.data = | |
488 | (unsigned long) &dev->cmd.context[i]; | |
489 | dev->cmd.context[i].timer.function = event_timeout; | |
490 | } | |
491 | ||
492 | dev->cmd.context[dev->cmd.max_cmds - 1].next = -1; | |
493 | dev->cmd.free_head = 0; | |
494 | ||
495 | sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds); | |
496 | spin_lock_init(&dev->cmd.context_lock); | |
497 | ||
498 | for (dev->cmd.token_mask = 1; | |
499 | dev->cmd.token_mask < dev->cmd.max_cmds; | |
500 | dev->cmd.token_mask <<= 1) | |
501 | ; /* nothing */ | |
502 | --dev->cmd.token_mask; | |
503 | ||
504 | dev->cmd.use_events = 1; | |
505 | down(&dev->cmd.poll_sem); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | /* | |
511 | * Switch back to polling (used when shutting down the device) | |
512 | */ | |
513 | void mthca_cmd_use_polling(struct mthca_dev *dev) | |
514 | { | |
515 | int i; | |
516 | ||
517 | dev->cmd.use_events = 0; | |
518 | ||
519 | for (i = 0; i < dev->cmd.max_cmds; ++i) | |
520 | down(&dev->cmd.event_sem); | |
521 | ||
522 | kfree(dev->cmd.context); | |
523 | ||
524 | up(&dev->cmd.poll_sem); | |
525 | } | |
526 | ||
ed878458 | 527 | struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev, |
87b750dc | 528 | gfp_t gfp_mask) |
ed878458 RD |
529 | { |
530 | struct mthca_mailbox *mailbox; | |
531 | ||
532 | mailbox = kmalloc(sizeof *mailbox, gfp_mask); | |
533 | if (!mailbox) | |
534 | return ERR_PTR(-ENOMEM); | |
535 | ||
536 | mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); | |
537 | if (!mailbox->buf) { | |
538 | kfree(mailbox); | |
539 | return ERR_PTR(-ENOMEM); | |
540 | } | |
541 | ||
542 | return mailbox; | |
543 | } | |
544 | ||
545 | void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox) | |
546 | { | |
547 | if (!mailbox) | |
548 | return; | |
549 | ||
550 | pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma); | |
551 | kfree(mailbox); | |
552 | } | |
553 | ||
1da177e4 LT |
554 | int mthca_SYS_EN(struct mthca_dev *dev, u8 *status) |
555 | { | |
556 | u64 out; | |
557 | int ret; | |
558 | ||
559 | ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status); | |
560 | ||
561 | if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR) | |
562 | mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, " | |
563 | "sladdr=%d, SPD source=%s\n", | |
564 | (int) (out >> 6) & 0xf, (int) (out >> 4) & 3, | |
565 | (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM"); | |
566 | ||
567 | return ret; | |
568 | } | |
569 | ||
570 | int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status) | |
571 | { | |
572 | return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status); | |
573 | } | |
574 | ||
575 | static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm, | |
576 | u64 virt, u8 *status) | |
577 | { | |
ed878458 | 578 | struct mthca_mailbox *mailbox; |
1da177e4 | 579 | struct mthca_icm_iter iter; |
ed878458 | 580 | __be64 *pages; |
1da177e4 LT |
581 | int lg; |
582 | int nent = 0; | |
583 | int i; | |
584 | int err = 0; | |
585 | int ts = 0, tc = 0; | |
586 | ||
ed878458 RD |
587 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
588 | if (IS_ERR(mailbox)) | |
589 | return PTR_ERR(mailbox); | |
590 | memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE); | |
591 | pages = mailbox->buf; | |
1da177e4 LT |
592 | |
593 | for (mthca_icm_first(icm, &iter); | |
594 | !mthca_icm_last(&iter); | |
595 | mthca_icm_next(&iter)) { | |
596 | /* | |
597 | * We have to pass pages that are aligned to their | |
598 | * size, so find the least significant 1 in the | |
599 | * address or size and use that as our log2 size. | |
600 | */ | |
601 | lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1; | |
602 | if (lg < 12) { | |
603 | mthca_warn(dev, "Got FW area not aligned to 4K (%llx/%lx).\n", | |
604 | (unsigned long long) mthca_icm_addr(&iter), | |
605 | mthca_icm_size(&iter)); | |
606 | err = -EINVAL; | |
607 | goto out; | |
608 | } | |
44dd823b | 609 | for (i = 0; i < mthca_icm_size(&iter) / (1 << lg); ++i) { |
1da177e4 | 610 | if (virt != -1) { |
ed878458 | 611 | pages[nent * 2] = cpu_to_be64(virt); |
1da177e4 LT |
612 | virt += 1 << lg; |
613 | } | |
614 | ||
ed878458 RD |
615 | pages[nent * 2 + 1] = cpu_to_be64((mthca_icm_addr(&iter) + |
616 | (i << lg)) | (lg - 12)); | |
1da177e4 LT |
617 | ts += 1 << (lg - 10); |
618 | ++tc; | |
619 | ||
44dd823b | 620 | if (++nent == MTHCA_MAILBOX_SIZE / 16) { |
ed878458 | 621 | err = mthca_cmd(dev, mailbox->dma, nent, 0, op, |
1da177e4 LT |
622 | CMD_TIME_CLASS_B, status); |
623 | if (err || *status) | |
624 | goto out; | |
625 | nent = 0; | |
626 | } | |
627 | } | |
628 | } | |
629 | ||
630 | if (nent) | |
ed878458 | 631 | err = mthca_cmd(dev, mailbox->dma, nent, 0, op, |
1da177e4 LT |
632 | CMD_TIME_CLASS_B, status); |
633 | ||
634 | switch (op) { | |
635 | case CMD_MAP_FA: | |
636 | mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); | |
637 | break; | |
638 | case CMD_MAP_ICM_AUX: | |
639 | mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); | |
640 | break; | |
641 | case CMD_MAP_ICM: | |
642 | mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", | |
643 | tc, ts, (unsigned long long) virt - (ts << 10)); | |
644 | break; | |
645 | } | |
646 | ||
647 | out: | |
ed878458 | 648 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
649 | return err; |
650 | } | |
651 | ||
652 | int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status) | |
653 | { | |
654 | return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status); | |
655 | } | |
656 | ||
657 | int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status) | |
658 | { | |
659 | return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status); | |
660 | } | |
661 | ||
662 | int mthca_RUN_FW(struct mthca_dev *dev, u8 *status) | |
663 | { | |
664 | return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status); | |
665 | } | |
666 | ||
667 | int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status) | |
668 | { | |
ed878458 | 669 | struct mthca_mailbox *mailbox; |
1da177e4 | 670 | u32 *outbox; |
1da177e4 LT |
671 | int err = 0; |
672 | u8 lg; | |
673 | ||
674 | #define QUERY_FW_OUT_SIZE 0x100 | |
675 | #define QUERY_FW_VER_OFFSET 0x00 | |
676 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f | |
677 | #define QUERY_FW_ERR_START_OFFSET 0x30 | |
678 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 | |
679 | ||
680 | #define QUERY_FW_START_OFFSET 0x20 | |
681 | #define QUERY_FW_END_OFFSET 0x28 | |
682 | ||
683 | #define QUERY_FW_SIZE_OFFSET 0x00 | |
684 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 | |
685 | #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40 | |
686 | #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48 | |
687 | ||
ed878458 RD |
688 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
689 | if (IS_ERR(mailbox)) | |
690 | return PTR_ERR(mailbox); | |
691 | outbox = mailbox->buf; | |
1da177e4 | 692 | |
ed878458 | 693 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW, |
1da177e4 LT |
694 | CMD_TIME_CLASS_A, status); |
695 | ||
696 | if (err) | |
697 | goto out; | |
698 | ||
699 | MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET); | |
700 | /* | |
701 | * FW subminor version is at more signifant bits than minor | |
702 | * version, so swap here. | |
703 | */ | |
704 | dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) | | |
705 | ((dev->fw_ver & 0xffff0000ull) >> 16) | | |
706 | ((dev->fw_ver & 0x0000ffffull) << 16); | |
707 | ||
708 | MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); | |
709 | dev->cmd.max_cmds = 1 << lg; | |
3d155f8c RD |
710 | MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET); |
711 | MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET); | |
1da177e4 LT |
712 | |
713 | mthca_dbg(dev, "FW version %012llx, max commands %d\n", | |
714 | (unsigned long long) dev->fw_ver, dev->cmd.max_cmds); | |
3d155f8c RD |
715 | mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n", |
716 | (unsigned long long) dev->catas_err.addr, dev->catas_err.size); | |
1da177e4 | 717 | |
d10ddbf6 | 718 | if (mthca_is_memfree(dev)) { |
1da177e4 LT |
719 | MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET); |
720 | MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); | |
721 | MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET); | |
722 | MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET); | |
723 | mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2); | |
724 | ||
725 | /* | |
726 | * Arbel page size is always 4 KB; round up number of | |
727 | * system pages needed. | |
728 | */ | |
729 | dev->fw.arbel.fw_pages = | |
730 | (dev->fw.arbel.fw_pages + (1 << (PAGE_SHIFT - 12)) - 1) >> | |
731 | (PAGE_SHIFT - 12); | |
732 | ||
733 | mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n", | |
734 | (unsigned long long) dev->fw.arbel.clr_int_base, | |
735 | (unsigned long long) dev->fw.arbel.eq_arm_base, | |
736 | (unsigned long long) dev->fw.arbel.eq_set_ci_base); | |
737 | } else { | |
738 | MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET); | |
739 | MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET); | |
740 | ||
741 | mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n", | |
742 | (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10), | |
743 | (unsigned long long) dev->fw.tavor.fw_start, | |
744 | (unsigned long long) dev->fw.tavor.fw_end); | |
745 | } | |
746 | ||
747 | out: | |
ed878458 | 748 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
749 | return err; |
750 | } | |
751 | ||
752 | int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status) | |
753 | { | |
ed878458 | 754 | struct mthca_mailbox *mailbox; |
1da177e4 LT |
755 | u8 info; |
756 | u32 *outbox; | |
1da177e4 LT |
757 | int err = 0; |
758 | ||
759 | #define ENABLE_LAM_OUT_SIZE 0x100 | |
760 | #define ENABLE_LAM_START_OFFSET 0x00 | |
761 | #define ENABLE_LAM_END_OFFSET 0x08 | |
762 | #define ENABLE_LAM_INFO_OFFSET 0x13 | |
763 | ||
764 | #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4) | |
765 | #define ENABLE_LAM_INFO_ECC_MASK 0x3 | |
766 | ||
ed878458 RD |
767 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
768 | if (IS_ERR(mailbox)) | |
769 | return PTR_ERR(mailbox); | |
770 | outbox = mailbox->buf; | |
1da177e4 | 771 | |
ed878458 | 772 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM, |
1da177e4 LT |
773 | CMD_TIME_CLASS_C, status); |
774 | ||
775 | if (err) | |
776 | goto out; | |
777 | ||
778 | if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE) | |
779 | goto out; | |
780 | ||
781 | MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET); | |
782 | MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET); | |
783 | MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET); | |
784 | ||
785 | if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) != | |
786 | !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { | |
787 | mthca_info(dev, "FW reports that HCA-attached memory " | |
788 | "is %s hidden; does not match PCI config\n", | |
789 | (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ? | |
790 | "" : "not"); | |
791 | } | |
792 | if (info & ENABLE_LAM_INFO_HIDDEN_FLAG) | |
793 | mthca_dbg(dev, "HCA-attached memory is hidden.\n"); | |
794 | ||
795 | mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", | |
796 | (int) ((dev->ddr_end - dev->ddr_start) >> 10), | |
797 | (unsigned long long) dev->ddr_start, | |
798 | (unsigned long long) dev->ddr_end); | |
799 | ||
800 | out: | |
ed878458 | 801 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
802 | return err; |
803 | } | |
804 | ||
805 | int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status) | |
806 | { | |
807 | return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status); | |
808 | } | |
809 | ||
810 | int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status) | |
811 | { | |
ed878458 | 812 | struct mthca_mailbox *mailbox; |
1da177e4 LT |
813 | u8 info; |
814 | u32 *outbox; | |
1da177e4 LT |
815 | int err = 0; |
816 | ||
817 | #define QUERY_DDR_OUT_SIZE 0x100 | |
818 | #define QUERY_DDR_START_OFFSET 0x00 | |
819 | #define QUERY_DDR_END_OFFSET 0x08 | |
820 | #define QUERY_DDR_INFO_OFFSET 0x13 | |
821 | ||
822 | #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4) | |
823 | #define QUERY_DDR_INFO_ECC_MASK 0x3 | |
824 | ||
ed878458 RD |
825 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
826 | if (IS_ERR(mailbox)) | |
827 | return PTR_ERR(mailbox); | |
828 | outbox = mailbox->buf; | |
1da177e4 | 829 | |
ed878458 | 830 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR, |
1da177e4 LT |
831 | CMD_TIME_CLASS_A, status); |
832 | ||
833 | if (err) | |
834 | goto out; | |
835 | ||
836 | MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET); | |
837 | MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET); | |
838 | MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET); | |
839 | ||
840 | if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) != | |
841 | !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { | |
842 | mthca_info(dev, "FW reports that HCA-attached memory " | |
843 | "is %s hidden; does not match PCI config\n", | |
844 | (info & QUERY_DDR_INFO_HIDDEN_FLAG) ? | |
845 | "" : "not"); | |
846 | } | |
847 | if (info & QUERY_DDR_INFO_HIDDEN_FLAG) | |
848 | mthca_dbg(dev, "HCA-attached memory is hidden.\n"); | |
849 | ||
850 | mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", | |
851 | (int) ((dev->ddr_end - dev->ddr_start) >> 10), | |
852 | (unsigned long long) dev->ddr_start, | |
853 | (unsigned long long) dev->ddr_end); | |
854 | ||
855 | out: | |
ed878458 | 856 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
857 | return err; |
858 | } | |
859 | ||
860 | int mthca_QUERY_DEV_LIM(struct mthca_dev *dev, | |
861 | struct mthca_dev_lim *dev_lim, u8 *status) | |
862 | { | |
ed878458 | 863 | struct mthca_mailbox *mailbox; |
1da177e4 | 864 | u32 *outbox; |
1da177e4 LT |
865 | u8 field; |
866 | u16 size; | |
867 | int err; | |
868 | ||
869 | #define QUERY_DEV_LIM_OUT_SIZE 0x100 | |
870 | #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10 | |
871 | #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11 | |
872 | #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12 | |
873 | #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13 | |
874 | #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14 | |
875 | #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15 | |
876 | #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16 | |
877 | #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17 | |
878 | #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19 | |
879 | #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a | |
880 | #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b | |
881 | #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d | |
882 | #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e | |
883 | #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f | |
884 | #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20 | |
885 | #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21 | |
886 | #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22 | |
887 | #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23 | |
888 | #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27 | |
889 | #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29 | |
890 | #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b | |
891 | #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f | |
892 | #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33 | |
893 | #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35 | |
894 | #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36 | |
895 | #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37 | |
896 | #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b | |
897 | #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f | |
898 | #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44 | |
899 | #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48 | |
900 | #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49 | |
901 | #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b | |
902 | #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51 | |
903 | #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52 | |
904 | #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55 | |
905 | #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56 | |
906 | #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61 | |
907 | #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62 | |
908 | #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63 | |
909 | #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64 | |
910 | #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65 | |
911 | #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66 | |
912 | #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67 | |
913 | #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80 | |
914 | #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82 | |
915 | #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84 | |
916 | #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86 | |
917 | #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88 | |
918 | #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a | |
919 | #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c | |
920 | #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e | |
921 | #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90 | |
922 | #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92 | |
923 | #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96 | |
924 | #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97 | |
925 | #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98 | |
926 | #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f | |
927 | #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0 | |
928 | ||
ed878458 RD |
929 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
930 | if (IS_ERR(mailbox)) | |
931 | return PTR_ERR(mailbox); | |
932 | outbox = mailbox->buf; | |
1da177e4 | 933 | |
ed878458 | 934 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM, |
1da177e4 LT |
935 | CMD_TIME_CLASS_A, status); |
936 | ||
937 | if (err) | |
938 | goto out; | |
939 | ||
1da177e4 LT |
940 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET); |
941 | dev_lim->reserved_qps = 1 << (field & 0xf); | |
942 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET); | |
943 | dev_lim->max_qps = 1 << (field & 0x1f); | |
944 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET); | |
945 | dev_lim->reserved_srqs = 1 << (field >> 4); | |
946 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET); | |
947 | dev_lim->max_srqs = 1 << (field & 0x1f); | |
948 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET); | |
949 | dev_lim->reserved_eecs = 1 << (field & 0xf); | |
950 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET); | |
951 | dev_lim->max_eecs = 1 << (field & 0x1f); | |
952 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET); | |
953 | dev_lim->max_cq_sz = 1 << field; | |
954 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET); | |
955 | dev_lim->reserved_cqs = 1 << (field & 0xf); | |
956 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET); | |
957 | dev_lim->max_cqs = 1 << (field & 0x1f); | |
958 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET); | |
959 | dev_lim->max_mpts = 1 << (field & 0x3f); | |
960 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET); | |
961 | dev_lim->reserved_eqs = 1 << (field & 0xf); | |
962 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET); | |
963 | dev_lim->max_eqs = 1 << (field & 0x7); | |
964 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET); | |
965 | dev_lim->reserved_mtts = 1 << (field >> 4); | |
966 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET); | |
967 | dev_lim->max_mrw_sz = 1 << field; | |
968 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET); | |
969 | dev_lim->reserved_mrws = 1 << (field & 0xf); | |
970 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET); | |
971 | dev_lim->max_mtt_seg = 1 << (field & 0x3f); | |
972 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET); | |
973 | dev_lim->max_requester_per_qp = 1 << (field & 0x3f); | |
974 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET); | |
975 | dev_lim->max_responder_per_qp = 1 << (field & 0x3f); | |
976 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET); | |
977 | dev_lim->max_rdma_global = 1 << (field & 0x3f); | |
978 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET); | |
979 | dev_lim->local_ca_ack_delay = field & 0x1f; | |
980 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET); | |
981 | dev_lim->max_mtu = field >> 4; | |
982 | dev_lim->max_port_width = field & 0xf; | |
983 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET); | |
984 | dev_lim->max_vl = field >> 4; | |
985 | dev_lim->num_ports = field & 0xf; | |
986 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET); | |
987 | dev_lim->max_gids = 1 << (field & 0xf); | |
988 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET); | |
989 | dev_lim->max_pkeys = 1 << (field & 0xf); | |
990 | MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET); | |
991 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET); | |
992 | dev_lim->reserved_uars = field >> 4; | |
993 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET); | |
994 | dev_lim->uar_size = 1 << ((field & 0x3f) + 20); | |
995 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET); | |
996 | dev_lim->min_page_sz = 1 << field; | |
997 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET); | |
998 | dev_lim->max_sg = field; | |
999 | ||
1000 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET); | |
1001 | dev_lim->max_desc_sz = size; | |
1002 | ||
1003 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET); | |
1004 | dev_lim->max_qp_per_mcg = 1 << field; | |
1005 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET); | |
1006 | dev_lim->reserved_mgms = field & 0xf; | |
1007 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET); | |
1008 | dev_lim->max_mcgs = 1 << field; | |
1009 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET); | |
1010 | dev_lim->reserved_pds = field >> 4; | |
1011 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET); | |
1012 | dev_lim->max_pds = 1 << (field & 0x3f); | |
1013 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET); | |
1014 | dev_lim->reserved_rdds = field >> 4; | |
1015 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET); | |
1016 | dev_lim->max_rdds = 1 << (field & 0x3f); | |
1017 | ||
1018 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET); | |
1019 | dev_lim->eec_entry_sz = size; | |
1020 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET); | |
1021 | dev_lim->qpc_entry_sz = size; | |
1022 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET); | |
1023 | dev_lim->eeec_entry_sz = size; | |
1024 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET); | |
1025 | dev_lim->eqpc_entry_sz = size; | |
1026 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET); | |
1027 | dev_lim->eqc_entry_sz = size; | |
1028 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET); | |
1029 | dev_lim->cqc_entry_sz = size; | |
1030 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET); | |
1031 | dev_lim->srq_entry_sz = size; | |
1032 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET); | |
1033 | dev_lim->uar_scratch_entry_sz = size; | |
1034 | ||
1035 | mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", | |
1036 | dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz); | |
ec34a922 RD |
1037 | mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", |
1038 | dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz); | |
1da177e4 LT |
1039 | mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", |
1040 | dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz); | |
1041 | mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", | |
1042 | dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz); | |
1043 | mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", | |
1044 | dev_lim->reserved_mrws, dev_lim->reserved_mtts); | |
1045 | mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", | |
1046 | dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars); | |
1047 | mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", | |
1048 | dev_lim->max_pds, dev_lim->reserved_mgms); | |
efaae8f7 JM |
1049 | mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", |
1050 | dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz); | |
1da177e4 LT |
1051 | |
1052 | mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags); | |
1053 | ||
d10ddbf6 | 1054 | if (mthca_is_memfree(dev)) { |
a3c8ab4f JM |
1055 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); |
1056 | dev_lim->max_srq_sz = 1 << field; | |
1057 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); | |
1058 | dev_lim->max_qp_sz = 1 << field; | |
1da177e4 LT |
1059 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET); |
1060 | dev_lim->hca.arbel.resize_srq = field & 1; | |
8cf2daf3 RD |
1061 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET); |
1062 | dev_lim->max_sg = min_t(int, field, dev_lim->max_sg); | |
77369ed3 JM |
1063 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET); |
1064 | dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz); | |
1da177e4 LT |
1065 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET); |
1066 | dev_lim->mpt_entry_sz = size; | |
1067 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET); | |
1068 | dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f); | |
1069 | MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox, | |
1070 | QUERY_DEV_LIM_BMME_FLAGS_OFFSET); | |
1071 | MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox, | |
1072 | QUERY_DEV_LIM_RSVD_LKEY_OFFSET); | |
1073 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET); | |
1074 | dev_lim->hca.arbel.lam_required = field & 1; | |
1075 | MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox, | |
1076 | QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET); | |
1077 | ||
1078 | if (dev_lim->hca.arbel.bmme_flags & 1) | |
1079 | mthca_dbg(dev, "Base MM extensions: yes " | |
1080 | "(flags %d, max PBL %d, rsvd L_Key %08x)\n", | |
1081 | dev_lim->hca.arbel.bmme_flags, | |
1082 | dev_lim->hca.arbel.max_pbl_sz, | |
1083 | dev_lim->hca.arbel.reserved_lkey); | |
1084 | else | |
1085 | mthca_dbg(dev, "Base MM extensions: no\n"); | |
1086 | ||
1087 | mthca_dbg(dev, "Max ICM size %lld MB\n", | |
1088 | (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20); | |
1089 | } else { | |
a3c8ab4f JM |
1090 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); |
1091 | dev_lim->max_srq_sz = (1 << field) - 1; | |
1092 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); | |
1093 | dev_lim->max_qp_sz = (1 << field) - 1; | |
1da177e4 LT |
1094 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET); |
1095 | dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f); | |
1da177e4 LT |
1096 | dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE; |
1097 | } | |
1098 | ||
1099 | out: | |
ed878458 | 1100 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1101 | return err; |
1102 | } | |
1103 | ||
2e8b981c MT |
1104 | static void get_board_id(void *vsd, char *board_id) |
1105 | { | |
1106 | int i; | |
1107 | ||
1108 | #define VSD_OFFSET_SIG1 0x00 | |
1109 | #define VSD_OFFSET_SIG2 0xde | |
1110 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 | |
1111 | #define VSD_OFFSET_TS_BOARD_ID 0x20 | |
1112 | ||
1113 | #define VSD_SIGNATURE_TOPSPIN 0x5ad | |
1114 | ||
1115 | memset(board_id, 0, MTHCA_BOARD_ID_LEN); | |
1116 | ||
1117 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && | |
1118 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { | |
1119 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN); | |
1120 | } else { | |
1121 | /* | |
1122 | * The board ID is a string but the firmware byte | |
1123 | * swaps each 4-byte word before passing it back to | |
1124 | * us. Therefore we need to swab it before printing. | |
1125 | */ | |
1126 | for (i = 0; i < 4; ++i) | |
1127 | ((u32 *) board_id)[i] = | |
1128 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); | |
1129 | } | |
1130 | } | |
1131 | ||
1da177e4 LT |
1132 | int mthca_QUERY_ADAPTER(struct mthca_dev *dev, |
1133 | struct mthca_adapter *adapter, u8 *status) | |
1134 | { | |
ed878458 | 1135 | struct mthca_mailbox *mailbox; |
1da177e4 | 1136 | u32 *outbox; |
1da177e4 LT |
1137 | int err; |
1138 | ||
1139 | #define QUERY_ADAPTER_OUT_SIZE 0x100 | |
1140 | #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00 | |
1141 | #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04 | |
1142 | #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08 | |
1143 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 | |
2e8b981c | 1144 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 |
1da177e4 | 1145 | |
ed878458 RD |
1146 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1147 | if (IS_ERR(mailbox)) | |
1148 | return PTR_ERR(mailbox); | |
1149 | outbox = mailbox->buf; | |
1da177e4 | 1150 | |
ed878458 | 1151 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER, |
1da177e4 LT |
1152 | CMD_TIME_CLASS_A, status); |
1153 | ||
1154 | if (err) | |
1155 | goto out; | |
1156 | ||
ed878458 RD |
1157 | MTHCA_GET(adapter->vendor_id, outbox, QUERY_ADAPTER_VENDOR_ID_OFFSET); |
1158 | MTHCA_GET(adapter->device_id, outbox, QUERY_ADAPTER_DEVICE_ID_OFFSET); | |
1da177e4 | 1159 | MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET); |
ed878458 | 1160 | MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
1da177e4 | 1161 | |
2e8b981c MT |
1162 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, |
1163 | adapter->board_id); | |
1164 | ||
1da177e4 | 1165 | out: |
ed878458 | 1166 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1167 | return err; |
1168 | } | |
1169 | ||
1170 | int mthca_INIT_HCA(struct mthca_dev *dev, | |
1171 | struct mthca_init_hca_param *param, | |
1172 | u8 *status) | |
1173 | { | |
ed878458 | 1174 | struct mthca_mailbox *mailbox; |
97f52eb4 | 1175 | __be32 *inbox; |
1da177e4 LT |
1176 | int err; |
1177 | ||
1178 | #define INIT_HCA_IN_SIZE 0x200 | |
1179 | #define INIT_HCA_FLAGS_OFFSET 0x014 | |
1180 | #define INIT_HCA_QPC_OFFSET 0x020 | |
1181 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) | |
1182 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) | |
1183 | #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20) | |
1184 | #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27) | |
1185 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) | |
1186 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) | |
1187 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) | |
1188 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) | |
1189 | #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) | |
1190 | #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) | |
1191 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) | |
1192 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) | |
1193 | #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) | |
1194 | #define INIT_HCA_UDAV_OFFSET 0x0b0 | |
1195 | #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0) | |
1196 | #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4) | |
1197 | #define INIT_HCA_MCAST_OFFSET 0x0c0 | |
1198 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) | |
1199 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) | |
1200 | #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) | |
1201 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) | |
1202 | #define INIT_HCA_TPT_OFFSET 0x0f0 | |
1203 | #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) | |
1204 | #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09) | |
1205 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) | |
1206 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) | |
1207 | #define INIT_HCA_UAR_OFFSET 0x120 | |
1208 | #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00) | |
1209 | #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09) | |
1210 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) | |
1211 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) | |
1212 | #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10) | |
1213 | #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18) | |
1214 | ||
ed878458 RD |
1215 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1216 | if (IS_ERR(mailbox)) | |
1217 | return PTR_ERR(mailbox); | |
1218 | inbox = mailbox->buf; | |
1da177e4 LT |
1219 | |
1220 | memset(inbox, 0, INIT_HCA_IN_SIZE); | |
1221 | ||
1222 | #if defined(__LITTLE_ENDIAN) | |
1223 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); | |
1224 | #elif defined(__BIG_ENDIAN) | |
1225 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); | |
1226 | #else | |
1227 | #error Host endianness not defined | |
1228 | #endif | |
1229 | /* Check port for UD address vector: */ | |
1230 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); | |
1231 | ||
1232 | /* We leave wqe_quota, responder_exu, etc as 0 (default) */ | |
1233 | ||
1234 | /* QPC/EEC/CQC/EQC/RDB attributes */ | |
1235 | ||
1236 | MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); | |
1237 | MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); | |
1238 | MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET); | |
1239 | MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET); | |
1240 | MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); | |
1241 | MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); | |
1242 | MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); | |
1243 | MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); | |
1244 | MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET); | |
1245 | MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET); | |
1246 | MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); | |
1247 | MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); | |
1248 | MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET); | |
1249 | ||
1250 | /* UD AV attributes */ | |
1251 | ||
1252 | /* multicast attributes */ | |
1253 | ||
1254 | MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); | |
1255 | MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1256 | MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET); | |
1257 | MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
1258 | ||
1259 | /* TPT attributes */ | |
1260 | ||
1261 | MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET); | |
d10ddbf6 | 1262 | if (!mthca_is_memfree(dev)) |
1da177e4 LT |
1263 | MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET); |
1264 | MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); | |
1265 | MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); | |
1266 | ||
1267 | /* UAR attributes */ | |
1268 | { | |
1269 | u8 uar_page_sz = PAGE_SHIFT - 12; | |
1270 | MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); | |
1271 | } | |
1272 | ||
1273 | MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET); | |
1274 | ||
d10ddbf6 | 1275 | if (mthca_is_memfree(dev)) { |
1da177e4 LT |
1276 | MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET); |
1277 | MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); | |
1278 | MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET); | |
1279 | } | |
1280 | ||
ed878458 | 1281 | err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status); |
1da177e4 | 1282 | |
ed878458 | 1283 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1284 | return err; |
1285 | } | |
1286 | ||
1287 | int mthca_INIT_IB(struct mthca_dev *dev, | |
1288 | struct mthca_init_ib_param *param, | |
1289 | int port, u8 *status) | |
1290 | { | |
ed878458 | 1291 | struct mthca_mailbox *mailbox; |
1da177e4 | 1292 | u32 *inbox; |
1da177e4 LT |
1293 | int err; |
1294 | u32 flags; | |
1295 | ||
1296 | #define INIT_IB_IN_SIZE 56 | |
1297 | #define INIT_IB_FLAGS_OFFSET 0x00 | |
1298 | #define INIT_IB_FLAG_SIG (1 << 18) | |
1299 | #define INIT_IB_FLAG_NG (1 << 17) | |
1300 | #define INIT_IB_FLAG_G0 (1 << 16) | |
1da177e4 | 1301 | #define INIT_IB_VL_SHIFT 4 |
da6561c2 | 1302 | #define INIT_IB_PORT_WIDTH_SHIFT 8 |
1da177e4 LT |
1303 | #define INIT_IB_MTU_SHIFT 12 |
1304 | #define INIT_IB_MAX_GID_OFFSET 0x06 | |
1305 | #define INIT_IB_MAX_PKEY_OFFSET 0x0a | |
1306 | #define INIT_IB_GUID0_OFFSET 0x10 | |
1307 | #define INIT_IB_NODE_GUID_OFFSET 0x18 | |
1308 | #define INIT_IB_SI_GUID_OFFSET 0x20 | |
1309 | ||
ed878458 RD |
1310 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1311 | if (IS_ERR(mailbox)) | |
1312 | return PTR_ERR(mailbox); | |
1313 | inbox = mailbox->buf; | |
1da177e4 LT |
1314 | |
1315 | memset(inbox, 0, INIT_IB_IN_SIZE); | |
1316 | ||
1317 | flags = 0; | |
1da177e4 LT |
1318 | flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0; |
1319 | flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0; | |
1320 | flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0; | |
1321 | flags |= param->vl_cap << INIT_IB_VL_SHIFT; | |
da6561c2 | 1322 | flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT; |
1da177e4 LT |
1323 | flags |= param->mtu_cap << INIT_IB_MTU_SHIFT; |
1324 | MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET); | |
1325 | ||
1326 | MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET); | |
1327 | MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET); | |
1328 | MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET); | |
1329 | MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET); | |
1330 | MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET); | |
1331 | ||
ed878458 | 1332 | err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB, |
1da177e4 LT |
1333 | CMD_TIME_CLASS_A, status); |
1334 | ||
ed878458 | 1335 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1336 | return err; |
1337 | } | |
1338 | ||
1339 | int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status) | |
1340 | { | |
1341 | return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status); | |
1342 | } | |
1343 | ||
1344 | int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status) | |
1345 | { | |
1346 | return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status); | |
1347 | } | |
1348 | ||
1349 | int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param, | |
1350 | int port, u8 *status) | |
1351 | { | |
ed878458 | 1352 | struct mthca_mailbox *mailbox; |
1da177e4 | 1353 | u32 *inbox; |
1da177e4 LT |
1354 | int err; |
1355 | u32 flags = 0; | |
1356 | ||
1357 | #define SET_IB_IN_SIZE 0x40 | |
1358 | #define SET_IB_FLAGS_OFFSET 0x00 | |
1359 | #define SET_IB_FLAG_SIG (1 << 18) | |
1360 | #define SET_IB_FLAG_RQK (1 << 0) | |
1361 | #define SET_IB_CAP_MASK_OFFSET 0x04 | |
1362 | #define SET_IB_SI_GUID_OFFSET 0x08 | |
1363 | ||
ed878458 RD |
1364 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1365 | if (IS_ERR(mailbox)) | |
1366 | return PTR_ERR(mailbox); | |
1367 | inbox = mailbox->buf; | |
1da177e4 LT |
1368 | |
1369 | memset(inbox, 0, SET_IB_IN_SIZE); | |
1370 | ||
1371 | flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0; | |
1372 | flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0; | |
1373 | MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET); | |
1374 | ||
1375 | MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET); | |
1376 | MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET); | |
1377 | ||
ed878458 | 1378 | err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB, |
1da177e4 LT |
1379 | CMD_TIME_CLASS_B, status); |
1380 | ||
ed878458 | 1381 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1382 | return err; |
1383 | } | |
1384 | ||
1385 | int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status) | |
1386 | { | |
1387 | return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status); | |
1388 | } | |
1389 | ||
1390 | int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status) | |
1391 | { | |
ed878458 | 1392 | struct mthca_mailbox *mailbox; |
97f52eb4 | 1393 | __be64 *inbox; |
1da177e4 LT |
1394 | int err; |
1395 | ||
ed878458 RD |
1396 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1397 | if (IS_ERR(mailbox)) | |
1398 | return PTR_ERR(mailbox); | |
1399 | inbox = mailbox->buf; | |
1da177e4 LT |
1400 | |
1401 | inbox[0] = cpu_to_be64(virt); | |
1402 | inbox[1] = cpu_to_be64(dma_addr); | |
1403 | ||
ed878458 RD |
1404 | err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM, |
1405 | CMD_TIME_CLASS_B, status); | |
1da177e4 | 1406 | |
ed878458 | 1407 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1408 | |
1409 | if (!err) | |
6bd6228e RD |
1410 | mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n", |
1411 | (unsigned long long) dma_addr, (unsigned long long) virt); | |
1da177e4 LT |
1412 | |
1413 | return err; | |
1414 | } | |
1415 | ||
1416 | int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status) | |
1417 | { | |
1418 | mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n", | |
1419 | page_count, (unsigned long long) virt); | |
1420 | ||
1421 | return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status); | |
1422 | } | |
1423 | ||
1424 | int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status) | |
1425 | { | |
1426 | return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status); | |
1427 | } | |
1428 | ||
1429 | int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status) | |
1430 | { | |
1431 | return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status); | |
1432 | } | |
1433 | ||
1434 | int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages, | |
1435 | u8 *status) | |
1436 | { | |
1437 | int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE, | |
1438 | CMD_TIME_CLASS_A, status); | |
1439 | ||
1440 | if (ret || status) | |
1441 | return ret; | |
1442 | ||
1443 | /* | |
1444 | * Arbel page size is always 4 KB; round up number of system | |
1445 | * pages needed. | |
1446 | */ | |
1447 | *aux_pages = (*aux_pages + (1 << (PAGE_SHIFT - 12)) - 1) >> (PAGE_SHIFT - 12); | |
1448 | ||
1449 | return 0; | |
1450 | } | |
1451 | ||
ed878458 | 1452 | int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1453 | int mpt_index, u8 *status) |
1454 | { | |
ed878458 RD |
1455 | return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT, |
1456 | CMD_TIME_CLASS_B, status); | |
1da177e4 LT |
1457 | } |
1458 | ||
ed878458 | 1459 | int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1460 | int mpt_index, u8 *status) |
1461 | { | |
ed878458 RD |
1462 | return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, |
1463 | !mailbox, CMD_HW2SW_MPT, | |
1464 | CMD_TIME_CLASS_B, status); | |
1da177e4 LT |
1465 | } |
1466 | ||
ed878458 | 1467 | int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1468 | int num_mtt, u8 *status) |
1469 | { | |
ed878458 RD |
1470 | return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT, |
1471 | CMD_TIME_CLASS_B, status); | |
1da177e4 LT |
1472 | } |
1473 | ||
b8ca06f6 MT |
1474 | int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status) |
1475 | { | |
1476 | return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status); | |
1477 | } | |
1478 | ||
1da177e4 LT |
1479 | int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap, |
1480 | int eq_num, u8 *status) | |
1481 | { | |
1482 | mthca_dbg(dev, "%s mask %016llx for eqn %d\n", | |
1483 | unmap ? "Clearing" : "Setting", | |
1484 | (unsigned long long) event_mask, eq_num); | |
1485 | return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num, | |
1486 | 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status); | |
1487 | } | |
1488 | ||
ed878458 | 1489 | int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1490 | int eq_num, u8 *status) |
1491 | { | |
ed878458 RD |
1492 | return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ, |
1493 | CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1494 | } |
1495 | ||
ed878458 | 1496 | int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1497 | int eq_num, u8 *status) |
1498 | { | |
ed878458 RD |
1499 | return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0, |
1500 | CMD_HW2SW_EQ, | |
1501 | CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1502 | } |
1503 | ||
ed878458 | 1504 | int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1505 | int cq_num, u8 *status) |
1506 | { | |
ed878458 | 1507 | return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ, |
1da177e4 | 1508 | CMD_TIME_CLASS_A, status); |
1da177e4 LT |
1509 | } |
1510 | ||
ed878458 | 1511 | int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1512 | int cq_num, u8 *status) |
1513 | { | |
ed878458 RD |
1514 | return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0, |
1515 | CMD_HW2SW_CQ, | |
1516 | CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1517 | } |
1518 | ||
ec34a922 RD |
1519 | int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1520 | int srq_num, u8 *status) | |
1521 | { | |
1522 | return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ, | |
1523 | CMD_TIME_CLASS_A, status); | |
1524 | } | |
1525 | ||
1526 | int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, | |
1527 | int srq_num, u8 *status) | |
1528 | { | |
1529 | return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0, | |
1530 | CMD_HW2SW_SRQ, | |
1531 | CMD_TIME_CLASS_A, status); | |
1532 | } | |
1533 | ||
1534 | int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status) | |
1535 | { | |
1536 | return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ, | |
1537 | CMD_TIME_CLASS_B, status); | |
1538 | } | |
1539 | ||
1da177e4 | 1540 | int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num, |
ed878458 | 1541 | int is_ee, struct mthca_mailbox *mailbox, u32 optmask, |
1da177e4 LT |
1542 | u8 *status) |
1543 | { | |
1544 | static const u16 op[] = { | |
1545 | [MTHCA_TRANS_RST2INIT] = CMD_RST2INIT_QPEE, | |
1546 | [MTHCA_TRANS_INIT2INIT] = CMD_INIT2INIT_QPEE, | |
1547 | [MTHCA_TRANS_INIT2RTR] = CMD_INIT2RTR_QPEE, | |
1548 | [MTHCA_TRANS_RTR2RTS] = CMD_RTR2RTS_QPEE, | |
1549 | [MTHCA_TRANS_RTS2RTS] = CMD_RTS2RTS_QPEE, | |
1550 | [MTHCA_TRANS_SQERR2RTS] = CMD_SQERR2RTS_QPEE, | |
1551 | [MTHCA_TRANS_ANY2ERR] = CMD_2ERR_QPEE, | |
1552 | [MTHCA_TRANS_RTS2SQD] = CMD_RTS2SQD_QPEE, | |
1553 | [MTHCA_TRANS_SQD2SQD] = CMD_SQD2SQD_QPEE, | |
1554 | [MTHCA_TRANS_SQD2RTS] = CMD_SQD2RTS_QPEE, | |
1555 | [MTHCA_TRANS_ANY2RST] = CMD_ERR2RST_QPEE | |
1556 | }; | |
1557 | u8 op_mod = 0; | |
ed878458 | 1558 | int my_mailbox = 0; |
1da177e4 LT |
1559 | int err; |
1560 | ||
1561 | if (trans < 0 || trans >= ARRAY_SIZE(op)) | |
1562 | return -EINVAL; | |
1563 | ||
1564 | if (trans == MTHCA_TRANS_ANY2RST) { | |
1da177e4 LT |
1565 | op_mod = 3; /* don't write outbox, any->reset */ |
1566 | ||
1567 | /* For debugging */ | |
ed878458 RD |
1568 | if (!mailbox) { |
1569 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
1570 | if (!IS_ERR(mailbox)) { | |
1571 | my_mailbox = 1; | |
1572 | op_mod = 2; /* write outbox, any->reset */ | |
1573 | } else | |
1574 | mailbox = NULL; | |
1575 | } | |
1da177e4 | 1576 | } else { |
1da177e4 LT |
1577 | if (0) { |
1578 | int i; | |
1579 | mthca_dbg(dev, "Dumping QP context:\n"); | |
ed878458 | 1580 | printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf)); |
1da177e4 LT |
1581 | for (i = 0; i < 0x100 / 4; ++i) { |
1582 | if (i % 8 == 0) | |
1583 | printk(" [%02x] ", i * 4); | |
ed878458 | 1584 | printk(" %08x", |
97f52eb4 | 1585 | be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); |
1da177e4 LT |
1586 | if ((i + 1) % 8 == 0) |
1587 | printk("\n"); | |
1588 | } | |
1589 | } | |
1590 | } | |
1591 | ||
1592 | if (trans == MTHCA_TRANS_ANY2RST) { | |
ed878458 RD |
1593 | err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, |
1594 | (!!is_ee << 24) | num, op_mod, | |
1595 | op[trans], CMD_TIME_CLASS_C, status); | |
1da177e4 | 1596 | |
ed878458 | 1597 | if (0 && mailbox) { |
1da177e4 LT |
1598 | int i; |
1599 | mthca_dbg(dev, "Dumping QP context:\n"); | |
ed878458 | 1600 | printk(" %08x\n", be32_to_cpup(mailbox->buf)); |
1da177e4 LT |
1601 | for (i = 0; i < 0x100 / 4; ++i) { |
1602 | if (i % 8 == 0) | |
1603 | printk("[%02x] ", i * 4); | |
ed878458 | 1604 | printk(" %08x", |
97f52eb4 | 1605 | be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); |
1da177e4 LT |
1606 | if ((i + 1) % 8 == 0) |
1607 | printk("\n"); | |
1608 | } | |
1609 | } | |
1610 | ||
1611 | } else | |
ed878458 | 1612 | err = mthca_cmd(dev, mailbox->dma, (!!is_ee << 24) | num, |
1da177e4 LT |
1613 | op_mod, op[trans], CMD_TIME_CLASS_C, status); |
1614 | ||
ed878458 RD |
1615 | if (my_mailbox) |
1616 | mthca_free_mailbox(dev, mailbox); | |
1617 | ||
1da177e4 LT |
1618 | return err; |
1619 | } | |
1620 | ||
1621 | int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee, | |
ed878458 | 1622 | struct mthca_mailbox *mailbox, u8 *status) |
1da177e4 | 1623 | { |
ed878458 RD |
1624 | return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0, |
1625 | CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1626 | } |
1627 | ||
1628 | int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn, | |
1629 | u8 *status) | |
1630 | { | |
1631 | u8 op_mod; | |
1632 | ||
1633 | switch (type) { | |
1634 | case IB_QPT_SMI: | |
1635 | op_mod = 0; | |
1636 | break; | |
1637 | case IB_QPT_GSI: | |
1638 | op_mod = 1; | |
1639 | break; | |
1640 | case IB_QPT_RAW_IPV6: | |
1641 | op_mod = 2; | |
1642 | break; | |
1643 | case IB_QPT_RAW_ETY: | |
1644 | op_mod = 3; | |
1645 | break; | |
1646 | default: | |
1647 | return -EINVAL; | |
1648 | } | |
1649 | ||
1650 | return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP, | |
1651 | CMD_TIME_CLASS_B, status); | |
1652 | } | |
1653 | ||
1654 | int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey, | |
ed878458 | 1655 | int port, struct ib_wc *in_wc, struct ib_grh *in_grh, |
1da177e4 LT |
1656 | void *in_mad, void *response_mad, u8 *status) |
1657 | { | |
ed878458 RD |
1658 | struct mthca_mailbox *inmailbox, *outmailbox; |
1659 | void *inbox; | |
1da177e4 LT |
1660 | int err; |
1661 | u32 in_modifier = port; | |
1662 | u8 op_modifier = 0; | |
1663 | ||
1664 | #define MAD_IFC_BOX_SIZE 0x400 | |
1665 | #define MAD_IFC_MY_QPN_OFFSET 0x100 | |
1666 | #define MAD_IFC_RQPN_OFFSET 0x104 | |
1667 | #define MAD_IFC_SL_OFFSET 0x108 | |
1668 | #define MAD_IFC_G_PATH_OFFSET 0x109 | |
1669 | #define MAD_IFC_RLID_OFFSET 0x10a | |
1670 | #define MAD_IFC_PKEY_OFFSET 0x10e | |
1671 | #define MAD_IFC_GRH_OFFSET 0x140 | |
1672 | ||
ed878458 RD |
1673 | inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1674 | if (IS_ERR(inmailbox)) | |
1675 | return PTR_ERR(inmailbox); | |
1676 | inbox = inmailbox->buf; | |
1677 | ||
1678 | outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
1679 | if (IS_ERR(outmailbox)) { | |
1680 | mthca_free_mailbox(dev, inmailbox); | |
1681 | return PTR_ERR(outmailbox); | |
1682 | } | |
1da177e4 | 1683 | |
ed878458 | 1684 | memcpy(inbox, in_mad, 256); |
1da177e4 LT |
1685 | |
1686 | /* | |
1687 | * Key check traps can't be generated unless we have in_wc to | |
1688 | * tell us where to send the trap. | |
1689 | */ | |
1690 | if (ignore_mkey || !in_wc) | |
1691 | op_modifier |= 0x1; | |
1692 | if (ignore_bkey || !in_wc) | |
1693 | op_modifier |= 0x2; | |
1694 | ||
1695 | if (in_wc) { | |
1696 | u8 val; | |
1697 | ||
ed878458 | 1698 | memset(inbox + 256, 0, 256); |
1da177e4 | 1699 | |
ed878458 RD |
1700 | MTHCA_PUT(inbox, in_wc->qp_num, MAD_IFC_MY_QPN_OFFSET); |
1701 | MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET); | |
1da177e4 LT |
1702 | |
1703 | val = in_wc->sl << 4; | |
ed878458 | 1704 | MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET); |
1da177e4 LT |
1705 | |
1706 | val = in_wc->dlid_path_bits | | |
1707 | (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); | |
ed878458 | 1708 | MTHCA_PUT(inbox, val, MAD_IFC_GRH_OFFSET); |
1da177e4 | 1709 | |
ed878458 RD |
1710 | MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET); |
1711 | MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET); | |
1da177e4 LT |
1712 | |
1713 | if (in_grh) | |
ed878458 | 1714 | memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40); |
1da177e4 LT |
1715 | |
1716 | op_modifier |= 0x10; | |
1717 | ||
1718 | in_modifier |= in_wc->slid << 16; | |
1719 | } | |
1720 | ||
ed878458 RD |
1721 | err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma, |
1722 | in_modifier, op_modifier, | |
1da177e4 LT |
1723 | CMD_MAD_IFC, CMD_TIME_CLASS_C, status); |
1724 | ||
1725 | if (!err && !*status) | |
ed878458 | 1726 | memcpy(response_mad, outmailbox->buf, 256); |
1da177e4 | 1727 | |
ed878458 RD |
1728 | mthca_free_mailbox(dev, inmailbox); |
1729 | mthca_free_mailbox(dev, outmailbox); | |
1da177e4 LT |
1730 | return err; |
1731 | } | |
1732 | ||
ed878458 RD |
1733 | int mthca_READ_MGM(struct mthca_dev *dev, int index, |
1734 | struct mthca_mailbox *mailbox, u8 *status) | |
1da177e4 | 1735 | { |
ed878458 RD |
1736 | return mthca_cmd_box(dev, 0, mailbox->dma, index, 0, |
1737 | CMD_READ_MGM, CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1738 | } |
1739 | ||
ed878458 RD |
1740 | int mthca_WRITE_MGM(struct mthca_dev *dev, int index, |
1741 | struct mthca_mailbox *mailbox, u8 *status) | |
1da177e4 | 1742 | { |
ed878458 RD |
1743 | return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM, |
1744 | CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1745 | } |
1746 | ||
ed878458 RD |
1747 | int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1748 | u16 *hash, u8 *status) | |
1da177e4 | 1749 | { |
1da177e4 LT |
1750 | u64 imm; |
1751 | int err; | |
1752 | ||
ed878458 | 1753 | err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH, |
1da177e4 | 1754 | CMD_TIME_CLASS_A, status); |
1da177e4 | 1755 | |
ed878458 | 1756 | *hash = imm; |
1da177e4 LT |
1757 | return err; |
1758 | } | |
1759 | ||
1760 | int mthca_NOP(struct mthca_dev *dev, u8 *status) | |
1761 | { | |
1762 | return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status); | |
1763 | } |