ARCv2: mm: Merge 2 updates to DC_CTRL for region flush
authorVineet Gupta <vgupta@synopsys.com>
Tue, 2 May 2017 22:28:12 +0000 (15:28 -0700)
committerVineet Gupta <vgupta@synopsys.com>
Tue, 2 May 2017 23:16:07 +0000 (16:16 -0700)
commitee40bd1e0c3fb83d810f258952692ffdebc14726
tree1aabc93d6ac3559e9940125e21cdcc445dbf180b
parent0d77117fc5c0333d024a183d6790167bb90c3b62
ARCv2: mm: Merge 2 updates to DC_CTRL for region flush

Region Flush has a weird programming model.

 1. Flush or Invalidate is selected by DC_CTRL.RGN_OP
 2 Flush-n-Invalidate is done by DC_CTRL.IM

Given the code structuring before, case #2 above was generating two
seperate updates to DC_CTRL which was pointless.

80a342b0 <__dma_cache_wback_inv_l1>:
80a342b0: clri r4
80a342b4: lr r2,[dc_ctrl]
80a342b8: bset_s r2,r2,0x6
80a342ba: sr r2,[dc_ctrl] <-- FIRST
|
80a342be: bmskn r3,r0,0x5
|
80a342c2: lr r2,[dc_ctrl]
80a342c6: and r2,r2,0xfffff1ff
80a342ce: bset_s r2,r2,0x9
80a342d0: sr r2,[dc_ctrl] <-- SECOND
|
80a342d4: add_s r1,r1,0x3f
80a342d6: bmsk_s r0,r0,0x5
80a342d8: add_s r0,r0,r1
80a342da: add_s r0,r0,r3
80a342dc: sr r0,[78]
80a342e0: sr r3,[77]
|...
|...

So move setting of DC_CTRL.RGN_OP into __before_dc_op() and combine with
any other update.

80b63324 <__dma_cache_wback_inv_l1>:
80b63324: clri r3
80b63328: lr r2,[dc_ctrl]
80b6332c: and r2,r2,0xfffff1ff
80b63334: or r2,r2,576
80b63338: sr r2,[dc_ctrl]
|
80b6333c: add_s r1,r1,0x3f
80b6333e: bmskn r2,r0,0x5
80b63342: add_s r0,r0,r1
80b63344: sr r0,[78]
80b63348: sr r2,[77]

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/mm/cache.c