clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value
authorTakeshi Kihara <takeshi.kihara.df@renesas.com>
Mon, 25 Feb 2019 02:48:38 +0000 (11:48 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 4 Apr 2019 09:54:46 +0000 (11:54 +0200)
commitb953eaaeb58efc944f51cffd3f6838657958f0f8
tree2a5d1da5a5c6f0cdc1edc95d7e562da9a3774e41
parent21ab095cbc069a351fa9cef919f2dafc43a8fde7
clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value

cpg_sd_clock_round_rate() may return an unsupported clock rate for the
requested clock rate. Therefore, when cpg_sd_clock_set_rate() sets the
clock rate acquired by cpg_sd_clock_round_rate(), an error may occur.

This is not conform the clk API design.

This patch fixes that by making sure cpg_sd_clock_calc_div() considers
only the division values defined in cpg_sd_div_table[].
With this fix, the cpg_sd_clock_round_rate() always return a support
clock rate.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 90c073e53909da85 ("clk: shmobile: r8a7795: Add SD divider support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
drivers/clk/renesas/rcar-gen3-cpg.c