KVM: MIPS/T&E: Report correct dcache line size
authorJames Hogan <james.hogan@imgtec.com>
Tue, 14 Mar 2017 10:25:47 +0000 (10:25 +0000)
committerJames Hogan <james.hogan@imgtec.com>
Tue, 28 Mar 2017 14:36:18 +0000 (15:36 +0100)
commit867f4da75277aaef10daa4e0e9ad6f905fa33fb1
tree8c7c12c8cb1536a9876d995fd96198e0ccb94e5e
parent1c506c9c104cf01d01a9633ad2e76f15f938c54c
KVM: MIPS/T&E: Report correct dcache line size

Octeon CPUs don't report the correct dcache line size in CP0_Config1.DL,
so encode the correct value for the guest CP0_Config1.DL based on
cpu_dcache_line_size().

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
arch/mips/kvm/trap_emul.c