LoongArch: Make WriteCombine configurable for ioremap()
authorHuacai Chen <chenhuacai@loongson.cn>
Tue, 18 Apr 2023 11:38:58 +0000 (19:38 +0800)
committerHuacai Chen <chenhuacai@loongson.cn>
Tue, 18 Apr 2023 11:38:58 +0000 (19:38 +0800)
commit16c52e503043aed1e2a2ce38d9249de5936c1f6b
tree7552a1e276d52b2cff4da4e8c7a0be030d4ce77a
parent6a8f57ae2eb07ab39a6f0ccad60c760743051026
LoongArch: Make WriteCombine configurable for ioremap()

LoongArch maintains cache coherency in hardware, but when paired with
LS7A chipsets the WUC attribute (Weak-ordered UnCached, which is similar
to WriteCombine) is out of the scope of cache coherency machanism for
PCIe devices (this is a PCIe protocol violation, which may be fixed in
newer chipsets).

This means WUC can only used for write-only memory regions now, so this
option is disabled by default, making WUC silently fallback to SUC for
ioremap(). You can enable this option if the kernel is ensured to run on
hardware without this bug.

Kernel parameter writecombine=on/off can be used to override the Kconfig
option.

Cc: stable@vger.kernel.org
Suggested-by: WANG Xuerui <kernel@xen0n.name>
Reviewed-by: WANG Xuerui <kernel@xen0n.name>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Documentation/admin-guide/kernel-parameters.rst
Documentation/admin-guide/kernel-parameters.txt
arch/loongarch/Kconfig
arch/loongarch/include/asm/io.h
arch/loongarch/kernel/setup.c