ARC: [plat-axs103] refactor the DT fudging code
authorVineet Gupta <vgupta@synopsys.com>
Tue, 22 Aug 2017 21:37:22 +0000 (14:37 -0700)
committerVineet Gupta <vgupta@synopsys.com>
Fri, 1 Sep 2017 18:26:26 +0000 (11:26 -0700)
commit0fa400cb8a90753044bbcb5810fa1a59d96d5ea1
tree76080e940d4b0fdde189ea918e80295a10f6e8c5
parentf6a09bace0bb9587985b48ed652f2b292f8de0de
ARC: [plat-axs103] refactor the DT fudging code

with clk frequency setting code gone by prev commits, we can elide the
unconditonal DT parsing to the specific case of quad core config where
we possibly need to fudge the DT value.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/plat-axs10x/axs10x.c