Merge branch 'x86/urgent' into core/efi, to pick up a pending EFI fix

[linux-2.6-block.git] / arch / arm64 / mm / proc.S

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 160a1b5ab9c6017d7cd8cf2b61ed0e0da465b893..7783ff05f74cc262c643b1a96932a717e47445c5 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -34,11 +34,7 @@
 #define TCR_TG_FLAGS   TCR_TG0_4K | TCR_TG1_4K
 #endif
 
-#ifdef CONFIG_SMP
 #define TCR_SMP_FLAGS  TCR_SHARED
-#else
-#define TCR_SMP_FLAGS  0
-#endif
 
 /* PTWs cacheable, inner/outer WBWA */
 #define TCR_CACHE_FLAGS        TCR_IRGN_WBWA | TCR_ORGN_WBWA
@@ -150,13 +146,13 @@ ENDPROC(cpu_do_switch_mm)
  *     value of the SCTLR_EL1 register.
  */
 ENTRY(__cpu_setup)
-       ic      iallu                           // I+BTB cache invalidate
        tlbi    vmalle1is                       // invalidate I + D TLBs
        dsb     ish
 
        mov     x0, #3 << 20
        msr     cpacr_el1, x0                   // Enable FP/ASIMD
-       msr     mdscr_el1, xzr                  // Reset mdscr_el1
+       mov     x0, #1 << 12                    // Reset mdscr_el1 and disable
+       msr     mdscr_el1, x0                   // access to the DCC from EL0
        /*
         * Memory region attributes for LPAE:
         *
@@ -198,6 +194,19 @@ ENTRY(__cpu_setup)
         */
        mrs     x9, ID_AA64MMFR0_EL1
        bfi     x10, x9, #32, #3
+#ifdef CONFIG_ARM64_HW_AFDBM
+       /*
+        * Hardware update of the Access and Dirty bits.
+        */
+       mrs     x9, ID_AA64MMFR1_EL1
+       and     x9, x9, #0xf
+       cbz     x9, 2f
+       cmp     x9, #2
+       b.lt    1f
+       orr     x10, x10, #TCR_HD               // hardware Dirty flag update
+1:     orr     x10, x10, #TCR_HA               // hardware Access flag update
+2:
+#endif /* CONFIG_ARM64_HW_AFDBM */
        msr     tcr_el1, x10
        ret                                     // return to head.S
 ENDPROC(__cpu_setup)