arm64: dts: Fix broken architected timer interrupt trigger
[linux-2.6-block.git] / arch / arm64 / boot / dts / amlogic / meson-gxbb.dtsi
index 063e3b679207390d1affe9aacb277c3598481b94..bf6c8d0510028b472efc4e7a34033e8ca0d8f7c8 100644 (file)
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <GIC_PPI 13
-                       (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+                       (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 14
-                       (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+                       (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 11
-                       (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+                       (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 10
-                       (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
+                       (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
        };
 
        xtal: xtal-clk {
                        #size-cells = <2>;
                        ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
 
+                       rng {
+                               compatible = "amlogic,meson-rng";
+                               reg = <0x0 0x0 0x0 0x4>;
+                       };
+
                        pinctrl_periphs: pinctrl@4b0 {
                                compatible = "amlogic,meson-gxbb-periphs-pinctrl";
                                #address-cells = <2>;
                        #address-cells = <2>;
                        #size-cells = <2>;
                        ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
+
+                       clkc: clock-controller@0 {
+                               compatible = "amlogic,gxbb-clkc";
+                               #clock-cells = <1>;
+                               reg = <0x0 0x0 0x0 0x3db>;
+                       };
                };
 
                apb: apb@d0000000 {