[linux-2.6-block.git] / virt / kvm / arm / vgic / vgic-mmio-v3.c

/*
 * VGICv3 MMIO handling functions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/irqchip/arm-gic-v3.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <kvm/iodev.h>
#include <kvm/arm_vgic.h>

#include <asm/kvm_emulate.h>

#include "vgic.h"
#include "vgic-mmio.h"

/* extract @num bytes at @offset bytes offset in data */
static unsigned long extract_bytes(unsigned long data, unsigned int offset,
				   unsigned int num)
{
	return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
}

static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
					    gpa_t addr, unsigned int len)
{
	u32 value = 0;

	switch (addr & 0x0c) {
	case GICD_CTLR:
		if (vcpu->kvm->arch.vgic.enabled)
			value |= GICD_CTLR_ENABLE_SS_G1;
		value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
		break;
	case GICD_TYPER:
		value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
		value = (value >> 5) - 1;
		value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
		break;
	case GICD_IIDR:
		value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
		break;
	default:
		return 0;
	}

	return value;
}

static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
				    gpa_t addr, unsigned int len,
				    unsigned long val)
{
	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	bool was_enabled = dist->enabled;

	switch (addr & 0x0c) {
	case GICD_CTLR:
		dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;

		if (!was_enabled && dist->enabled)
			vgic_kick_vcpus(vcpu->kvm);
		break;
	case GICD_TYPER:
	case GICD_IIDR:
		return;
	}
}

static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
					      gpa_t addr, unsigned int len)
{
	unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
	int target_vcpu_id = vcpu->vcpu_id;
	u64 value;

	value = (mpidr & GENMASK(23, 0)) << 32;
	value |= ((target_vcpu_id & 0xffff) << 8);
	if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
		value |= GICR_TYPER_LAST;

	return extract_bytes(value, addr & 7, len);
}

static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
					     gpa_t addr, unsigned int len)
{
	return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
}

static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
					      gpa_t addr, unsigned int len)
{
	switch (addr & 0xffff) {
	case GICD_PIDR2:
		/* report a GICv3 compliant implementation */
		return 0x3b;
	}

	return 0;
}

/*
 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
 * redistributors, while SPIs are covered by registers in the distributor
 * block. Trying to set private IRQs in this block gets ignored.
 * We take some special care here to fix the calculation of the register
 * offset.
 */
#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc)	\
	{								\
		.reg_offset = off,					\
		.bits_per_irq = bpi,					\
		.len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,		\
		.access_flags = acc,					\
		.read = vgic_mmio_read_raz,				\
		.write = vgic_mmio_write_wi,				\
	}, {								\
		.reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,	\
		.bits_per_irq = bpi,					\
		.len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,	\
		.access_flags = acc,					\
		.read = rd,						\
		.write = wr,						\
	}

static const struct vgic_register_region vgic_v3_dist_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
		vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
		vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
		vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
		vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
		vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
		vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
		vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
		vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
		vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
		vgic_mmio_read_config, vgic_mmio_write_config, 2,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
		vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
		VGIC_ACCESS_32bit),
};

static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
		vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
		vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
		vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
		VGIC_ACCESS_32bit),
};

static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
		vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
		vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
		vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
		vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
		vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
		vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
		vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
		vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
		vgic_mmio_read_config, vgic_mmio_write_config, 8,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
};

unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
{
	dev->regions = vgic_v3_dist_registers;
	dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);

	kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);

	return SZ_64K;
}

int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
{
	int nr_vcpus = atomic_read(&kvm->online_vcpus);
	struct kvm_vcpu *vcpu;
	struct vgic_io_device *devices;
	int c, ret = 0;

	devices = kmalloc(sizeof(struct vgic_io_device) * nr_vcpus * 2,
			  GFP_KERNEL);
	if (!devices)
		return -ENOMEM;

	kvm_for_each_vcpu(c, vcpu, kvm) {
		gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
		gpa_t sgi_base = rd_base + SZ_64K;
		struct vgic_io_device *rd_dev = &devices[c * 2];
		struct vgic_io_device *sgi_dev = &devices[c * 2 + 1];

		kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
		rd_dev->base_addr = rd_base;
		rd_dev->regions = vgic_v3_rdbase_registers;
		rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
		rd_dev->redist_vcpu = vcpu;

		mutex_lock(&kvm->slots_lock);
		ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
					      SZ_64K, &rd_dev->dev);
		mutex_unlock(&kvm->slots_lock);

		if (ret)
			break;

		kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
		sgi_dev->base_addr = sgi_base;
		sgi_dev->regions = vgic_v3_sgibase_registers;
		sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
		sgi_dev->redist_vcpu = vcpu;

		mutex_lock(&kvm->slots_lock);
		ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
					      SZ_64K, &sgi_dev->dev);
		mutex_unlock(&kvm->slots_lock);
		if (ret) {
			kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
						  &rd_dev->dev);
			break;
		}
	}

	if (ret) {
		/* The current c failed, so we start with the previous one. */
		for (c--; c >= 0; c--) {
			kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
						  &devices[c * 2].dev);
			kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
						  &devices[c * 2 + 1].dev);
		}
		kfree(devices);
	} else {
		kvm->arch.vgic.redist_iodevs = devices;
	}

	return ret;
}
Commit	Line	Data
ed9b8cef AP	1	/*
	2	* VGICv3 MMIO handling functions
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/irqchip/arm-gic-v3.h>
	15	#include <linux/kvm.h>
	16	#include <linux/kvm_host.h>
	17	#include <kvm/iodev.h>
	18	#include <kvm/arm_vgic.h>
	19
	20	#include <asm/kvm_emulate.h>
	21
	22	#include "vgic.h"
	23	#include "vgic-mmio.h"
	24
741972d8 AP	25	/* extract @num bytes at @offset bytes offset in data */
	26	static unsigned long extract_bytes(unsigned long data, unsigned int offset,
	27	unsigned int num)
	28	{
	29	return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
	30	}
	31
fd59ed3b AP	32	static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
	33	gpa_t addr, unsigned int len)
	34	{
	35	u32 value = 0;
	36
	37	switch (addr & 0x0c) {
	38	case GICD_CTLR:
	39	if (vcpu->kvm->arch.vgic.enabled)
	40	value \|= GICD_CTLR_ENABLE_SS_G1;
	41	value \|= GICD_CTLR_ARE_NS \| GICD_CTLR_DS;
	42	break;
	43	case GICD_TYPER:
	44	value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
	45	value = (value >> 5) - 1;
	46	value \|= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
	47	break;
	48	case GICD_IIDR:
	49	value = (PRODUCT_ID_KVM << 24) \| (IMPLEMENTER_ARM << 0);
	50	break;
	51	default:
	52	return 0;
	53	}
	54
	55	return value;
	56	}
	57
	58	static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
	59	gpa_t addr, unsigned int len,
	60	unsigned long val)
	61	{
	62	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	63	bool was_enabled = dist->enabled;
	64
	65	switch (addr & 0x0c) {
	66	case GICD_CTLR:
	67	dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
	68
	69	if (!was_enabled && dist->enabled)
	70	vgic_kick_vcpus(vcpu->kvm);
	71	break;
	72	case GICD_TYPER:
	73	case GICD_IIDR:
	74	return;
	75	}
	76	}
	77
741972d8 AP	78	static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
	79	gpa_t addr, unsigned int len)
	80	{
	81	unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
	82	int target_vcpu_id = vcpu->vcpu_id;
	83	u64 value;
	84
	85	value = (mpidr & GENMASK(23, 0)) << 32;
	86	value \|= ((target_vcpu_id & 0xffff) << 8);
	87	if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
	88	value \|= GICR_TYPER_LAST;
	89
	90	return extract_bytes(value, addr & 7, len);
	91	}
	92
	93	static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
	94	gpa_t addr, unsigned int len)
	95	{
	96	return (PRODUCT_ID_KVM << 24) \| (IMPLEMENTER_ARM << 0);
	97	}
	98
54f59d2b AP	99	static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
	100	gpa_t addr, unsigned int len)
	101	{
	102	switch (addr & 0xffff) {
	103	case GICD_PIDR2:
	104	/* report a GICv3 compliant implementation */
	105	return 0x3b;
	106	}
	107
	108	return 0;
	109	}
	110
ed9b8cef AP	111	/*
	112	* The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
	113	* redistributors, while SPIs are covered by registers in the distributor
	114	* block. Trying to set private IRQs in this block gets ignored.
	115	* We take some special care here to fix the calculation of the register
	116	* offset.
	117	*/
	118	#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \
	119	{ \
	120	.reg_offset = off, \
	121	.bits_per_irq = bpi, \
	122	.len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
	123	.access_flags = acc, \
	124	.read = vgic_mmio_read_raz, \
	125	.write = vgic_mmio_write_wi, \
	126	}, { \
	127	.reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
	128	.bits_per_irq = bpi, \
	129	.len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
	130	.access_flags = acc, \
	131	.read = rd, \
	132	.write = wr, \
	133	}
	134
	135	static const struct vgic_register_region vgic_v3_dist_registers[] = {
	136	REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
fd59ed3b	137	vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
ed9b8cef AP	138	VGIC_ACCESS_32bit),
	139	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
	140	vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
	141	VGIC_ACCESS_32bit),
	142	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
	143	vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
	144	VGIC_ACCESS_32bit),
	145	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
	146	vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
	147	VGIC_ACCESS_32bit),
	148	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
	149	vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
	150	VGIC_ACCESS_32bit),
	151	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
	152	vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
	153	VGIC_ACCESS_32bit),
	154	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
	155	vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
	156	VGIC_ACCESS_32bit),
	157	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
	158	vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
	159	VGIC_ACCESS_32bit),
	160	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
	161	vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
	162	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
	163	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
	164	vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
	165	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
	166	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
	167	vgic_mmio_read_config, vgic_mmio_write_config, 2,
	168	VGIC_ACCESS_32bit),
	169	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
	170	vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
	171	VGIC_ACCESS_32bit),
	172	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
	173	vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
	174	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
	175	REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
54f59d2b	176	vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
ed9b8cef AP	177	VGIC_ACCESS_32bit),
	178	};
	179
	180	static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
	181	REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
	182	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
	183	VGIC_ACCESS_32bit),
	184	REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
741972d8	185	vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
ed9b8cef AP	186	VGIC_ACCESS_32bit),
ed9b8cef AP	187	REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
741972d8	188	vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
ed9b8cef AP	189	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
	190	REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
	191	vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
	192	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
	193	REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
	194	vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
	195	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
	196	REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
54f59d2b	197	vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
ed9b8cef AP	198	VGIC_ACCESS_32bit),
	199	};
	200
	201	static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
	202	REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
	203	vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
	204	VGIC_ACCESS_32bit),
	205	REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
	206	vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
	207	VGIC_ACCESS_32bit),
	208	REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
	209	vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
	210	VGIC_ACCESS_32bit),
	211	REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
	212	vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
	213	VGIC_ACCESS_32bit),
	214	REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
	215	vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
	216	VGIC_ACCESS_32bit),
	217	REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
	218	vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
	219	VGIC_ACCESS_32bit),
	220	REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
	221	vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
	222	VGIC_ACCESS_32bit),
	223	REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
	224	vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
	225	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
	226	REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
	227	vgic_mmio_read_config, vgic_mmio_write_config, 8,
	228	VGIC_ACCESS_32bit),
	229	REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
	230	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
	231	VGIC_ACCESS_32bit),
	232	REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
	233	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
	234	VGIC_ACCESS_32bit),
	235	};
	236
	237	unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
	238	{
	239	dev->regions = vgic_v3_dist_registers;
	240	dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
	241
	242	kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
	243
	244	return SZ_64K;
	245	}
	246
	247	int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
	248	{
	249	int nr_vcpus = atomic_read(&kvm->online_vcpus);
	250	struct kvm_vcpu *vcpu;
	251	struct vgic_io_device *devices;
	252	int c, ret = 0;
	253
	254	devices = kmalloc(sizeof(struct vgic_io_device) * nr_vcpus * 2,
	255	GFP_KERNEL);
	256	if (!devices)
	257	return -ENOMEM;
	258
	259	kvm_for_each_vcpu(c, vcpu, kvm) {
	260	gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
	261	gpa_t sgi_base = rd_base + SZ_64K;
262	struct vgic_io_device rd_dev = &devices[c 2];
263	struct vgic_io_device sgi_dev = &devices[c 2 + 1];
264
265	kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
266	rd_dev->base_addr = rd_base;
267	rd_dev->regions = vgic_v3_rdbase_registers;
268	rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
269	rd_dev->redist_vcpu = vcpu;
270
271	mutex_lock(&kvm->slots_lock);
272	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
273	SZ_64K, &rd_dev->dev);
274	mutex_unlock(&kvm->slots_lock);
275
276	if (ret)
277	break;
278
279	kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
280	sgi_dev->base_addr = sgi_base;
281	sgi_dev->regions = vgic_v3_sgibase_registers;
282	sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
283	sgi_dev->redist_vcpu = vcpu;
284
285	mutex_lock(&kvm->slots_lock);
286	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
287	SZ_64K, &sgi_dev->dev);
288	mutex_unlock(&kvm->slots_lock);
289	if (ret) {
290	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
291	&rd_dev->dev);
292	break;
293	}
294	}
295
296	if (ret) {
297	/* The current c failed, so we start with the previous one. */
298	for (c--; c >= 0; c--) {
299	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
300	&devices[c * 2].dev);
301	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
302	&devices[c * 2 + 1].dev);
303	}
304	kfree(devices);
305	} else {
306	kvm->arch.vgic.redist_iodevs = devices;
307	}
308
309	return ret;
310	}