[linux-2.6-block.git] / sound / soc / samsung / s3c24xx-i2s.c

/*
 * s3c24xx-i2s.c  --  ALSA Soc Audio Layer
 *
 * (c) 2006 Wolfson Microelectronics PLC.
 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
 *
 * Copyright 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/module.h>

#include <sound/soc.h>
#include <sound/pcm_params.h>

#include <mach/dma.h>
#include <mach/gpio-samsung.h>
#include <plat/gpio-cfg.h>
#include "regs-iis.h"

#include "dma.h"
#include "s3c24xx-i2s.h"

static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = {
	.channel	= DMACH_I2S_OUT,
	.ch_name	= "tx",
	.dma_size	= 2,
};

static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = {
	.channel	= DMACH_I2S_IN,
	.ch_name	= "rx",
	.dma_size	= 2,
};

struct s3c24xx_i2s_info {
	void __iomem	*regs;
	struct clk	*iis_clk;
	u32		iiscon;
	u32		iismod;
	u32		iisfcon;
	u32		iispsr;
};
static struct s3c24xx_i2s_info s3c24xx_i2s;

static void s3c24xx_snd_txctrl(int on)
{
	u32 iisfcon;
	u32 iiscon;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);

	if (on) {
		iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
		iiscon  |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
		iiscon  &= ~S3C2410_IISCON_TXIDLE;
		iismod  |= S3C2410_IISMOD_TXMODE;

		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
	} else {
		/* note, we have to disable the FIFOs otherwise bad things
		 * seem to happen when the DMA stops. According to the
		 * Samsung supplied kernel, this should allow the DMA
		 * engine and FIFOs to reset. If this isn't allowed, the
		 * DMA engine will simply freeze randomly.
		 */

		iisfcon &= ~S3C2410_IISFCON_TXENABLE;
		iisfcon &= ~S3C2410_IISFCON_TXDMA;
		iiscon  |=  S3C2410_IISCON_TXIDLE;
		iiscon  &= ~S3C2410_IISCON_TXDMAEN;
		iismod  &= ~S3C2410_IISMOD_TXMODE;

		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
	}

	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
}

static void s3c24xx_snd_rxctrl(int on)
{
	u32 iisfcon;
	u32 iiscon;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);

	if (on) {
		iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
		iiscon  |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
		iiscon  &= ~S3C2410_IISCON_RXIDLE;
		iismod  |= S3C2410_IISMOD_RXMODE;

		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
	} else {
		/* note, we have to disable the FIFOs otherwise bad things
		 * seem to happen when the DMA stops. According to the
		 * Samsung supplied kernel, this should allow the DMA
		 * engine and FIFOs to reset. If this isn't allowed, the
		 * DMA engine will simply freeze randomly.
		 */

		iisfcon &= ~S3C2410_IISFCON_RXENABLE;
		iisfcon &= ~S3C2410_IISFCON_RXDMA;
		iiscon  |= S3C2410_IISCON_RXIDLE;
		iiscon  &= ~S3C2410_IISCON_RXDMAEN;
		iismod  &= ~S3C2410_IISMOD_RXMODE;

		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
	}

	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
}

/*
 * Wait for the LR signal to allow synchronisation to the L/R clock
 * from the codec. May only be needed for slave mode.
 */
static int s3c24xx_snd_lrsync(void)
{
	u32 iiscon;
	int timeout = 50; /* 5ms */

	pr_debug("Entered %s\n", __func__);

	while (1) {
		iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
		if (iiscon & S3C2410_IISCON_LRINDEX)
			break;

		if (!timeout--)
			return -ETIMEDOUT;
		udelay(100);
	}

	return 0;
}

/*
 * Check whether CPU is the master or slave
 */
static inline int s3c24xx_snd_is_clkmaster(void)
{
	pr_debug("Entered %s\n", __func__);

	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
}

/*
 * Set S3C24xx I2S DAI format
 */
static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
		unsigned int fmt)
{
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params r: IISMOD: %x \n", iismod);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		iismod |= S3C2410_IISMOD_SLAVE;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		iismod &= ~S3C2410_IISMOD_SLAVE;
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_LEFT_J:
		iismod |= S3C2410_IISMOD_MSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		iismod &= ~S3C2410_IISMOD_MSB;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params w: IISMOD: %x \n", iismod);
	return 0;
}

static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct snd_dmaengine_dai_dma_data *dma_data;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	dma_data = snd_soc_dai_get_dma_data(dai, substream);

	/* Working copies of register */
	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params r: IISMOD: %x\n", iismod);

	switch (params_width(params)) {
	case 8:
		iismod &= ~S3C2410_IISMOD_16BIT;
		dma_data->addr_width = 1;
		break;
	case 16:
		iismod |= S3C2410_IISMOD_16BIT;
		dma_data->addr_width = 2;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params w: IISMOD: %x\n", iismod);
	return 0;
}

static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	int ret = 0;

	pr_debug("Entered %s\n", __func__);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!s3c24xx_snd_is_clkmaster()) {
			ret = s3c24xx_snd_lrsync();
			if (ret)
				goto exit_err;
		}

		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c24xx_snd_rxctrl(1);
		else
			s3c24xx_snd_txctrl(1);

		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c24xx_snd_rxctrl(0);
		else
			s3c24xx_snd_txctrl(0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

exit_err:
	return ret;
}

/*
 * Set S3C24xx Clock source
 */
static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
	int clk_id, unsigned int freq, int dir)
{
	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("Entered %s\n", __func__);

	iismod &= ~S3C2440_IISMOD_MPLL;

	switch (clk_id) {
	case S3C24XX_CLKSRC_PCLK:
		break;
	case S3C24XX_CLKSRC_MPLL:
		iismod |= S3C2440_IISMOD_MPLL;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	return 0;
}

/*
 * Set S3C24xx Clock dividers
 */
static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
	int div_id, int div)
{
	u32 reg;

	pr_debug("Entered %s\n", __func__);

	switch (div_id) {
	case S3C24XX_DIV_BCLK:
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
		break;
	case S3C24XX_DIV_MCLK:
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
		break;
	case S3C24XX_DIV_PRESCALER:
		writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

/*
 * To avoid duplicating clock code, allow machine driver to
 * get the clockrate from here.
 */
u32 s3c24xx_i2s_get_clockrate(void)
{
	return clk_get_rate(s3c24xx_i2s.iis_clk);
}
EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);

static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
{
	pr_debug("Entered %s\n", __func__);

	samsung_asoc_init_dma_data(dai, &s3c24xx_i2s_pcm_stereo_out,
		&s3c24xx_i2s_pcm_stereo_in);

	s3c24xx_i2s.iis_clk = devm_clk_get(dai->dev, "iis");
	if (IS_ERR(s3c24xx_i2s.iis_clk)) {
		pr_err("failed to get iis_clock\n");
		return PTR_ERR(s3c24xx_i2s.iis_clk);
	}
	clk_prepare_enable(s3c24xx_i2s.iis_clk);

	/* Configure the I2S pins (GPE0...GPE4) in correct mode */
	s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
			      S3C_GPIO_PULL_NONE);

	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);

	s3c24xx_snd_txctrl(0);
	s3c24xx_snd_rxctrl(0);

	return 0;
}

#ifdef CONFIG_PM
static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
{
	pr_debug("Entered %s\n", __func__);

	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);

	clk_disable_unprepare(s3c24xx_i2s.iis_clk);

	return 0;
}

static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
{
	pr_debug("Entered %s\n", __func__);
	clk_prepare_enable(s3c24xx_i2s.iis_clk);

	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);

	return 0;
}
#else
#define s3c24xx_i2s_suspend NULL
#define s3c24xx_i2s_resume NULL
#endif


#define S3C24XX_I2S_RATES \
	(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
	SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
	SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)

static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
	.trigger	= s3c24xx_i2s_trigger,
	.hw_params	= s3c24xx_i2s_hw_params,
	.set_fmt	= s3c24xx_i2s_set_fmt,
	.set_clkdiv	= s3c24xx_i2s_set_clkdiv,
	.set_sysclk	= s3c24xx_i2s_set_sysclk,
};

static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
	.probe = s3c24xx_i2s_probe,
	.suspend = s3c24xx_i2s_suspend,
	.resume = s3c24xx_i2s_resume,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = S3C24XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = S3C24XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = &s3c24xx_i2s_dai_ops,
};

static const struct snd_soc_component_driver s3c24xx_i2s_component = {
	.name		= "s3c24xx-i2s",
};

static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
{
	int ret = 0;
	struct resource *res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "Can't get IO resource.\n");
		return -ENOENT;
	}
	s3c24xx_i2s.regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(s3c24xx_i2s.regs))
		return PTR_ERR(s3c24xx_i2s.regs);

	s3c24xx_i2s_pcm_stereo_out.dma_addr = res->start + S3C2410_IISFIFO;
	s3c24xx_i2s_pcm_stereo_in.dma_addr = res->start + S3C2410_IISFIFO;

	ret = devm_snd_soc_register_component(&pdev->dev,
			&s3c24xx_i2s_component, &s3c24xx_i2s_dai, 1);
	if (ret) {
		pr_err("failed to register the dai\n");
		return ret;
	}

	ret = samsung_asoc_dma_platform_register(&pdev->dev);
	if (ret)
		pr_err("failed to register the dma: %d\n", ret);

	return ret;
}

static struct platform_driver s3c24xx_iis_driver = {
	.probe  = s3c24xx_iis_dev_probe,
	.driver = {
		.name = "s3c24xx-iis",
	},
};

module_platform_driver(s3c24xx_iis_driver);

/* Module information */
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:s3c24xx-iis");
Commit	Line	Data
c1422a66 BD	1	/*
	2	* s3c24xx-i2s.c -- ALSA Soc Audio Layer
	3	*
	4	* (c) 2006 Wolfson Microelectronics PLC.
	5	* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
	6	*
c8efef17	7	* Copyright 2004-2005 Simtec Electronics
c1422a66 BD	8	* http://armlinux.simtec.co.uk/
	9	* Ben Dooks <ben@simtec.co.uk>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
c1422a66 BD	15	*/
c1422a66 BD	16
c1422a66 BD	17	#include <linux/delay.h>
c1422a66 BD	18	#include <linux/clk.h>
40efc15f	19	#include <linux/io.h>
ec976d6e	20	#include <linux/gpio.h>
da155d5b	21	#include <linux/module.h>
ec976d6e	22
c1422a66	23	#include <sound/soc.h>
0378b6ac	24	#include <sound/pcm_params.h>
c1422a66	25
a09e64fb	26	#include <mach/dma.h>
abffae64 SK	27	#include <mach/gpio-samsung.h>
abffae64 SK	28	#include <plat/gpio-cfg.h>
5d229ce5	29	#include "regs-iis.h"
aa9673cf	30
4b640cf3	31	#include "dma.h"
c1422a66 BD	32	#include "s3c24xx-i2s.h"
c1422a66 BD	33
faa31776	34	static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = {
c1422a66	35	.channel = DMACH_I2S_OUT,
87b132bc	36	.ch_name = "tx",
e81208fe	37	.dma_size = 2,
c1422a66 BD	38	};
c1422a66 BD	39
faa31776	40	static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = {
c1422a66	41	.channel = DMACH_I2S_IN,
87b132bc	42	.ch_name = "rx",
e81208fe	43	.dma_size = 2,
c1422a66 BD	44	};
	45
	46	struct s3c24xx_i2s_info {
	47	void __iomem *regs;
	48	struct clk *iis_clk;
5cd919a2 GG	49	u32 iiscon;
	50	u32 iismod;
	51	u32 iisfcon;
	52	u32 iispsr;
c1422a66 BD	53	};
	54	static struct s3c24xx_i2s_info s3c24xx_i2s;
	55
	56	static void s3c24xx_snd_txctrl(int on)
	57	{
	58	u32 iisfcon;
	59	u32 iiscon;
	60	u32 iismod;
	61
ee7d4767	62	pr_debug("Entered %s\n", __func__);
c1422a66 BD	63
	64	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	65	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	66	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	67
5314adc3	68	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	69
	70	if (on) {
	71	iisfcon \|= S3C2410_IISFCON_TXDMA \| S3C2410_IISFCON_TXENABLE;
	72	iiscon \|= S3C2410_IISCON_TXDMAEN \| S3C2410_IISCON_IISEN;
	73	iiscon &= ~S3C2410_IISCON_TXIDLE;
	74	iismod \|= S3C2410_IISMOD_TXMODE;
	75
	76	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	77	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	78	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	79	} else {
	80	/* note, we have to disable the FIFOs otherwise bad things
	81	* seem to happen when the DMA stops. According to the
	82	* Samsung supplied kernel, this should allow the DMA
	83	* engine and FIFOs to reset. If this isn't allowed, the
	84	* DMA engine will simply freeze randomly.
	85	*/
	86
	87	iisfcon &= ~S3C2410_IISFCON_TXENABLE;
	88	iisfcon &= ~S3C2410_IISFCON_TXDMA;
	89	iiscon \|= S3C2410_IISCON_TXIDLE;
	90	iiscon &= ~S3C2410_IISCON_TXDMAEN;
	91	iismod &= ~S3C2410_IISMOD_TXMODE;
	92
	93	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	94	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	95	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	96	}
	97
5314adc3	98	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	99	}
	100
	101	static void s3c24xx_snd_rxctrl(int on)
	102	{
	103	u32 iisfcon;
	104	u32 iiscon;
	105	u32 iismod;
	106
ee7d4767	107	pr_debug("Entered %s\n", __func__);
c1422a66 BD	108
	109	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	110	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	111	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	112
5314adc3	113	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	114
	115	if (on) {
	116	iisfcon \|= S3C2410_IISFCON_RXDMA \| S3C2410_IISFCON_RXENABLE;
	117	iiscon \|= S3C2410_IISCON_RXDMAEN \| S3C2410_IISCON_IISEN;
	118	iiscon &= ~S3C2410_IISCON_RXIDLE;
	119	iismod \|= S3C2410_IISMOD_RXMODE;
	120
	121	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	122	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	123	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	124	} else {
	125	/* note, we have to disable the FIFOs otherwise bad things
	126	* seem to happen when the DMA stops. According to the
	127	* Samsung supplied kernel, this should allow the DMA
	128	* engine and FIFOs to reset. If this isn't allowed, the
	129	* DMA engine will simply freeze randomly.
	130	*/
	131
0015e7d1 MB	132	iisfcon &= ~S3C2410_IISFCON_RXENABLE;
	133	iisfcon &= ~S3C2410_IISFCON_RXDMA;
	134	iiscon \|= S3C2410_IISCON_RXIDLE;
	135	iiscon &= ~S3C2410_IISCON_RXDMAEN;
c1422a66 BD	136	iismod &= ~S3C2410_IISMOD_RXMODE;
	137
	138	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	139	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	140	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	141	}
	142
5314adc3	143	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	144	}
	145
	146	/*
	147	* Wait for the LR signal to allow synchronisation to the L/R clock
	148	* from the codec. May only be needed for slave mode.
	149	*/
	150	static int s3c24xx_snd_lrsync(void)
	151	{
	152	u32 iiscon;
33e5b222	153	int timeout = 50; /* 5ms */
c1422a66	154
ee7d4767	155	pr_debug("Entered %s\n", __func__);
c1422a66 BD	156
	157	while (1) {
	158	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	159	if (iiscon & S3C2410_IISCON_LRINDEX)
	160	break;
	161
33e5b222	162	if (!timeout--)
c1422a66	163	return -ETIMEDOUT;
33e5b222	164	udelay(100);
c1422a66 BD	165	}
	166
	167	return 0;
	168	}
	169
	170	/*
	171	* Check whether CPU is the master or slave
	172	*/
	173	static inline int s3c24xx_snd_is_clkmaster(void)
	174	{
ee7d4767	175	pr_debug("Entered %s\n", __func__);
c1422a66 BD	176
	177	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
	178	}
	179
	180	/*
	181	* Set S3C24xx I2S DAI format
	182	*/
1992a6fb	183	static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
c1422a66 BD	184	unsigned int fmt)
	185	{
	186	u32 iismod;
	187
ee7d4767	188	pr_debug("Entered %s\n", __func__);
c1422a66 BD	189
c1422a66 BD	190	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	191	pr_debug("hw_params r: IISMOD: %x \n", iismod);
c1422a66 BD	192
	193	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	194	case SND_SOC_DAIFMT_CBM_CFM:
	195	iismod \|= S3C2410_IISMOD_SLAVE;
	196	break;
	197	case SND_SOC_DAIFMT_CBS_CFS:
2c36eecf	198	iismod &= ~S3C2410_IISMOD_SLAVE;
c1422a66 BD	199	break;
	200	default:
	201	return -EINVAL;
	202	}
	203
	204	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	205	case SND_SOC_DAIFMT_LEFT_J:
	206	iismod \|= S3C2410_IISMOD_MSB;
	207	break;
	208	case SND_SOC_DAIFMT_I2S:
2c36eecf	209	iismod &= ~S3C2410_IISMOD_MSB;
c1422a66 BD	210	break;
	211	default:
	212	return -EINVAL;
	213	}
	214
	215	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	216	pr_debug("hw_params w: IISMOD: %x \n", iismod);
c1422a66 BD	217	return 0;
	218	}
	219
	220	static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	221	struct snd_pcm_hw_params *params,
dee89c4d MB	222	struct snd_soc_dai *dai)
c1422a66	223	{
87b132bc	224	struct snd_dmaengine_dai_dma_data *dma_data;
c1422a66 BD	225	u32 iismod;
c1422a66 BD	226
ee7d4767	227	pr_debug("Entered %s\n", __func__);
c1422a66	228
87b132bc	229	dma_data = snd_soc_dai_get_dma_data(dai, substream);
c1422a66 BD	230
	231	/* Working copies of register */
	232	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	233	pr_debug("hw_params r: IISMOD: %x\n", iismod);
c1422a66	234
88ce1465 TB	235	switch (params_width(params)) {
88ce1465 TB	236	case 8:
53599bbc	237	iismod &= ~S3C2410_IISMOD_16BIT;
87b132bc	238	dma_data->addr_width = 1;
c1422a66	239	break;
88ce1465	240	case 16:
c1422a66	241	iismod \|= S3C2410_IISMOD_16BIT;
87b132bc	242	dma_data->addr_width = 2;
c1422a66	243	break;
53599bbc CP	244	default:
53599bbc CP	245	return -EINVAL;
c1422a66 BD	246	}
	247
	248	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	249	pr_debug("hw_params w: IISMOD: %x\n", iismod);
c1422a66 BD	250	return 0;
	251	}
	252
dee89c4d MB	253	static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	254	struct snd_soc_dai *dai)
c1422a66 BD	255	{
	256	int ret = 0;
	257
ee7d4767	258	pr_debug("Entered %s\n", __func__);
c1422a66 BD	259
	260	switch (cmd) {
	261	case SNDRV_PCM_TRIGGER_START:
	262	case SNDRV_PCM_TRIGGER_RESUME:
	263	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	264	if (!s3c24xx_snd_is_clkmaster()) {
	265	ret = s3c24xx_snd_lrsync();
	266	if (ret)
	267	goto exit_err;
	268	}
	269
	270	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	271	s3c24xx_snd_rxctrl(1);
	272	else
	273	s3c24xx_snd_txctrl(1);
faf907c7	274
c1422a66 BD	275	break;
	276	case SNDRV_PCM_TRIGGER_STOP:
	277	case SNDRV_PCM_TRIGGER_SUSPEND:
	278	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	279	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	280	s3c24xx_snd_rxctrl(0);
	281	else
	282	s3c24xx_snd_txctrl(0);
	283	break;
	284	default:
	285	ret = -EINVAL;
	286	break;
	287	}
	288
	289	exit_err:
	290	return ret;
	291	}
	292
	293	/*
	294	* Set S3C24xx Clock source
	295	*/
1992a6fb	296	static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
c1422a66 BD	297	int clk_id, unsigned int freq, int dir)
	298	{
	299	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	300
ee7d4767	301	pr_debug("Entered %s\n", __func__);
c1422a66 BD	302
	303	iismod &= ~S3C2440_IISMOD_MPLL;
	304
	305	switch (clk_id) {
	306	case S3C24XX_CLKSRC_PCLK:
	307	break;
	308	case S3C24XX_CLKSRC_MPLL:
	309	iismod \|= S3C2440_IISMOD_MPLL;
	310	break;
	311	default:
	312	return -EINVAL;
	313	}
	314
	315	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	316	return 0;
	317	}
	318
	319	/*
	320	* Set S3C24xx Clock dividers
	321	*/
1992a6fb	322	static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
c1422a66 BD	323	int div_id, int div)
	324	{
	325	u32 reg;
	326
ee7d4767	327	pr_debug("Entered %s\n", __func__);
c1422a66 BD	328
c1422a66 BD	329	switch (div_id) {
82fb159a	330	case S3C24XX_DIV_BCLK:
c1422a66 BD	331	reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
	332	writel(reg \| div, s3c24xx_i2s.regs + S3C2410_IISMOD);
	333	break;
82fb159a	334	case S3C24XX_DIV_MCLK:
c1422a66 BD	335	reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
	336	writel(reg \| div, s3c24xx_i2s.regs + S3C2410_IISMOD);
	337	break;
	338	case S3C24XX_DIV_PRESCALER:
	339	writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
	340	reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	341	writel(reg \| S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
	342	break;
	343	default:
	344	return -EINVAL;
	345	}
	346
	347	return 0;
	348	}
	349
	350	/*
	351	* To avoid duplicating clock code, allow machine driver to
	352	* get the clockrate from here.
	353	*/
	354	u32 s3c24xx_i2s_get_clockrate(void)
	355	{
	356	return clk_get_rate(s3c24xx_i2s.iis_clk);
	357	}
	358	EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
	359
f0fba2ad	360	static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
c1422a66	361	{
ee7d4767	362	pr_debug("Entered %s\n", __func__);
c1422a66	363
87b132bc VK	364	samsung_asoc_init_dma_data(dai, &s3c24xx_i2s_pcm_stereo_out,
87b132bc VK	365	&s3c24xx_i2s_pcm_stereo_in);
c1422a66	366
87b132bc	367	s3c24xx_i2s.iis_clk = devm_clk_get(dai->dev, "iis");
7803e329	368	if (IS_ERR(s3c24xx_i2s.iis_clk)) {
b52a5195	369	pr_err("failed to get iis_clock\n");
7803e329	370	return PTR_ERR(s3c24xx_i2s.iis_clk);
c1422a66	371	}
c1ae59c7	372	clk_prepare_enable(s3c24xx_i2s.iis_clk);
c1422a66	373
0eed8a18 SN	374	/* Configure the I2S pins (GPE0...GPE4) in correct mode */
	375	s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
	376	S3C_GPIO_PULL_NONE);
c1422a66 BD	377
	378	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
	379
	380	s3c24xx_snd_txctrl(0);
	381	s3c24xx_snd_rxctrl(0);
	382
	383	return 0;
	384	}
	385
5cd919a2	386	#ifdef CONFIG_PM
dc7d7b83	387	static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
5cd919a2	388	{
ee7d4767	389	pr_debug("Entered %s\n", __func__);
40920307	390
5cd919a2 GG	391	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	392	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	393	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	394	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
	395
c1ae59c7	396	clk_disable_unprepare(s3c24xx_i2s.iis_clk);
5cd919a2 GG	397
	398	return 0;
	399	}
	400
dc7d7b83	401	static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
5cd919a2	402	{
ee7d4767	403	pr_debug("Entered %s\n", __func__);
c1ae59c7	404	clk_prepare_enable(s3c24xx_i2s.iis_clk);
5cd919a2 GG	405
	406	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	407	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	408	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	409	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
	410
	411	return 0;
	412	}
	413	#else
	414	#define s3c24xx_i2s_suspend NULL
	415	#define s3c24xx_i2s_resume NULL
	416	#endif
	417
	418
c1422a66 BD	419	#define S3C24XX_I2S_RATES \
	420	(SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \| SNDRV_PCM_RATE_16000 \| \
	421	SNDRV_PCM_RATE_22050 \| SNDRV_PCM_RATE_32000 \| SNDRV_PCM_RATE_44100 \| \
	422	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	423
85e7652d	424	static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
6335d055 EM	425	.trigger = s3c24xx_i2s_trigger,
	426	.hw_params = s3c24xx_i2s_hw_params,
	427	.set_fmt = s3c24xx_i2s_set_fmt,
	428	.set_clkdiv = s3c24xx_i2s_set_clkdiv,
	429	.set_sysclk = s3c24xx_i2s_set_sysclk,
	430	};
	431
f0fba2ad	432	static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
c1422a66	433	.probe = s3c24xx_i2s_probe,
5cd919a2 GG	434	.suspend = s3c24xx_i2s_suspend,
5cd919a2 GG	435	.resume = s3c24xx_i2s_resume,
c1422a66 BD	436	.playback = {
	437	.channels_min = 2,
	438	.channels_max = 2,
	439	.rates = S3C24XX_I2S_RATES,
	440	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,},
	441	.capture = {
	442	.channels_min = 2,
	443	.channels_max = 2,
	444	.rates = S3C24XX_I2S_RATES,
	445	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,},
6335d055	446	.ops = &s3c24xx_i2s_dai_ops,
c1422a66	447	};
f0fba2ad	448
5642ddff KM	449	static const struct snd_soc_component_driver s3c24xx_i2s_component = {
	450	.name = "s3c24xx-i2s",
	451	};
	452
fdca21ad	453	static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
f0fba2ad	454	{
a08485d8	455	int ret = 0;
87b132bc VK	456	struct resource *res;
	457
	458	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	459	if (!res) {
	460	dev_err(&pdev->dev, "Can't get IO resource.\n");
	461	return -ENOENT;
	462	}
	463	s3c24xx_i2s.regs = devm_ioremap_resource(&pdev->dev, res);
c479163a WY	464	if (IS_ERR(s3c24xx_i2s.regs))
c479163a WY	465	return PTR_ERR(s3c24xx_i2s.regs);
87b132bc VK	466
	467	s3c24xx_i2s_pcm_stereo_out.dma_addr = res->start + S3C2410_IISFIFO;
	468	s3c24xx_i2s_pcm_stereo_in.dma_addr = res->start + S3C2410_IISFIFO;
a08485d8	469
7253e354 TB	470	ret = devm_snd_soc_register_component(&pdev->dev,
7253e354 TB	471	&s3c24xx_i2s_component, &s3c24xx_i2s_dai, 1);
a08485d8 PV	472	if (ret) {
	473	pr_err("failed to register the dai\n");
	474	return ret;
	475	}
	476
06b10ff9	477	ret = samsung_asoc_dma_platform_register(&pdev->dev);
7253e354	478	if (ret)
a08485d8	479	pr_err("failed to register the dma: %d\n", ret);
a08485d8	480
a08485d8	481	return ret;
f0fba2ad LG	482	}
f0fba2ad LG	483
f0fba2ad LG	484	static struct platform_driver s3c24xx_iis_driver = {
f0fba2ad LG	485	.probe = s3c24xx_iis_dev_probe,
f0fba2ad LG	486	.driver = {
f0fba2ad LG	487	.name = "s3c24xx-iis",
f0fba2ad LG	488	},
f0fba2ad LG	489	};
c1422a66	490
e00c3f55	491	module_platform_driver(s3c24xx_iis_driver);
3f4b783c	492
c1422a66 BD	493	/* Module information */
	494	MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
	495	MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
	496	MODULE_LICENSE("GPL");
960d0697	497	MODULE_ALIAS("platform:s3c24xx-iis");