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Merge branch 'pm-cpufreq'
[linux-2.6-block.git] / sound / soc / intel / haswell / sst-haswell-ipc.c
CommitLineData
a4b12990
MB		 1/*
2 * Intel SST Haswell/Broadwell IPC Support
3 *
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/device.h>
21#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/export.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
a4b12990
MB		 28#include <linux/platform_device.h>
29#include <linux/kthread.h>
30#include <linux/firmware.h>
31#include <linux/dma-mapping.h>
32#include <linux/debugfs.h>
aed3c7b7 33#include <linux/pm_runtime.h>
1b006996 34#include <sound/asound.h>
a4b12990
MB		 35
36#include "sst-haswell-ipc.h"
ba57f682
JY		 37#include "../common/sst-dsp.h"
38#include "../common/sst-dsp-priv.h"
0e7921e9 39#include "../common/sst-ipc.h"
a4b12990
MB		 40
41/* Global Message - Generic */
42#define IPC_GLB_TYPE_SHIFT 24
43#define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
44#define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
45
46/* Global Message - Reply */
47#define IPC_GLB_REPLY_SHIFT 0
48#define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
49#define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
50
51/* Stream Message - Generic */
52#define IPC_STR_TYPE_SHIFT 20
53#define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
54#define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
55#define IPC_STR_ID_SHIFT 16
56#define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
57#define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
58
59/* Stream Message - Reply */
60#define IPC_STR_REPLY_SHIFT 0
61#define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
62
63/* Stream Stage Message - Generic */
64#define IPC_STG_TYPE_SHIFT 12
65#define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
66#define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
67#define IPC_STG_ID_SHIFT 10
68#define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
69#define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
70
71/* Stream Stage Message - Reply */
72#define IPC_STG_REPLY_SHIFT 0
73#define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
74
75/* Debug Log Message - Generic */
76#define IPC_LOG_OP_SHIFT 20
77#define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
78#define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
79#define IPC_LOG_ID_SHIFT 16
80#define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
81#define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
82
e8e79ede
LH		 83/* Module Message */
84#define IPC_MODULE_OPERATION_SHIFT 20
85#define IPC_MODULE_OPERATION_MASK (0xf << IPC_MODULE_OPERATION_SHIFT)
86#define IPC_MODULE_OPERATION(x) (x << IPC_MODULE_OPERATION_SHIFT)
87
88#define IPC_MODULE_ID_SHIFT 16
89#define IPC_MODULE_ID_MASK (0xf << IPC_MODULE_ID_SHIFT)
90#define IPC_MODULE_ID(x) (x << IPC_MODULE_ID_SHIFT)
91
a4b12990
MB		 92/* IPC message timeout (msecs) */
93#define IPC_TIMEOUT_MSECS 300
94#define IPC_BOOT_MSECS 200
95#define IPC_MSG_WAIT 0
96#define IPC_MSG_NOWAIT 1
97
98/* Firmware Ready Message */
99#define IPC_FW_READY (0x1 << 29)
100#define IPC_STATUS_MASK (0x3 << 30)
101
102#define IPC_EMPTY_LIST_SIZE 8
103#define IPC_MAX_STREAMS 4
104
105/* Mailbox */
106#define IPC_MAX_MAILBOX_BYTES 256
107
a0a7c48f
JY		 108#define INVALID_STREAM_HW_ID 0xffffffff
109
a4b12990
MB		 110/* Global Message - Types and Replies */
111enum ipc_glb_type {
112 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
113 IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
114 IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
115 IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
116 IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
117 IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
118 /* Request to store firmware context during D0->D3 transition */
119 IPC_GLB_REQUEST_DUMP = 7,
120 /* Request to restore firmware context during D3->D0 transition */
121 IPC_GLB_RESTORE_CONTEXT = 8,
122 IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
123 IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
124 IPC_GLB_SHORT_REPLY = 11,
125 IPC_GLB_ENTER_DX_STATE = 12,
126 IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
127 IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
e8e79ede 128 IPC_GLB_MODULE_OPERATION = 15, /* Message to loadable fw module */
a4b12990
MB		 129 IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
130 IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
131};
132
133enum ipc_glb_reply {
134 IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
135 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
136 IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
137 IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
138 IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
139 IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
140 IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
141 IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
142 IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
143 IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
144 IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
145};
146
e8e79ede
LH		 147enum ipc_module_operation {
148 IPC_MODULE_NOTIFICATION = 0,
149 IPC_MODULE_ENABLE = 1,
150 IPC_MODULE_DISABLE = 2,
151 IPC_MODULE_GET_PARAMETER = 3,
152 IPC_MODULE_SET_PARAMETER = 4,
153 IPC_MODULE_GET_INFO = 5,
154 IPC_MODULE_MAX_MESSAGE
155};
156
a4b12990
MB		 157/* Stream Message - Types */
158enum ipc_str_operation {
159 IPC_STR_RESET = 0,
160 IPC_STR_PAUSE = 1,
161 IPC_STR_RESUME = 2,
162 IPC_STR_STAGE_MESSAGE = 3,
163 IPC_STR_NOTIFICATION = 4,
164 IPC_STR_MAX_MESSAGE
165};
166
167/* Stream Stage Message Types */
168enum ipc_stg_operation {
169 IPC_STG_GET_VOLUME = 0,
170 IPC_STG_SET_VOLUME,
171 IPC_STG_SET_WRITE_POSITION,
172 IPC_STG_SET_FX_ENABLE,
173 IPC_STG_SET_FX_DISABLE,
174 IPC_STG_SET_FX_GET_PARAM,
175 IPC_STG_SET_FX_SET_PARAM,
176 IPC_STG_SET_FX_GET_INFO,
177 IPC_STG_MUTE_LOOPBACK,
178 IPC_STG_MAX_MESSAGE
179};
180
181/* Stream Stage Message Types For Notification*/
182enum ipc_stg_operation_notify {
183 IPC_POSITION_CHANGED = 0,
184 IPC_STG_GLITCH,
185 IPC_STG_MAX_NOTIFY
186};
187
188enum ipc_glitch_type {
189 IPC_GLITCH_UNDERRUN = 1,
190 IPC_GLITCH_DECODER_ERROR,
191 IPC_GLITCH_DOUBLED_WRITE_POS,
192 IPC_GLITCH_MAX
193};
194
195/* Debug Control */
196enum ipc_debug_operation {
197 IPC_DEBUG_ENABLE_LOG = 0,
198 IPC_DEBUG_DISABLE_LOG = 1,
199 IPC_DEBUG_REQUEST_LOG_DUMP = 2,
200 IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
201 IPC_DEBUG_MAX_DEBUG_LOG
202};
203
204/* Firmware Ready */
205struct sst_hsw_ipc_fw_ready {
206 u32 inbox_offset;
207 u32 outbox_offset;
208 u32 inbox_size;
209 u32 outbox_size;
210 u32 fw_info_size;
249adddb 211 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
a4b12990
MB		 212} __attribute__((packed));
213
a4b12990
MB		 214struct sst_hsw_stream;
215struct sst_hsw;
216
217/* Stream infomation */
218struct sst_hsw_stream {
219 /* configuration */
220 struct sst_hsw_ipc_stream_alloc_req request;
221 struct sst_hsw_ipc_stream_alloc_reply reply;
222 struct sst_hsw_ipc_stream_free_req free_req;
223
224 /* Mixer info */
225 u32 mute_volume[SST_HSW_NO_CHANNELS];
226 u32 mute[SST_HSW_NO_CHANNELS];
227
228 /* runtime info */
229 struct sst_hsw *hsw;
230 int host_id;
231 bool commited;
232 bool running;
233
234 /* Notification work */
235 struct work_struct notify_work;
236 u32 header;
237
238 /* Position info from DSP */
239 struct sst_hsw_ipc_stream_set_position wpos;
240 struct sst_hsw_ipc_stream_get_position rpos;
241 struct sst_hsw_ipc_stream_glitch_position glitch;
242
243 /* Volume info */
244 struct sst_hsw_ipc_volume_req vol_req;
245
246 /* driver callback */
247 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
248 void *pdata;
249
1b006996
LY		 250 /* record the fw read position when playback */
251 snd_pcm_uframes_t old_position;
252 bool play_silence;
a4b12990
MB		 253 struct list_head node;
254};
255
256/* FW log ring information */
257struct sst_hsw_log_stream {
258 dma_addr_t dma_addr;
259 unsigned char *dma_area;
260 unsigned char *ring_descr;
261 int pages;
262 int size;
263
264 /* Notification work */
265 struct work_struct notify_work;
266 wait_queue_head_t readers_wait_q;
267 struct mutex rw_mutex;
268
269 u32 last_pos;
270 u32 curr_pos;
271 u32 reader_pos;
272
273 /* fw log config */
274 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
275
276 struct sst_hsw *hsw;
277};
278
279/* SST Haswell IPC data */
280struct sst_hsw {
281 struct device *dev;
282 struct sst_dsp *dsp;
283 struct platform_device *pdev_pcm;
284
285 /* FW config */
286 struct sst_hsw_ipc_fw_ready fw_ready;
287 struct sst_hsw_ipc_fw_version version;
a4b12990 288 bool fw_done;
aed3c7b7 289 struct sst_fw *sst_fw;
a4b12990
MB		 290
291 /* stream */
292 struct list_head stream_list;
293
294 /* global mixer */
295 struct sst_hsw_ipc_stream_info_reply mixer_info;
296 enum sst_hsw_volume_curve curve_type;
297 u32 curve_duration;
298 u32 mute[SST_HSW_NO_CHANNELS];
299 u32 mute_volume[SST_HSW_NO_CHANNELS];
300
301 /* DX */
302 struct sst_hsw_ipc_dx_reply dx;
aed3c7b7
LG		 303 void *dx_context;
304 dma_addr_t dx_context_paddr;
f1ec5ec7
LG		 305 enum sst_hsw_device_id dx_dev;
306 enum sst_hsw_device_mclk dx_mclk;
307 enum sst_hsw_device_mode dx_mode;
308 u32 dx_clock_divider;
a4b12990
MB		 309
310 /* boot */
311 wait_queue_head_t boot_wait;
312 bool boot_complete;
313 bool shutdown;
314
315 /* IPC messaging */
0e7921e9 316 struct sst_generic_ipc ipc;
a4b12990
MB		 317
318 /* FW log stream */
319 struct sst_hsw_log_stream log_stream;
76c07b82
LH		 320
321 /* flags bit field to track module state when resume from RTD3,
322 * each bit represent state (enabled/disabled) of single module */
323 u32 enabled_modules_rtd3;
3814c204
LH		 324
325 /* buffer to store parameter lines */
326 u32 param_idx_w; /* write index */
327 u32 param_idx_r; /* read index */
328 u8 param_buf[WAVES_PARAM_LINES][WAVES_PARAM_COUNT];
a4b12990
MB		 329};
330
331#define CREATE_TRACE_POINTS
332#include <trace/events/hswadsp.h>
333
334static inline u32 msg_get_global_type(u32 msg)
335{
336 return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
337}
338
339static inline u32 msg_get_global_reply(u32 msg)
340{
341 return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
342}
343
344static inline u32 msg_get_stream_type(u32 msg)
345{
346 return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
347}
348
349static inline u32 msg_get_stage_type(u32 msg)
350{
351 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
352}
353
a4b12990
MB		 354static inline u32 msg_get_stream_id(u32 msg)
355{
356 return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
357}
358
359static inline u32 msg_get_notify_reason(u32 msg)
360{
361 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
362}
363
e8e79ede
LH		 364static inline u32 msg_get_module_operation(u32 msg)
365{
366 return (msg & IPC_MODULE_OPERATION_MASK) >> IPC_MODULE_OPERATION_SHIFT;
367}
368
369static inline u32 msg_get_module_id(u32 msg)
370{
371 return (msg & IPC_MODULE_ID_MASK) >> IPC_MODULE_ID_SHIFT;
372}
373
a4b12990
MB		 374u32 create_channel_map(enum sst_hsw_channel_config config)
375{
376 switch (config) {
377 case SST_HSW_CHANNEL_CONFIG_MONO:
378 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
379 case SST_HSW_CHANNEL_CONFIG_STEREO:
380 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
381 | (SST_HSW_CHANNEL_RIGHT << 4));
382 case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
383 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
384 | (SST_HSW_CHANNEL_RIGHT << 4)
385 | (SST_HSW_CHANNEL_LFE << 8 ));
386 case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
387 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
388 | (SST_HSW_CHANNEL_CENTER << 4)
389 | (SST_HSW_CHANNEL_RIGHT << 8));
390 case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
391 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
392 | (SST_HSW_CHANNEL_CENTER << 4)
393 | (SST_HSW_CHANNEL_RIGHT << 8)
394 | (SST_HSW_CHANNEL_LFE << 12));
395 case SST_HSW_CHANNEL_CONFIG_QUATRO:
396 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
397 | (SST_HSW_CHANNEL_RIGHT << 4)
398 | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
399 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
400 case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
401 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
402 | (SST_HSW_CHANNEL_CENTER << 4)
403 | (SST_HSW_CHANNEL_RIGHT << 8)
404 | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
405 case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
406 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
407 | (SST_HSW_CHANNEL_CENTER << 4)
408 | (SST_HSW_CHANNEL_RIGHT << 8)
409 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
410 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
411 case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
412 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
413 | (SST_HSW_CHANNEL_LEFT << 4)
414 | (SST_HSW_CHANNEL_RIGHT << 8)
415 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
416 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
417 | (SST_HSW_CHANNEL_LFE << 20));
418 case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
419 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
420 | (SST_HSW_CHANNEL_LEFT << 4));
421 default:
422 return 0xFFFFFFFF;
423 }
424}
425
426static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
427 int stream_id)
428{
429 struct sst_hsw_stream *stream;
430
431 list_for_each_entry(stream, &hsw->stream_list, node) {
432 if (stream->reply.stream_hw_id == stream_id)
433 return stream;
434 }
435
436 return NULL;
437}
438
a4b12990
MB		 439static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
440{
441 struct sst_hsw_ipc_fw_ready fw_ready;
442 u32 offset;
249adddb
JY		 443 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
444 char *tmp[5], *pinfo;
445 int i = 0;
a4b12990
MB		 446
447 offset = (header & 0x1FFFFFFF) << 3;
448
449 dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
450 header, offset);
451
452 /* copy data from the DSP FW ready offset */
453 sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
454
455 sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
456 fw_ready.inbox_size, fw_ready.outbox_offset,
457 fw_ready.outbox_size);
458
459 hsw->boot_complete = true;
460 wake_up(&hsw->boot_wait);
461
462 dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
463 fw_ready.inbox_offset, fw_ready.inbox_size);
464 dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
465 fw_ready.outbox_offset, fw_ready.outbox_size);
249adddb
JY		 466 if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
467 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
468 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
469
470 /* log the FW version info got from the mailbox here. */
471 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
472 pinfo = &fw_info[0];
a5e5e12b 473 for (i = 0; i < ARRAY_SIZE(tmp); i++)
249adddb
JY		 474 tmp[i] = strsep(&pinfo, " ");
475 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
476 "version: %s.%s, build %s, source commit id: %s\n",
477 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
478 }
a4b12990
MB		 479}
480
481static void hsw_notification_work(struct work_struct *work)
482{
483 struct sst_hsw_stream *stream = container_of(work,
484 struct sst_hsw_stream, notify_work);
485 struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
486 struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
487 struct sst_hsw *hsw = stream->hsw;
488 u32 reason;
489
490 reason = msg_get_notify_reason(stream->header);
491
492 switch (reason) {
493 case IPC_STG_GLITCH:
494 trace_ipc_notification("DSP stream under/overrun",
495 stream->reply.stream_hw_id);
496 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
497
498 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
499 glitch->glitch_type, glitch->present_pos,
500 glitch->write_pos);
501 break;
502
503 case IPC_POSITION_CHANGED:
504 trace_ipc_notification("DSP stream position changed for",
505 stream->reply.stream_hw_id);
7897ab78 506 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
a4b12990
MB		 507
508 if (stream->notify_position)
509 stream->notify_position(stream, stream->pdata);
510
511 break;
512 default:
513 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
514 stream->header);
515 break;
516 }
517
518 /* tell DSP that notification has been handled */
09a34aa5 519 sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
a4b12990
MB		 520 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
521
522 /* unmask busy interrupt */
09a34aa5 523 sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
a4b12990
MB		 524}
525
a4b12990
MB		 526static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
527{
528 struct sst_hsw_stream *stream;
529 u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
530 u32 stream_id = msg_get_stream_id(header);
531 u32 stream_msg = msg_get_stream_type(header);
532
533 stream = get_stream_by_id(hsw, stream_id);
534 if (stream == NULL)
535 return;
536
537 switch (stream_msg) {
538 case IPC_STR_STAGE_MESSAGE:
539 case IPC_STR_NOTIFICATION:
81552612 540 break;
a4b12990 541 case IPC_STR_RESET:
81552612 542 trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
a4b12990
MB		 543 break;
544 case IPC_STR_PAUSE:
545 stream->running = false;
546 trace_ipc_notification("stream paused",
547 stream->reply.stream_hw_id);
548 break;
549 case IPC_STR_RESUME:
550 stream->running = true;
551 trace_ipc_notification("stream running",
552 stream->reply.stream_hw_id);
553 break;
554 }
555}
556
557static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
558{
559 struct ipc_message *msg;
560 u32 reply = msg_get_global_reply(header);
561
562 trace_ipc_reply("processing -->", header);
563
0e7921e9 564 msg = sst_ipc_reply_find_msg(&hsw->ipc, header);
a4b12990
MB		 565 if (msg == NULL) {
566 trace_ipc_error("error: can't find message header", header);
567 return -EIO;
568 }
569
570 /* first process the header */
571 switch (reply) {
572 case IPC_GLB_REPLY_PENDING:
573 trace_ipc_pending_reply("received", header);
574 msg->pending = true;
0e7921e9 575 hsw->ipc.pending = true;
a4b12990
MB		 576 return 1;
577 case IPC_GLB_REPLY_SUCCESS:
578 if (msg->pending) {
579 trace_ipc_pending_reply("completed", header);
580 sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
581 msg->rx_size);
0e7921e9 582 hsw->ipc.pending = false;
a4b12990
MB		 583 } else {
584 /* copy data from the DSP */
585 sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
586 msg->rx_size);
587 }
588 break;
589 /* these will be rare - but useful for debug */
590 case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
591 trace_ipc_error("error: unknown message type", header);
592 msg->errno = -EBADMSG;
593 break;
594 case IPC_GLB_REPLY_OUT_OF_RESOURCES:
595 trace_ipc_error("error: out of resources", header);
596 msg->errno = -ENOMEM;
597 break;
598 case IPC_GLB_REPLY_BUSY:
599 trace_ipc_error("error: reply busy", header);
600 msg->errno = -EBUSY;
601 break;
602 case IPC_GLB_REPLY_FAILURE:
603 trace_ipc_error("error: reply failure", header);
604 msg->errno = -EINVAL;
605 break;
606 case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
607 trace_ipc_error("error: stage uninitialized", header);
608 msg->errno = -EINVAL;
609 break;
610 case IPC_GLB_REPLY_NOT_FOUND:
611 trace_ipc_error("error: reply not found", header);
612 msg->errno = -EINVAL;
613 break;
614 case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
615 trace_ipc_error("error: source not started", header);
616 msg->errno = -EINVAL;
617 break;
618 case IPC_GLB_REPLY_INVALID_REQUEST:
619 trace_ipc_error("error: invalid request", header);
620 msg->errno = -EINVAL;
621 break;
622 case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
623 trace_ipc_error("error: invalid parameter", header);
624 msg->errno = -EINVAL;
625 break;
626 default:
627 trace_ipc_error("error: unknown reply", header);
628 msg->errno = -EINVAL;
629 break;
630 }
631
632 /* update any stream states */
d6e08617
PP		 633 if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
634 hsw_stream_update(hsw, msg);
a4b12990
MB		 635
636 /* wake up and return the error if we have waiters on this message ? */
637 list_del(&msg->list);
0e7921e9 638 sst_ipc_tx_msg_reply_complete(&hsw->ipc, msg);
a4b12990
MB		 639
640 return 1;
641}
642
e8e79ede
LH		 643static int hsw_module_message(struct sst_hsw *hsw, u32 header)
644{
645 u32 operation, module_id;
646 int handled = 0;
647
648 operation = msg_get_module_operation(header);
649 module_id = msg_get_module_id(header);
650 dev_dbg(hsw->dev, "received module message header: 0x%8.8x\n",
651 header);
652 dev_dbg(hsw->dev, "operation: 0x%8.8x module_id: 0x%8.8x\n",
653 operation, module_id);
654
655 switch (operation) {
656 case IPC_MODULE_NOTIFICATION:
657 dev_dbg(hsw->dev, "module notification received");
658 handled = 1;
659 break;
660 default:
661 handled = hsw_process_reply(hsw, header);
662 break;
663 }
664
665 return handled;
666}
667
a4b12990
MB		 668static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
669{
670 u32 stream_msg, stream_id, stage_type;
671 struct sst_hsw_stream *stream;
672 int handled = 0;
673
674 stream_msg = msg_get_stream_type(header);
675 stream_id = msg_get_stream_id(header);
676 stage_type = msg_get_stage_type(header);
677
678 stream = get_stream_by_id(hsw, stream_id);
679 if (stream == NULL)
680 return handled;
681
682 stream->header = header;
683
684 switch (stream_msg) {
685 case IPC_STR_STAGE_MESSAGE:
686 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
687 header);
688 break;
689 case IPC_STR_NOTIFICATION:
690 schedule_work(&stream->notify_work);
691 break;
692 default:
693 /* handle pending message complete request */
694 handled = hsw_process_reply(hsw, header);
695 break;
696 }
697
698 return handled;
699}
700
701static int hsw_log_message(struct sst_hsw *hsw, u32 header)
702{
703 u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
704 struct sst_hsw_log_stream *stream = &hsw->log_stream;
705 int ret = 1;
706
707 if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
708 dev_err(hsw->dev,
709 "error: log msg not implemented 0x%8.8x\n", header);
710 return 0;
711 }
712
713 mutex_lock(&stream->rw_mutex);
714 stream->last_pos = stream->curr_pos;
715 sst_dsp_inbox_read(
716 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
717 mutex_unlock(&stream->rw_mutex);
718
719 schedule_work(&stream->notify_work);
720
721 return ret;
722}
723
724static int hsw_process_notification(struct sst_hsw *hsw)
725{
726 struct sst_dsp *sst = hsw->dsp;
727 u32 type, header;
728 int handled = 1;
729
730 header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
731 type = msg_get_global_type(header);
732
733 trace_ipc_request("processing -->", header);
734
735 /* FW Ready is a special case */
736 if (!hsw->boot_complete && header & IPC_FW_READY) {
737 hsw_fw_ready(hsw, header);
738 return handled;
739 }
740
741 switch (type) {
742 case IPC_GLB_GET_FW_VERSION:
743 case IPC_GLB_ALLOCATE_STREAM:
744 case IPC_GLB_FREE_STREAM:
745 case IPC_GLB_GET_FW_CAPABILITIES:
746 case IPC_GLB_REQUEST_DUMP:
747 case IPC_GLB_GET_DEVICE_FORMATS:
748 case IPC_GLB_SET_DEVICE_FORMATS:
749 case IPC_GLB_ENTER_DX_STATE:
750 case IPC_GLB_GET_MIXER_STREAM_INFO:
751 case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
752 case IPC_GLB_RESTORE_CONTEXT:
753 case IPC_GLB_SHORT_REPLY:
754 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
755 type, header);
756 break;
757 case IPC_GLB_STREAM_MESSAGE:
758 handled = hsw_stream_message(hsw, header);
759 break;
760 case IPC_GLB_DEBUG_LOG_MESSAGE:
761 handled = hsw_log_message(hsw, header);
762 break;
e8e79ede
LH		 763 case IPC_GLB_MODULE_OPERATION:
764 handled = hsw_module_message(hsw, header);
765 break;
a4b12990
MB		 766 default:
767 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
768 type, header);
769 break;
770 }
771
772 return handled;
773}
774
775static irqreturn_t hsw_irq_thread(int irq, void *context)
776{
777 struct sst_dsp *sst = (struct sst_dsp *) context;
778 struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
0e7921e9 779 struct sst_generic_ipc *ipc = &hsw->ipc;
a4b12990 780 u32 ipcx, ipcd;
a4b12990
MB		 781 unsigned long flags;
782
783 spin_lock_irqsave(&sst->spinlock, flags);
784
785 ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
786 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
787
788 /* reply message from DSP */
789 if (ipcx & SST_IPCX_DONE) {
790
791 /* Handle Immediate reply from DSP Core */
af1086ba 792 hsw_process_reply(hsw, ipcx);
a4b12990 793
af1086ba
LG		 794 /* clear DONE bit - tell DSP we have completed */
795 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
796 SST_IPCX_DONE, 0);
a4b12990 797
af1086ba
LG		 798 /* unmask Done interrupt */
799 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
800 SST_IMRX_DONE, 0);
a4b12990
MB		 801 }
802
803 /* new message from DSP */
804 if (ipcd & SST_IPCD_BUSY) {
805
806 /* Handle Notification and Delayed reply from DSP Core */
af1086ba 807 hsw_process_notification(hsw);
a4b12990
MB		 808
809 /* clear BUSY bit and set DONE bit - accept new messages */
af1086ba
LG		 810 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
811 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
a4b12990 812
af1086ba
LG		 813 /* unmask busy interrupt */
814 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
815 SST_IMRX_BUSY, 0);
a4b12990
MB		 816 }
817
818 spin_unlock_irqrestore(&sst->spinlock, flags);
819
820 /* continue to send any remaining messages... */
0e7921e9 821 queue_kthread_work(&ipc->kworker, &ipc->kwork);
a4b12990
MB		 822
823 return IRQ_HANDLED;
824}
825
826int sst_hsw_fw_get_version(struct sst_hsw *hsw,
827 struct sst_hsw_ipc_fw_version *version)
828{
829 int ret;
830
0e7921e9
JY		 831 ret = sst_ipc_tx_message_wait(&hsw->ipc,
832 IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
a4b12990
MB		 833 NULL, 0, version, sizeof(*version));
834 if (ret < 0)
835 dev_err(hsw->dev, "error: get version failed\n");
836
837 return ret;
838}
839
840/* Mixer Controls */
a4b12990
MB		 841int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
842 u32 stage_id, u32 channel, u32 *volume)
843{
844 if (channel > 1)
845 return -EINVAL;
846
847 sst_dsp_read(hsw->dsp, volume,
bf657d24
CE		 848 stream->reply.volume_register_address[channel],
849 sizeof(*volume));
a4b12990
MB		 850
851 return 0;
852}
853
a4b12990
MB		 854/* stream volume */
855int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
856 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
857{
858 struct sst_hsw_ipc_volume_req *req;
859 u32 header;
860 int ret;
861
862 trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
863
f1e59825 864 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
a4b12990
MB		 865 return -EINVAL;
866
a4b12990
MB		 867 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
868 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
869 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
870 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
871 header |= (stage_id << IPC_STG_ID_SHIFT);
872
873 req = &stream->vol_req;
a4b12990
MB		 874 req->target_volume = volume;
875
f1e59825
JY		 876 /* set both at same time ? */
877 if (channel == SST_HSW_CHANNELS_ALL) {
878 if (hsw->mute[0] && hsw->mute[1]) {
879 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
880 return 0;
881 } else if (hsw->mute[0])
882 req->channel = 1;
883 else if (hsw->mute[1])
884 req->channel = 0;
885 else
886 req->channel = SST_HSW_CHANNELS_ALL;
887 } else {
888 /* set only 1 channel */
889 if (hsw->mute[channel]) {
890 hsw->mute_volume[channel] = volume;
891 return 0;
892 }
893 req->channel = channel;
894 }
895
0e7921e9
JY		 896 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, req,
897 sizeof(*req), NULL, 0);
a4b12990
MB		 898 if (ret < 0) {
899 dev_err(hsw->dev, "error: set stream volume failed\n");
900 return ret;
901 }
902
903 return 0;
904}
905
a4b12990
MB		 906int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
907 u32 *volume)
908{
909 if (channel > 1)
910 return -EINVAL;
911
912 sst_dsp_read(hsw->dsp, volume,
913 hsw->mixer_info.volume_register_address[channel],
914 sizeof(*volume));
915
916 return 0;
917}
918
a4b12990
MB		 919/* global mixer volume */
920int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
921 u32 volume)
922{
923 struct sst_hsw_ipc_volume_req req;
924 u32 header;
925 int ret;
926
927 trace_ipc_request("set mixer volume", volume);
928
f1e59825
JY		 929 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
930 return -EINVAL;
931
a4b12990 932 /* set both at same time ? */
f1e59825 933 if (channel == SST_HSW_CHANNELS_ALL) {
a4b12990
MB		 934 if (hsw->mute[0] && hsw->mute[1]) {
935 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
936 return 0;
937 } else if (hsw->mute[0])
938 req.channel = 1;
939 else if (hsw->mute[1])
940 req.channel = 0;
941 else
f1e59825 942 req.channel = SST_HSW_CHANNELS_ALL;
a4b12990
MB		 943 } else {
944 /* set only 1 channel */
945 if (hsw->mute[channel]) {
946 hsw->mute_volume[channel] = volume;
947 return 0;
948 }
949 req.channel = channel;
950 }
951
952 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
953 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
954 header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
955 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
956 header |= (stage_id << IPC_STG_ID_SHIFT);
957
958 req.curve_duration = hsw->curve_duration;
959 req.curve_type = hsw->curve_type;
960 req.target_volume = volume;
961
0e7921e9
JY		 962 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &req,
963 sizeof(req), NULL, 0);
a4b12990
MB		 964 if (ret < 0) {
965 dev_err(hsw->dev, "error: set mixer volume failed\n");
966 return ret;
967 }
968
969 return 0;
970}
971
972/* Stream API */
973struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
974 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
975 void *data)
976{
977 struct sst_hsw_stream *stream;
d132cb0a
WD		 978 struct sst_dsp *sst = hsw->dsp;
979 unsigned long flags;
a4b12990
MB		 980
981 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
982 if (stream == NULL)
983 return NULL;
984
d132cb0a 985 spin_lock_irqsave(&sst->spinlock, flags);
a0a7c48f 986 stream->reply.stream_hw_id = INVALID_STREAM_HW_ID;
a4b12990
MB		 987 list_add(&stream->node, &hsw->stream_list);
988 stream->notify_position = notify_position;
989 stream->pdata = data;
990 stream->hsw = hsw;
991 stream->host_id = id;
992
993 /* work to process notification messages */
994 INIT_WORK(&stream->notify_work, hsw_notification_work);
d132cb0a 995 spin_unlock_irqrestore(&sst->spinlock, flags);
a4b12990
MB		 996
997 return stream;
998}
999
1000int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1001{
1002 u32 header;
1003 int ret = 0;
d132cb0a
WD		 1004 struct sst_dsp *sst = hsw->dsp;
1005 unsigned long flags;
a4b12990 1006
f81677b4
JY		 1007 if (!stream) {
1008 dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n");
1009 return 0;
1010 }
1011
a4b12990
MB		 1012 /* dont free DSP streams that are not commited */
1013 if (!stream->commited)
1014 goto out;
1015
1016 trace_ipc_request("stream free", stream->host_id);
1017
1018 stream->free_req.stream_id = stream->reply.stream_hw_id;
1019 header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1020
0e7921e9 1021 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &stream->free_req,
a4b12990
MB		 1022 sizeof(stream->free_req), NULL, 0);
1023 if (ret < 0) {
1024 dev_err(hsw->dev, "error: free stream %d failed\n",
1025 stream->free_req.stream_id);
1026 return -EAGAIN;
1027 }
1028
1029 trace_hsw_stream_free_req(stream, &stream->free_req);
1030
1031out:
de30a2cc 1032 cancel_work_sync(&stream->notify_work);
d132cb0a 1033 spin_lock_irqsave(&sst->spinlock, flags);
a4b12990
MB		 1034 list_del(&stream->node);
1035 kfree(stream);
d132cb0a 1036 spin_unlock_irqrestore(&sst->spinlock, flags);
a4b12990
MB		 1037
1038 return ret;
1039}
1040
1041int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1042 struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1043{
1044 if (stream->commited) {
1045 dev_err(hsw->dev, "error: stream committed for set bits\n");
1046 return -EINVAL;
1047 }
1048
1049 stream->request.format.bitdepth = bits;
1050 return 0;
1051}
1052
1053int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1054 struct sst_hsw_stream *stream, int channels)
1055{
1056 if (stream->commited) {
1057 dev_err(hsw->dev, "error: stream committed for set channels\n");
1058 return -EINVAL;
1059 }
1060
a4b12990
MB		 1061 stream->request.format.ch_num = channels;
1062 return 0;
1063}
1064
1065int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1066 struct sst_hsw_stream *stream, int rate)
1067{
1068 if (stream->commited) {
1069 dev_err(hsw->dev, "error: stream committed for set rate\n");
1070 return -EINVAL;
1071 }
1072
1073 stream->request.format.frequency = rate;
1074 return 0;
1075}
1076
1077int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1078 struct sst_hsw_stream *stream, u32 map,
1079 enum sst_hsw_channel_config config)
1080{
1081 if (stream->commited) {
1082 dev_err(hsw->dev, "error: stream committed for set map\n");
1083 return -EINVAL;
1084 }
1085
1086 stream->request.format.map = map;
1087 stream->request.format.config = config;
1088 return 0;
1089}
1090
1091int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1092 struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1093{
1094 if (stream->commited) {
1095 dev_err(hsw->dev, "error: stream committed for set style\n");
1096 return -EINVAL;
1097 }
1098
1099 stream->request.format.style = style;
1100 return 0;
1101}
1102
1103int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1104 struct sst_hsw_stream *stream, u32 bits)
1105{
1106 if (stream->commited) {
1107 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1108 return -EINVAL;
1109 }
1110
1111 stream->request.format.valid_bit = bits;
1112 return 0;
1113}
1114
1115/* Stream Configuration */
1116int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1117 enum sst_hsw_stream_path_id path_id,
1118 enum sst_hsw_stream_type stream_type,
1119 enum sst_hsw_stream_format format_id)
1120{
1121 if (stream->commited) {
1122 dev_err(hsw->dev, "error: stream committed for set format\n");
1123 return -EINVAL;
1124 }
1125
1126 stream->request.path_id = path_id;
1127 stream->request.stream_type = stream_type;
1128 stream->request.format_id = format_id;
1129
1130 trace_hsw_stream_alloc_request(stream, &stream->request);
1131
1132 return 0;
1133}
1134
1135int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1136 u32 ring_pt_address, u32 num_pages,
1137 u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1138{
1139 if (stream->commited) {
1140 dev_err(hsw->dev, "error: stream committed for buffer\n");
1141 return -EINVAL;
1142 }
1143
1144 stream->request.ringinfo.ring_pt_address = ring_pt_address;
1145 stream->request.ringinfo.num_pages = num_pages;
1146 stream->request.ringinfo.ring_size = ring_size;
1147 stream->request.ringinfo.ring_offset = ring_offset;
1148 stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1149
1150 trace_hsw_stream_buffer(stream);
1151
1152 return 0;
1153}
1154
1155int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
e9600bc1 1156 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime)
a4b12990
MB		 1157{
1158 struct sst_hsw_module_map *map = &stream->request.map;
e9600bc1
LG		 1159 struct sst_dsp *dsp = sst_hsw_get_dsp(hsw);
1160 struct sst_module *module = runtime->module;
a4b12990
MB		 1161
1162 if (stream->commited) {
1163 dev_err(hsw->dev, "error: stream committed for set module\n");
1164 return -EINVAL;
1165 }
1166
1167 /* only support initial module atm */
1168 map->module_entries_count = 1;
e9600bc1
LG		 1169 map->module_entries[0].module_id = module->id;
1170 map->module_entries[0].entry_point = module->entry;
1171
1172 stream->request.persistent_mem.offset =
1173 sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM);
1174 stream->request.persistent_mem.size = module->persistent_size;
1175
1176 stream->request.scratch_mem.offset =
1177 sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM);
1178 stream->request.scratch_mem.size = dsp->scratch_size;
1179
1180 dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id,
1181 runtime->id);
1182 dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n",
1183 stream->request.persistent_mem.offset,
1184 stream->request.persistent_mem.size);
1185 dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n",
1186 stream->request.scratch_mem.offset,
1187 stream->request.scratch_mem.size);
a4b12990
MB		 1188
1189 return 0;
1190}
1191
1192int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1193{
1194 struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1195 struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1196 u32 header;
1197 int ret;
1198
f81677b4
JY		 1199 if (!stream) {
1200 dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n");
1201 return 0;
1202 }
1203
1204 if (stream->commited) {
1205 dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n");
1206 return 0;
1207 }
1208
a4b12990
MB		 1209 trace_ipc_request("stream alloc", stream->host_id);
1210
1211 header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1212
0e7921e9
JY		 1213 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, str_req,
1214 sizeof(*str_req), reply, sizeof(*reply));
a4b12990
MB		 1215 if (ret < 0) {
1216 dev_err(hsw->dev, "error: stream commit failed\n");
1217 return ret;
1218 }
1219
1220 stream->commited = 1;
1221 trace_hsw_stream_alloc_reply(stream);
1222
1223 return 0;
1224}
1225
1b006996
LY		 1226snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
1227 struct sst_hsw_stream *stream)
1228{
1229 return stream->old_position;
1230}
1231
1232void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
1233 struct sst_hsw_stream *stream, snd_pcm_uframes_t val)
1234{
1235 stream->old_position = val;
1236}
1237
1238bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
1239 struct sst_hsw_stream *stream)
1240{
1241 return stream->play_silence;
1242}
1243
1244void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
1245 struct sst_hsw_stream *stream, bool val)
1246{
1247 stream->play_silence = val;
1248}
1249
a4b12990
MB		 1250/* Stream Information - these calls could be inline but we want the IPC
1251 ABI to be opaque to client PCM drivers to cope with any future ABI changes */
a4b12990
MB		 1252int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1253{
1254 struct sst_hsw_ipc_stream_info_reply *reply;
1255 u32 header;
1256 int ret;
1257
1258 reply = &hsw->mixer_info;
1259 header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1260
1261 trace_ipc_request("get global mixer info", 0);
1262
0e7921e9
JY		 1263 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0,
1264 reply, sizeof(*reply));
a4b12990
MB		 1265 if (ret < 0) {
1266 dev_err(hsw->dev, "error: get stream info failed\n");
1267 return ret;
1268 }
1269
1270 trace_hsw_mixer_info_reply(reply);
1271
1272 return 0;
1273}
1274
1275/* Send stream command */
1276static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1277 int stream_id, int wait)
1278{
1279 u32 header;
1280
1281 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1282 header |= (stream_id << IPC_STR_ID_SHIFT);
1283
1284 if (wait)
0e7921e9
JY		 1285 return sst_ipc_tx_message_wait(&hsw->ipc, header,
1286 NULL, 0, NULL, 0);
a4b12990 1287 else
0e7921e9 1288 return sst_ipc_tx_message_nowait(&hsw->ipc, header, NULL, 0);
a4b12990
MB		 1289}
1290
1291/* Stream ALSA trigger operations */
1292int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1293 int wait)
1294{
1295 int ret;
1296
f81677b4
JY		 1297 if (!stream) {
1298 dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n");
1299 return 0;
1300 }
1301
a4b12990
MB		 1302 trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1303
1304 ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1305 stream->reply.stream_hw_id, wait);
1306 if (ret < 0)
1307 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1308 stream->reply.stream_hw_id);
1309
1310 return ret;
1311}
1312
1313int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1314 int wait)
1315{
1316 int ret;
1317
f81677b4
JY		 1318 if (!stream) {
1319 dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n");
1320 return 0;
1321 }
1322
a4b12990
MB		 1323 trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1324
1325 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1326 stream->reply.stream_hw_id, wait);
1327 if (ret < 0)
1328 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1329 stream->reply.stream_hw_id);
1330
1331 return ret;
1332}
1333
1334int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1335{
1336 int ret, tries = 10;
1337
f81677b4
JY		 1338 if (!stream) {
1339 dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n");
1340 return 0;
1341 }
1342
a4b12990
MB		 1343 /* dont reset streams that are not commited */
1344 if (!stream->commited)
1345 return 0;
1346
1347 /* wait for pause to complete before we reset the stream */
b8af8b1d 1348 while (stream->running && --tries)
a4b12990
MB		 1349 msleep(1);
1350 if (!tries) {
1351 dev_err(hsw->dev, "error: reset stream %d still running\n",
1352 stream->reply.stream_hw_id);
1353 return -EINVAL;
1354 }
1355
1356 trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1357
1358 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1359 stream->reply.stream_hw_id, 1);
1360 if (ret < 0)
1361 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1362 stream->reply.stream_hw_id);
1363 return ret;
1364}
1365
1366/* Stream pointer positions */
51b4e24f 1367u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
a4b12990
MB		 1368 struct sst_hsw_stream *stream)
1369{
51b4e24f
LG		 1370 u32 rpos;
1371
1372 sst_dsp_read(hsw->dsp, &rpos,
1373 stream->reply.read_position_register_address, sizeof(rpos));
1374
1375 return rpos;
1376}
1377
1378/* Stream presentation (monotonic) positions */
1379u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1380 struct sst_hsw_stream *stream)
1381{
1382 u64 ppos;
1383
1384 sst_dsp_read(hsw->dsp, &ppos,
1385 stream->reply.presentation_position_register_address,
1386 sizeof(ppos));
1387
1388 return ppos;
a4b12990
MB		 1389}
1390
a4b12990
MB		 1391/* physical BE config */
1392int sst_hsw_device_set_config(struct sst_hsw *hsw,
1393 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1394 enum sst_hsw_device_mode mode, u32 clock_divider)
1395{
1396 struct sst_hsw_ipc_device_config_req config;
1397 u32 header;
1398 int ret;
1399
1400 trace_ipc_request("set device config", dev);
1401
f1ec5ec7
LG		 1402 hsw->dx_dev = config.ssp_interface = dev;
1403 hsw->dx_mclk = config.clock_frequency = mclk;
1404 hsw->dx_mode = config.mode = mode;
1405 hsw->dx_clock_divider = config.clock_divider = clock_divider;
f07e51c5
LG		 1406 if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
1407 config.channels = 4;
1408 else
1409 config.channels = 2;
a4b12990
MB		 1410
1411 trace_hsw_device_config_req(&config);
1412
1413 header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1414
0e7921e9
JY		 1415 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &config,
1416 sizeof(config), NULL, 0);
a4b12990
MB		 1417 if (ret < 0)
1418 dev_err(hsw->dev, "error: set device formats failed\n");
1419
1420 return ret;
1421}
1422EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1423
1424/* DX Config */
1425int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1426 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1427{
1428 u32 header, state_;
543ec637 1429 int ret, item;
a4b12990
MB		 1430
1431 header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1432 state_ = state;
1433
1434 trace_ipc_request("PM enter Dx state", state);
1435
0e7921e9
JY		 1436 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &state_,
1437 sizeof(state_), dx, sizeof(*dx));
a4b12990
MB		 1438 if (ret < 0) {
1439 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1440 return ret;
1441 }
1442
543ec637
LG		 1443 for (item = 0; item < dx->entries_no; item++) {
1444 dev_dbg(hsw->dev,
1445 "Item[%d] offset[%x] - size[%x] - source[%x]\n",
1446 item, dx->mem_info[item].offset,
1447 dx->mem_info[item].size,
1448 dx->mem_info[item].source);
1449 }
a4b12990
MB		 1450 dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1451 dx->entries_no, state);
1452
e9600bc1 1453 return ret;
a4b12990
MB		 1454}
1455
e9600bc1
LG		 1456struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
1457 int mod_id, int offset)
a4b12990 1458{
e9600bc1
LG		 1459 struct sst_dsp *dsp = hsw->dsp;
1460 struct sst_module *module;
1461 struct sst_module_runtime *runtime;
1462 int err;
a4b12990 1463
e9600bc1
LG		 1464 module = sst_module_get_from_id(dsp, mod_id);
1465 if (module == NULL) {
1466 dev_err(dsp->dev, "error: failed to get module %d for pcm\n",
1467 mod_id);
1468 return NULL;
1469 }
a4b12990 1470
e9600bc1
LG		 1471 runtime = sst_module_runtime_new(module, mod_id, NULL);
1472 if (runtime == NULL) {
1473 dev_err(dsp->dev, "error: failed to create module %d runtime\n",
1474 mod_id);
1475 return NULL;
1476 }
a4b12990 1477
e9600bc1
LG		 1478 err = sst_module_runtime_alloc_blocks(runtime, offset);
1479 if (err < 0) {
1480 dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n",
1481 mod_id);
1482 sst_module_runtime_free(runtime);
1483 return NULL;
1484 }
a4b12990 1485
e9600bc1
LG		 1486 dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id,
1487 mod_id);
1488 return runtime;
1489}
a4b12990 1490
e9600bc1
LG		 1491void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime)
1492{
1493 sst_module_runtime_free_blocks(runtime);
1494 sst_module_runtime_free(runtime);
a4b12990
MB		 1495}
1496
35e03a88 1497#ifdef CONFIG_PM
aed3c7b7
LG		 1498static int sst_hsw_dx_state_dump(struct sst_hsw *hsw)
1499{
1500 struct sst_dsp *sst = hsw->dsp;
1501 u32 item, offset, size;
1502 int ret = 0;
1503
1504 trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS);
1505
1506 if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {
1507 dev_err(hsw->dev,
1508 "error: number of FW context regions greater than %d\n",
1509 SST_HSW_MAX_DX_REGIONS);
1510 memset(&hsw->dx, 0, sizeof(hsw->dx));
1511 return -EINVAL;
1512 }
1513
1514 ret = sst_dsp_dma_get_channel(sst, 0);
1515 if (ret < 0) {
1516 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1517 return ret;
1518 }
1519
1520 /* set on-demond mode on engine 0 channel 3 */
1521 sst_dsp_shim_update_bits(sst, SST_HMDC,
1522 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
1523 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
1524
1525 for (item = 0; item < hsw->dx.entries_no; item++) {
1526 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1527 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1528 && hsw->dx.mem_info[item].offset <
1529 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1530
1531 offset = hsw->dx.mem_info[item].offset
1532 - DSP_DRAM_ADDR_OFFSET;
1533 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1534
1535 ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset,
1536 sst->addr.lpe_base + offset, size);
1537 if (ret < 0) {
1538 dev_err(hsw->dev,
1539 "error: FW context dump failed\n");
1540 memset(&hsw->dx, 0, sizeof(hsw->dx));
1541 goto out;
1542 }
1543 }
1544 }
1545
1546out:
1547 sst_dsp_dma_put_channel(sst);
1548 return ret;
1549}
1550
1551static int sst_hsw_dx_state_restore(struct sst_hsw *hsw)
1552{
1553 struct sst_dsp *sst = hsw->dsp;
1554 u32 item, offset, size;
1555 int ret;
1556
1557 for (item = 0; item < hsw->dx.entries_no; item++) {
1558 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1559 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1560 && hsw->dx.mem_info[item].offset <
1561 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1562
1563 offset = hsw->dx.mem_info[item].offset
1564 - DSP_DRAM_ADDR_OFFSET;
1565 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1566
1567 ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset,
1568 hsw->dx_context_paddr + offset, size);
1569 if (ret < 0) {
1570 dev_err(hsw->dev,
1571 "error: FW context restore failed\n");
1572 return ret;
1573 }
1574 }
1575 }
1576
1577 return 0;
1578}
1579
aed3c7b7
LG		 1580int sst_hsw_dsp_load(struct sst_hsw *hsw)
1581{
1582 struct sst_dsp *dsp = hsw->dsp;
3fe0607a 1583 struct sst_fw *sst_fw, *t;
aed3c7b7
LG		 1584 int ret;
1585
1586 dev_dbg(hsw->dev, "loading audio DSP....");
1587
1588 ret = sst_dsp_wake(dsp);
1589 if (ret < 0) {
1590 dev_err(hsw->dev, "error: failed to wake audio DSP\n");
1591 return -ENODEV;
1592 }
1593
1594 ret = sst_dsp_dma_get_channel(dsp, 0);
1595 if (ret < 0) {
1596 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1597 return ret;
1598 }
1599
3fe0607a
LH		 1600 list_for_each_entry_safe_reverse(sst_fw, t, &dsp->fw_list, list) {
1601 ret = sst_fw_reload(sst_fw);
1602 if (ret < 0) {
1603 dev_err(hsw->dev, "error: SST FW reload failed\n");
1604 sst_dsp_dma_put_channel(dsp);
1605 return -ENOMEM;
1606 }
aed3c7b7 1607 }
3fe0607a
LH		 1608 ret = sst_block_alloc_scratch(hsw->dsp);
1609 if (ret < 0)
1610 return -EINVAL;
aed3c7b7
LG		 1611
1612 sst_dsp_dma_put_channel(dsp);
1613 return 0;
1614}
1615
1616static int sst_hsw_dsp_restore(struct sst_hsw *hsw)
1617{
1618 struct sst_dsp *dsp = hsw->dsp;
1619 int ret;
1620
1621 dev_dbg(hsw->dev, "restoring audio DSP....");
1622
1623 ret = sst_dsp_dma_get_channel(dsp, 0);
1624 if (ret < 0) {
1625 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1626 return ret;
1627 }
1628
1629 ret = sst_hsw_dx_state_restore(hsw);
1630 if (ret < 0) {
1631 dev_err(hsw->dev, "error: SST FW context restore failed\n");
1632 sst_dsp_dma_put_channel(dsp);
1633 return -ENOMEM;
1634 }
1635 sst_dsp_dma_put_channel(dsp);
1636
1637 /* wait for DSP boot completion */
1638 sst_dsp_boot(dsp);
1639
1640 return ret;
1641}
1642
1643int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw)
1644{
1645 int ret;
1646
1647 dev_dbg(hsw->dev, "audio dsp runtime suspend\n");
1648
1649 ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);
1650 if (ret < 0)
1651 return ret;
1652
1653 sst_dsp_stall(hsw->dsp);
1654
1655 ret = sst_hsw_dx_state_dump(hsw);
1656 if (ret < 0)
1657 return ret;
1658
0e7921e9 1659 sst_ipc_drop_all(&hsw->ipc);
aed3c7b7
LG		 1660
1661 return 0;
1662}
1663
1664int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw)
1665{
3fe0607a
LH		 1666 struct sst_fw *sst_fw, *t;
1667 struct sst_dsp *dsp = hsw->dsp;
1668
1669 list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) {
1670 sst_fw_unload(sst_fw);
1671 }
1672 sst_block_free_scratch(dsp);
aed3c7b7
LG		 1673
1674 hsw->boot_complete = false;
1675
3fe0607a 1676 sst_dsp_sleep(dsp);
aed3c7b7
LG		 1677
1678 return 0;
1679}
1680
1681int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
1682{
1683 struct device *dev = hsw->dev;
1684 int ret;
1685
1686 dev_dbg(dev, "audio dsp runtime resume\n");
1687
1688 if (hsw->boot_complete)
1689 return 1; /* tell caller no action is required */
1690
1691 ret = sst_hsw_dsp_restore(hsw);
1692 if (ret < 0)
1693 dev_err(dev, "error: audio DSP boot failure\n");
1694
9449d39b
LH		 1695 sst_hsw_init_module_state(hsw);
1696
aed3c7b7
LG		 1697 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1698 msecs_to_jiffies(IPC_BOOT_MSECS));
1699 if (ret == 0) {
b891f62f
LG		 1700 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
1701 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
1702 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
aed3c7b7
LG		 1703 return -EIO;
1704 }
1705
f1ec5ec7
LG		 1706 /* Set ADSP SSP port settings - sadly the FW does not store SSP port
1707 settings as part of the PM context. */
1708 ret = sst_hsw_device_set_config(hsw, hsw->dx_dev, hsw->dx_mclk,
1709 hsw->dx_mode, hsw->dx_clock_divider);
aed3c7b7
LG		 1710 if (ret < 0)
1711 dev_err(dev, "error: SSP re-initialization failed\n");
1712
1713 return ret;
1714}
1715#endif
1716
a4b12990
MB		 1717struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1718{
1719 return hsw->dsp;
1720}
1721
9449d39b
LH		 1722void sst_hsw_init_module_state(struct sst_hsw *hsw)
1723{
1724 struct sst_module *module;
1725 enum sst_hsw_module_id id;
1726
1727 /* the base fw contains several modules */
1728 for (id = SST_HSW_MODULE_BASE_FW; id < SST_HSW_MAX_MODULE_ID; id++) {
1729 module = sst_module_get_from_id(hsw->dsp, id);
8c43fc2f
LH		 1730 if (module) {
1731 /* module waves is active only after being enabled */
1732 if (id == SST_HSW_MODULE_WAVES)
1733 module->state = SST_MODULE_STATE_INITIALIZED;
1734 else
1735 module->state = SST_MODULE_STATE_ACTIVE;
1736 }
9449d39b
LH		 1737 }
1738}
1739
8c43fc2f
LH		 1740bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id)
1741{
1742 struct sst_module *module;
1743
1744 module = sst_module_get_from_id(hsw->dsp, module_id);
1745 if (module == NULL || module->state == SST_MODULE_STATE_UNLOADED)
1746 return false;
1747 else
1748 return true;
1749}
1750
e8e79ede
LH		 1751bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id)
1752{
1753 struct sst_module *module;
1754
1755 module = sst_module_get_from_id(hsw->dsp, module_id);
1756 if (module != NULL && module->state == SST_MODULE_STATE_ACTIVE)
1757 return true;
1758 else
1759 return false;
1760}
1761
76c07b82
LH		 1762void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1763{
1764 hsw->enabled_modules_rtd3 |= (1 << module_id);
1765}
1766
1767void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1768{
1769 hsw->enabled_modules_rtd3 &= ~(1 << module_id);
1770}
1771
1772bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1773{
1774 return hsw->enabled_modules_rtd3 & (1 << module_id);
1775}
1776
3814c204
LH		 1777void sst_hsw_reset_param_buf(struct sst_hsw *hsw)
1778{
1779 hsw->param_idx_w = 0;
1780 hsw->param_idx_r = 0;
1781 memset((void *)hsw->param_buf, 0, sizeof(hsw->param_buf));
1782}
1783
1784int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf)
1785{
1786 /* save line to the first available position of param buffer */
1787 if (hsw->param_idx_w > WAVES_PARAM_LINES - 1) {
1788 dev_warn(hsw->dev, "warning: param buffer overflow!\n");
1789 return -EPERM;
1790 }
1791 memcpy(hsw->param_buf[hsw->param_idx_w], buf, WAVES_PARAM_COUNT);
1792 hsw->param_idx_w++;
1793 return 0;
1794}
1795
1796int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf)
1797{
1798 u8 id = 0;
1799
1800 /* read the first matching line from param buffer */
1801 while (hsw->param_idx_r < WAVES_PARAM_LINES) {
1802 id = hsw->param_buf[hsw->param_idx_r][0];
1803 hsw->param_idx_r++;
1804 if (buf[0] == id) {
1805 memcpy(buf, hsw->param_buf[hsw->param_idx_r],
1806 WAVES_PARAM_COUNT);
1807 break;
1808 }
1809 }
1810 if (hsw->param_idx_r > WAVES_PARAM_LINES - 1) {
1811 dev_dbg(hsw->dev, "end of buffer, roll to the beginning\n");
1812 hsw->param_idx_r = 0;
1813 return 0;
1814 }
1815 return 0;
1816}
1817
1818int sst_hsw_launch_param_buf(struct sst_hsw *hsw)
1819{
1820 int ret, idx;
1821
5d5b275d
LH		 1822 if (!sst_hsw_is_module_active(hsw, SST_HSW_MODULE_WAVES)) {
1823 dev_dbg(hsw->dev, "module waves is not active\n");
1824 return 0;
1825 }
1826
3814c204
LH		 1827 /* put all param lines to DSP through ipc */
1828 for (idx = 0; idx < hsw->param_idx_w; idx++) {
1829 ret = sst_hsw_module_set_param(hsw,
1830 SST_HSW_MODULE_WAVES, 0, hsw->param_buf[idx][0],
1831 WAVES_PARAM_COUNT, hsw->param_buf[idx]);
1832 if (ret < 0)
1833 return ret;
1834 }
1835 return 0;
1836}
1837
9449d39b
LH		 1838int sst_hsw_module_load(struct sst_hsw *hsw,
1839 u32 module_id, u32 instance_id, char *name)
1840{
1841 int ret = 0;
1842 const struct firmware *fw = NULL;
1843 struct sst_fw *hsw_sst_fw;
1844 struct sst_module *module;
1845 struct device *dev = hsw->dev;
1846 struct sst_dsp *dsp = hsw->dsp;
1847
1848 dev_dbg(dev, "sst_hsw_module_load id=%d, name='%s'", module_id, name);
1849
1850 module = sst_module_get_from_id(dsp, module_id);
1851 if (module == NULL) {
1852 /* loading for the first time */
1853 if (module_id == SST_HSW_MODULE_BASE_FW) {
1854 /* for base module: use fw requested in acpi probe */
1855 fw = dsp->pdata->fw;
1856 if (!fw) {
1857 dev_err(dev, "request Base fw failed\n");
1858 return -ENODEV;
1859 }
1860 } else {
1861 /* try and load any other optional modules if they are
1862 * available. Use dev_info instead of dev_err in case
1863 * request firmware failed */
1864 ret = request_firmware(&fw, name, dev);
1865 if (ret) {
1866 dev_info(dev, "fw image %s not available(%d)\n",
1867 name, ret);
1868 return ret;
1869 }
1870 }
1871 hsw_sst_fw = sst_fw_new(dsp, fw, hsw);
1872 if (hsw_sst_fw == NULL) {
1873 dev_err(dev, "error: failed to load firmware\n");
1874 ret = -ENOMEM;
1875 goto out;
1876 }
1877 module = sst_module_get_from_id(dsp, module_id);
1878 if (module == NULL) {
1879 dev_err(dev, "error: no module %d in firmware %s\n",
1880 module_id, name);
1881 }
1882 } else
1883 dev_info(dev, "module %d (%s) already loaded\n",
1884 module_id, name);
1885out:
1886 /* release fw, but base fw should be released by acpi driver */
1887 if (fw && module_id != SST_HSW_MODULE_BASE_FW)
1888 release_firmware(fw);
1889
1890 return ret;
1891}
1892
e8e79ede
LH		 1893int sst_hsw_module_enable(struct sst_hsw *hsw,
1894 u32 module_id, u32 instance_id)
1895{
1896 int ret;
1897 u32 header = 0;
1898 struct sst_hsw_ipc_module_config config;
1899 struct sst_module *module;
1900 struct sst_module_runtime *runtime;
1901 struct device *dev = hsw->dev;
1902 struct sst_dsp *dsp = hsw->dsp;
1903
1904 if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1905 dev_dbg(dev, "module %d not loaded\n", module_id);
1906 return 0;
1907 }
1908
1909 if (sst_hsw_is_module_active(hsw, module_id)) {
1910 dev_info(dev, "module %d already enabled\n", module_id);
1911 return 0;
1912 }
1913
1914 module = sst_module_get_from_id(dsp, module_id);
1915 if (module == NULL) {
1916 dev_err(dev, "module %d not valid\n", module_id);
1917 return -ENXIO;
1918 }
1919
1920 runtime = sst_module_runtime_get_from_id(module, module_id);
1921 if (runtime == NULL) {
1922 dev_err(dev, "runtime %d not valid", module_id);
1923 return -ENXIO;
1924 }
1925
1926 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1927 IPC_MODULE_OPERATION(IPC_MODULE_ENABLE) |
1928 IPC_MODULE_ID(module_id);
1929 dev_dbg(dev, "module enable header: %x\n", header);
1930
1931 config.map.module_entries_count = 1;
1932 config.map.module_entries[0].module_id = module->id;
1933 config.map.module_entries[0].entry_point = module->entry;
1934
1935 config.persistent_mem.offset =
1936 sst_dsp_get_offset(dsp,
1937 runtime->persistent_offset, SST_MEM_DRAM);
1938 config.persistent_mem.size = module->persistent_size;
1939
1940 config.scratch_mem.offset =
1941 sst_dsp_get_offset(dsp,
1942 dsp->scratch_offset, SST_MEM_DRAM);
1943 config.scratch_mem.size = module->scratch_size;
1944 dev_dbg(dev, "mod %d enable p:%d @ %x, s:%d @ %x, ep: %x",
1945 config.map.module_entries[0].module_id,
1946 config.persistent_mem.size,
1947 config.persistent_mem.offset,
1948 config.scratch_mem.size, config.scratch_mem.offset,
1949 config.map.module_entries[0].entry_point);
1950
0e7921e9 1951 ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
e8e79ede
LH		 1952 &config, sizeof(config), NULL, 0);
1953 if (ret < 0)
1954 dev_err(dev, "ipc: module enable failed - %d\n", ret);
1955 else
1956 module->state = SST_MODULE_STATE_ACTIVE;
1957
1958 return ret;
1959}
1960
1961int sst_hsw_module_disable(struct sst_hsw *hsw,
1962 u32 module_id, u32 instance_id)
1963{
1964 int ret;
1965 u32 header;
1966 struct sst_module *module;
1967 struct device *dev = hsw->dev;
1968 struct sst_dsp *dsp = hsw->dsp;
1969
1970 if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1971 dev_dbg(dev, "module %d not loaded\n", module_id);
1972 return 0;
1973 }
1974
1975 if (!sst_hsw_is_module_active(hsw, module_id)) {
1976 dev_info(dev, "module %d already disabled\n", module_id);
1977 return 0;
1978 }
1979
1980 module = sst_module_get_from_id(dsp, module_id);
1981 if (module == NULL) {
1982 dev_err(dev, "module %d not valid\n", module_id);
1983 return -ENXIO;
1984 }
1985
1986 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1987 IPC_MODULE_OPERATION(IPC_MODULE_DISABLE) |
1988 IPC_MODULE_ID(module_id);
1989
0e7921e9 1990 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0, NULL, 0);
e8e79ede
LH		 1991 if (ret < 0)
1992 dev_err(dev, "module disable failed - %d\n", ret);
1993 else
1994 module->state = SST_MODULE_STATE_INITIALIZED;
1995
1996 return ret;
1997}
1998
20189226
LH		 1999int sst_hsw_module_set_param(struct sst_hsw *hsw,
2000 u32 module_id, u32 instance_id, u32 parameter_id,
2001 u32 param_size, char *param)
2002{
2003 int ret;
2004 unsigned char *data = NULL;
2005 u32 header = 0;
2006 u32 payload_size = 0, transfer_parameter_size = 0;
2007 dma_addr_t dma_addr = 0;
2008 struct sst_hsw_transfer_parameter *parameter;
2009 struct device *dev = hsw->dev;
2010
2011 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
2012 IPC_MODULE_OPERATION(IPC_MODULE_SET_PARAMETER) |
2013 IPC_MODULE_ID(module_id);
2014 dev_dbg(dev, "sst_hsw_module_set_param header=%x\n", header);
2015
2016 payload_size = param_size +
2017 sizeof(struct sst_hsw_transfer_parameter) -
2018 sizeof(struct sst_hsw_transfer_list);
2019 dev_dbg(dev, "parameter size : %d\n", param_size);
2020 dev_dbg(dev, "payload size : %d\n", payload_size);
2021
2022 if (payload_size <= SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE) {
2023 /* short parameter, mailbox can contain data */
2024 dev_dbg(dev, "transfer parameter size : %d\n",
2025 transfer_parameter_size);
2026
2027 transfer_parameter_size = ALIGN(payload_size, 4);
2028 dev_dbg(dev, "transfer parameter aligned size : %d\n",
2029 transfer_parameter_size);
2030
2031 parameter = kzalloc(transfer_parameter_size, GFP_KERNEL);
2032 if (parameter == NULL)
2033 return -ENOMEM;
2034
2035 memcpy(parameter->data, param, param_size);
2036 } else {
2037 dev_warn(dev, "transfer parameter size too large!");
2038 return 0;
2039 }
2040
2041 parameter->parameter_id = parameter_id;
2042 parameter->data_size = param_size;
2043
0e7921e9 2044 ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
20189226
LH		 2045 parameter, transfer_parameter_size , NULL, 0);
2046 if (ret < 0)
2047 dev_err(dev, "ipc: module set parameter failed - %d\n", ret);
2048
2049 kfree(parameter);
2050
2051 if (data)
2052 dma_free_coherent(hsw->dsp->dma_dev,
2053 param_size, (void *)data, dma_addr);
2054
2055 return ret;
2056}
2057
a4b12990
MB		 2058static struct sst_dsp_device hsw_dev = {
2059 .thread = hsw_irq_thread,
2060 .ops = &haswell_ops,
2061};
2062
0e7921e9
JY		 2063static void hsw_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
2064{
2065 /* send the message */
2066 sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
2067 sst_dsp_ipc_msg_tx(ipc->dsp, msg->header);
2068}
2069
2070static void hsw_shim_dbg(struct sst_generic_ipc *ipc, const char *text)
2071{
2072 struct sst_dsp *sst = ipc->dsp;
2073 u32 isr, ipcd, imrx, ipcx;
2074
2075 ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
2076 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
2077 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
2078 imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
2079
2080 dev_err(ipc->dev,
2081 "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
2082 text, ipcx, isr, ipcd, imrx);
2083}
2084
2085static void hsw_tx_data_copy(struct ipc_message *msg, char *tx_data,
2086 size_t tx_size)
2087{
2088 memcpy(msg->tx_data, tx_data, tx_size);
2089}
2090
2091static u64 hsw_reply_msg_match(u64 header, u64 *mask)
2092{
2093 /* clear reply bits & status bits */
2094 header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
2095 *mask = (u64)-1;
2096
2097 return header;
2098}
2099
40fea921
SP		 2100static bool hsw_is_dsp_busy(struct sst_dsp *dsp)
2101{
2102 u64 ipcx;
2103
2104 ipcx = sst_dsp_shim_read_unlocked(dsp, SST_IPCX);
2105 return (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE));
2106}
2107
a4b12990
MB		 2108int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
2109{
2110 struct sst_hsw_ipc_fw_version version;
2111 struct sst_hsw *hsw;
0e7921e9 2112 struct sst_generic_ipc *ipc;
a4b12990
MB		 2113 int ret;
2114
2115 dev_dbg(dev, "initialising Audio DSP IPC\n");
2116
2117 hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
2118 if (hsw == NULL)
2119 return -ENOMEM;
2120
4b563ea3
JY		 2121 hsw->dev = dev;
2122
0e7921e9
JY		 2123 ipc = &hsw->ipc;
2124 ipc->dev = dev;
2125 ipc->ops.tx_msg = hsw_tx_msg;
2126 ipc->ops.shim_dbg = hsw_shim_dbg;
2127 ipc->ops.tx_data_copy = hsw_tx_data_copy;
2128 ipc->ops.reply_msg_match = hsw_reply_msg_match;
40fea921 2129 ipc->ops.is_dsp_busy = hsw_is_dsp_busy;
a4b12990 2130
d0e72cc0
SP		 2131 ipc->tx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2132 ipc->rx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2133
0e7921e9
JY		 2134 ret = sst_ipc_init(ipc);
2135 if (ret != 0)
2136 goto ipc_init_err;
a4b12990 2137
0e7921e9
JY		 2138 INIT_LIST_HEAD(&hsw->stream_list);
2139 init_waitqueue_head(&hsw->boot_wait);
a4b12990
MB		 2140 hsw_dev.thread_context = hsw;
2141
2142 /* init SST shim */
2143 hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
2144 if (hsw->dsp == NULL) {
2145 ret = -ENODEV;
0e7921e9 2146 goto dsp_new_err;
a4b12990
MB		 2147 }
2148
0e7921e9
JY		 2149 ipc->dsp = hsw->dsp;
2150
aed3c7b7
LG		 2151 /* allocate DMA buffer for context storage */
2152 hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev,
2153 SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL);
2154 if (hsw->dx_context == NULL) {
2155 ret = -ENOMEM;
2156 goto dma_err;
2157 }
2158
a4b12990
MB		 2159 /* keep the DSP in reset state for base FW loading */
2160 sst_dsp_reset(hsw->dsp);
2161
9449d39b
LH		 2162 /* load base module and other modules in base firmware image */
2163 ret = sst_hsw_module_load(hsw, SST_HSW_MODULE_BASE_FW, 0, "Base");
2164 if (ret < 0)
a4b12990 2165 goto fw_err;
a4b12990 2166
8c43fc2f
LH		 2167 /* try to load module waves */
2168 sst_hsw_module_load(hsw, SST_HSW_MODULE_WAVES, 0, "intel/IntcPP01.bin");
2169
3fe0607a
LH		 2170 /* allocate scratch mem regions */
2171 ret = sst_block_alloc_scratch(hsw->dsp);
2172 if (ret < 0)
2173 goto boot_err;
2174
3814c204
LH		 2175 /* init param buffer */
2176 sst_hsw_reset_param_buf(hsw);
2177
a4b12990
MB		 2178 /* wait for DSP boot completion */
2179 sst_dsp_boot(hsw->dsp);
2180 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
2181 msecs_to_jiffies(IPC_BOOT_MSECS));
2182 if (ret == 0) {
2183 ret = -EIO;
b891f62f
LG		 2184 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
2185 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
2186 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
a4b12990
MB		 2187 goto boot_err;
2188 }
2189
9449d39b
LH		 2190 /* init module state after boot */
2191 sst_hsw_init_module_state(hsw);
2192
a4b12990
MB		 2193 /* get the FW version */
2194 sst_hsw_fw_get_version(hsw, &version);
a4b12990
MB		 2195
2196 /* get the globalmixer */
2197 ret = sst_hsw_mixer_get_info(hsw);
2198 if (ret < 0) {
2199 dev_err(hsw->dev, "error: failed to get stream info\n");
2200 goto boot_err;
2201 }
2202
2203 pdata->dsp = hsw;
2204 return 0;
2205
2206boot_err:
2207 sst_dsp_reset(hsw->dsp);
9449d39b 2208 sst_fw_free_all(hsw->dsp);
a4b12990 2209fw_err:
aed3c7b7
LG		 2210 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2211 hsw->dx_context, hsw->dx_context_paddr);
2212dma_err:
a4b12990 2213 sst_dsp_free(hsw->dsp);
0e7921e9
JY		 2214dsp_new_err:
2215 sst_ipc_fini(ipc);
2216ipc_init_err:
a4b12990
MB		 2217 return ret;
2218}
2219EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
2220
2221void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
2222{
2223 struct sst_hsw *hsw = pdata->dsp;
2224
2225 sst_dsp_reset(hsw->dsp);
2226 sst_fw_free_all(hsw->dsp);
aed3c7b7
LG		 2227 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2228 hsw->dx_context, hsw->dx_context_paddr);
a4b12990 2229 sst_dsp_free(hsw->dsp);
0e7921e9 2230 sst_ipc_fini(&hsw->ipc);
a4b12990
MB		 2231}
2232EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);
Linux 6.x block layer and io_uring tree(s)