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Merge branches 'acpi-resources', 'acpi-battery', 'acpi-doc' and 'acpi-pnp'
[linux-2.6-block.git] / sound / soc / intel / haswell / sst-haswell-ipc.c
CommitLineData
a4b12990
MB		 1/*
2 * Intel SST Haswell/Broadwell IPC Support
3 *
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/device.h>
21#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/export.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
a4b12990
MB		 28#include <linux/platform_device.h>
29#include <linux/kthread.h>
30#include <linux/firmware.h>
31#include <linux/dma-mapping.h>
32#include <linux/debugfs.h>
aed3c7b7 33#include <linux/pm_runtime.h>
1b006996 34#include <sound/asound.h>
a4b12990
MB		 35
36#include "sst-haswell-ipc.h"
ba57f682
JY		 37#include "../common/sst-dsp.h"
38#include "../common/sst-dsp-priv.h"
0e7921e9 39#include "../common/sst-ipc.h"
a4b12990
MB		 40
41/* Global Message - Generic */
42#define IPC_GLB_TYPE_SHIFT 24
43#define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
44#define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
45
46/* Global Message - Reply */
47#define IPC_GLB_REPLY_SHIFT 0
48#define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
49#define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
50
51/* Stream Message - Generic */
52#define IPC_STR_TYPE_SHIFT 20
53#define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
54#define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
55#define IPC_STR_ID_SHIFT 16
56#define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
57#define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
58
59/* Stream Message - Reply */
60#define IPC_STR_REPLY_SHIFT 0
61#define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
62
63/* Stream Stage Message - Generic */
64#define IPC_STG_TYPE_SHIFT 12
65#define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
66#define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
67#define IPC_STG_ID_SHIFT 10
68#define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
69#define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
70
71/* Stream Stage Message - Reply */
72#define IPC_STG_REPLY_SHIFT 0
73#define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
74
75/* Debug Log Message - Generic */
76#define IPC_LOG_OP_SHIFT 20
77#define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
78#define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
79#define IPC_LOG_ID_SHIFT 16
80#define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
81#define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
82
e8e79ede
LH		 83/* Module Message */
84#define IPC_MODULE_OPERATION_SHIFT 20
85#define IPC_MODULE_OPERATION_MASK (0xf << IPC_MODULE_OPERATION_SHIFT)
86#define IPC_MODULE_OPERATION(x) (x << IPC_MODULE_OPERATION_SHIFT)
87
88#define IPC_MODULE_ID_SHIFT 16
89#define IPC_MODULE_ID_MASK (0xf << IPC_MODULE_ID_SHIFT)
90#define IPC_MODULE_ID(x) (x << IPC_MODULE_ID_SHIFT)
91
a4b12990
MB		 92/* IPC message timeout (msecs) */
93#define IPC_TIMEOUT_MSECS 300
94#define IPC_BOOT_MSECS 200
95#define IPC_MSG_WAIT 0
96#define IPC_MSG_NOWAIT 1
97
98/* Firmware Ready Message */
99#define IPC_FW_READY (0x1 << 29)
100#define IPC_STATUS_MASK (0x3 << 30)
101
102#define IPC_EMPTY_LIST_SIZE 8
103#define IPC_MAX_STREAMS 4
104
105/* Mailbox */
106#define IPC_MAX_MAILBOX_BYTES 256
107
a0a7c48f
JY		 108#define INVALID_STREAM_HW_ID 0xffffffff
109
a4b12990
MB		 110/* Global Message - Types and Replies */
111enum ipc_glb_type {
112 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
113 IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
114 IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
115 IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
116 IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
117 IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
118 /* Request to store firmware context during D0->D3 transition */
119 IPC_GLB_REQUEST_DUMP = 7,
120 /* Request to restore firmware context during D3->D0 transition */
121 IPC_GLB_RESTORE_CONTEXT = 8,
122 IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
123 IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
124 IPC_GLB_SHORT_REPLY = 11,
125 IPC_GLB_ENTER_DX_STATE = 12,
126 IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
127 IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
e8e79ede 128 IPC_GLB_MODULE_OPERATION = 15, /* Message to loadable fw module */
a4b12990
MB		 129 IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
130 IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
131};
132
133enum ipc_glb_reply {
134 IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
135 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
136 IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
137 IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
138 IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
139 IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
140 IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
141 IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
142 IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
143 IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
144 IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
145};
146
e8e79ede
LH		 147enum ipc_module_operation {
148 IPC_MODULE_NOTIFICATION = 0,
149 IPC_MODULE_ENABLE = 1,
150 IPC_MODULE_DISABLE = 2,
151 IPC_MODULE_GET_PARAMETER = 3,
152 IPC_MODULE_SET_PARAMETER = 4,
153 IPC_MODULE_GET_INFO = 5,
154 IPC_MODULE_MAX_MESSAGE
155};
156
a4b12990
MB		 157/* Stream Message - Types */
158enum ipc_str_operation {
159 IPC_STR_RESET = 0,
160 IPC_STR_PAUSE = 1,
161 IPC_STR_RESUME = 2,
162 IPC_STR_STAGE_MESSAGE = 3,
163 IPC_STR_NOTIFICATION = 4,
164 IPC_STR_MAX_MESSAGE
165};
166
167/* Stream Stage Message Types */
168enum ipc_stg_operation {
169 IPC_STG_GET_VOLUME = 0,
170 IPC_STG_SET_VOLUME,
171 IPC_STG_SET_WRITE_POSITION,
172 IPC_STG_SET_FX_ENABLE,
173 IPC_STG_SET_FX_DISABLE,
174 IPC_STG_SET_FX_GET_PARAM,
175 IPC_STG_SET_FX_SET_PARAM,
176 IPC_STG_SET_FX_GET_INFO,
177 IPC_STG_MUTE_LOOPBACK,
178 IPC_STG_MAX_MESSAGE
179};
180
181/* Stream Stage Message Types For Notification*/
182enum ipc_stg_operation_notify {
183 IPC_POSITION_CHANGED = 0,
184 IPC_STG_GLITCH,
185 IPC_STG_MAX_NOTIFY
186};
187
188enum ipc_glitch_type {
189 IPC_GLITCH_UNDERRUN = 1,
190 IPC_GLITCH_DECODER_ERROR,
191 IPC_GLITCH_DOUBLED_WRITE_POS,
192 IPC_GLITCH_MAX
193};
194
195/* Debug Control */
196enum ipc_debug_operation {
197 IPC_DEBUG_ENABLE_LOG = 0,
198 IPC_DEBUG_DISABLE_LOG = 1,
199 IPC_DEBUG_REQUEST_LOG_DUMP = 2,
200 IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
201 IPC_DEBUG_MAX_DEBUG_LOG
202};
203
204/* Firmware Ready */
205struct sst_hsw_ipc_fw_ready {
206 u32 inbox_offset;
207 u32 outbox_offset;
208 u32 inbox_size;
209 u32 outbox_size;
210 u32 fw_info_size;
249adddb 211 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
a4b12990
MB		 212} __attribute__((packed));
213
a4b12990
MB		 214struct sst_hsw_stream;
215struct sst_hsw;
216
217/* Stream infomation */
218struct sst_hsw_stream {
219 /* configuration */
220 struct sst_hsw_ipc_stream_alloc_req request;
221 struct sst_hsw_ipc_stream_alloc_reply reply;
222 struct sst_hsw_ipc_stream_free_req free_req;
223
224 /* Mixer info */
225 u32 mute_volume[SST_HSW_NO_CHANNELS];
226 u32 mute[SST_HSW_NO_CHANNELS];
227
228 /* runtime info */
229 struct sst_hsw *hsw;
230 int host_id;
231 bool commited;
232 bool running;
233
234 /* Notification work */
235 struct work_struct notify_work;
236 u32 header;
237
238 /* Position info from DSP */
239 struct sst_hsw_ipc_stream_set_position wpos;
240 struct sst_hsw_ipc_stream_get_position rpos;
241 struct sst_hsw_ipc_stream_glitch_position glitch;
242
243 /* Volume info */
244 struct sst_hsw_ipc_volume_req vol_req;
245
246 /* driver callback */
247 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
248 void *pdata;
249
1b006996
LY		 250 /* record the fw read position when playback */
251 snd_pcm_uframes_t old_position;
252 bool play_silence;
a4b12990
MB		 253 struct list_head node;
254};
255
256/* FW log ring information */
257struct sst_hsw_log_stream {
258 dma_addr_t dma_addr;
259 unsigned char *dma_area;
260 unsigned char *ring_descr;
261 int pages;
262 int size;
263
264 /* Notification work */
265 struct work_struct notify_work;
266 wait_queue_head_t readers_wait_q;
267 struct mutex rw_mutex;
268
269 u32 last_pos;
270 u32 curr_pos;
271 u32 reader_pos;
272
273 /* fw log config */
274 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
275
276 struct sst_hsw *hsw;
277};
278
279/* SST Haswell IPC data */
280struct sst_hsw {
281 struct device *dev;
282 struct sst_dsp *dsp;
283 struct platform_device *pdev_pcm;
284
285 /* FW config */
286 struct sst_hsw_ipc_fw_ready fw_ready;
287 struct sst_hsw_ipc_fw_version version;
a4b12990 288 bool fw_done;
aed3c7b7 289 struct sst_fw *sst_fw;
a4b12990
MB		 290
291 /* stream */
292 struct list_head stream_list;
293
294 /* global mixer */
295 struct sst_hsw_ipc_stream_info_reply mixer_info;
296 enum sst_hsw_volume_curve curve_type;
297 u32 curve_duration;
298 u32 mute[SST_HSW_NO_CHANNELS];
299 u32 mute_volume[SST_HSW_NO_CHANNELS];
300
301 /* DX */
302 struct sst_hsw_ipc_dx_reply dx;
aed3c7b7
LG		 303 void *dx_context;
304 dma_addr_t dx_context_paddr;
a4b12990
MB		 305
306 /* boot */
307 wait_queue_head_t boot_wait;
308 bool boot_complete;
309 bool shutdown;
310
311 /* IPC messaging */
0e7921e9 312 struct sst_generic_ipc ipc;
a4b12990
MB		 313
314 /* FW log stream */
315 struct sst_hsw_log_stream log_stream;
76c07b82
LH		 316
317 /* flags bit field to track module state when resume from RTD3,
318 * each bit represent state (enabled/disabled) of single module */
319 u32 enabled_modules_rtd3;
3814c204
LH		 320
321 /* buffer to store parameter lines */
322 u32 param_idx_w; /* write index */
323 u32 param_idx_r; /* read index */
324 u8 param_buf[WAVES_PARAM_LINES][WAVES_PARAM_COUNT];
a4b12990
MB		 325};
326
327#define CREATE_TRACE_POINTS
328#include <trace/events/hswadsp.h>
329
330static inline u32 msg_get_global_type(u32 msg)
331{
332 return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
333}
334
335static inline u32 msg_get_global_reply(u32 msg)
336{
337 return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
338}
339
340static inline u32 msg_get_stream_type(u32 msg)
341{
342 return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
343}
344
345static inline u32 msg_get_stage_type(u32 msg)
346{
347 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
348}
349
a4b12990
MB		 350static inline u32 msg_get_stream_id(u32 msg)
351{
352 return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
353}
354
355static inline u32 msg_get_notify_reason(u32 msg)
356{
357 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
358}
359
e8e79ede
LH		 360static inline u32 msg_get_module_operation(u32 msg)
361{
362 return (msg & IPC_MODULE_OPERATION_MASK) >> IPC_MODULE_OPERATION_SHIFT;
363}
364
365static inline u32 msg_get_module_id(u32 msg)
366{
367 return (msg & IPC_MODULE_ID_MASK) >> IPC_MODULE_ID_SHIFT;
368}
369
a4b12990
MB		 370u32 create_channel_map(enum sst_hsw_channel_config config)
371{
372 switch (config) {
373 case SST_HSW_CHANNEL_CONFIG_MONO:
374 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
375 case SST_HSW_CHANNEL_CONFIG_STEREO:
376 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
377 | (SST_HSW_CHANNEL_RIGHT << 4));
378 case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
379 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
380 | (SST_HSW_CHANNEL_RIGHT << 4)
381 | (SST_HSW_CHANNEL_LFE << 8 ));
382 case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
383 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
384 | (SST_HSW_CHANNEL_CENTER << 4)
385 | (SST_HSW_CHANNEL_RIGHT << 8));
386 case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
387 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
388 | (SST_HSW_CHANNEL_CENTER << 4)
389 | (SST_HSW_CHANNEL_RIGHT << 8)
390 | (SST_HSW_CHANNEL_LFE << 12));
391 case SST_HSW_CHANNEL_CONFIG_QUATRO:
392 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
393 | (SST_HSW_CHANNEL_RIGHT << 4)
394 | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
395 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
396 case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
397 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
398 | (SST_HSW_CHANNEL_CENTER << 4)
399 | (SST_HSW_CHANNEL_RIGHT << 8)
400 | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
401 case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
402 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
403 | (SST_HSW_CHANNEL_CENTER << 4)
404 | (SST_HSW_CHANNEL_RIGHT << 8)
405 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
406 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
407 case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
408 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
409 | (SST_HSW_CHANNEL_LEFT << 4)
410 | (SST_HSW_CHANNEL_RIGHT << 8)
411 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
412 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
413 | (SST_HSW_CHANNEL_LFE << 20));
414 case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
415 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
416 | (SST_HSW_CHANNEL_LEFT << 4));
417 default:
418 return 0xFFFFFFFF;
419 }
420}
421
422static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
423 int stream_id)
424{
425 struct sst_hsw_stream *stream;
426
427 list_for_each_entry(stream, &hsw->stream_list, node) {
428 if (stream->reply.stream_hw_id == stream_id)
429 return stream;
430 }
431
432 return NULL;
433}
434
a4b12990
MB		 435static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
436{
437 struct sst_hsw_ipc_fw_ready fw_ready;
438 u32 offset;
249adddb
JY		 439 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
440 char *tmp[5], *pinfo;
441 int i = 0;
a4b12990
MB		 442
443 offset = (header & 0x1FFFFFFF) << 3;
444
445 dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
446 header, offset);
447
448 /* copy data from the DSP FW ready offset */
449 sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
450
451 sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
452 fw_ready.inbox_size, fw_ready.outbox_offset,
453 fw_ready.outbox_size);
454
455 hsw->boot_complete = true;
456 wake_up(&hsw->boot_wait);
457
458 dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
459 fw_ready.inbox_offset, fw_ready.inbox_size);
460 dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
461 fw_ready.outbox_offset, fw_ready.outbox_size);
249adddb
JY		 462 if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
463 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
464 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
465
466 /* log the FW version info got from the mailbox here. */
467 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
468 pinfo = &fw_info[0];
a5e5e12b 469 for (i = 0; i < ARRAY_SIZE(tmp); i++)
249adddb
JY		 470 tmp[i] = strsep(&pinfo, " ");
471 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
472 "version: %s.%s, build %s, source commit id: %s\n",
473 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
474 }
a4b12990
MB		 475}
476
477static void hsw_notification_work(struct work_struct *work)
478{
479 struct sst_hsw_stream *stream = container_of(work,
480 struct sst_hsw_stream, notify_work);
481 struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
482 struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
483 struct sst_hsw *hsw = stream->hsw;
484 u32 reason;
485
486 reason = msg_get_notify_reason(stream->header);
487
488 switch (reason) {
489 case IPC_STG_GLITCH:
490 trace_ipc_notification("DSP stream under/overrun",
491 stream->reply.stream_hw_id);
492 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
493
494 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
495 glitch->glitch_type, glitch->present_pos,
496 glitch->write_pos);
497 break;
498
499 case IPC_POSITION_CHANGED:
500 trace_ipc_notification("DSP stream position changed for",
501 stream->reply.stream_hw_id);
7897ab78 502 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
a4b12990
MB		 503
504 if (stream->notify_position)
505 stream->notify_position(stream, stream->pdata);
506
507 break;
508 default:
509 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
510 stream->header);
511 break;
512 }
513
514 /* tell DSP that notification has been handled */
09a34aa5 515 sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
a4b12990
MB		 516 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
517
518 /* unmask busy interrupt */
09a34aa5 519 sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
a4b12990
MB		 520}
521
a4b12990
MB		 522static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
523{
524 struct sst_hsw_stream *stream;
525 u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
526 u32 stream_id = msg_get_stream_id(header);
527 u32 stream_msg = msg_get_stream_type(header);
528
529 stream = get_stream_by_id(hsw, stream_id);
530 if (stream == NULL)
531 return;
532
533 switch (stream_msg) {
534 case IPC_STR_STAGE_MESSAGE:
535 case IPC_STR_NOTIFICATION:
81552612 536 break;
a4b12990 537 case IPC_STR_RESET:
81552612 538 trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
a4b12990
MB		 539 break;
540 case IPC_STR_PAUSE:
541 stream->running = false;
542 trace_ipc_notification("stream paused",
543 stream->reply.stream_hw_id);
544 break;
545 case IPC_STR_RESUME:
546 stream->running = true;
547 trace_ipc_notification("stream running",
548 stream->reply.stream_hw_id);
549 break;
550 }
551}
552
553static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
554{
555 struct ipc_message *msg;
556 u32 reply = msg_get_global_reply(header);
557
558 trace_ipc_reply("processing -->", header);
559
0e7921e9 560 msg = sst_ipc_reply_find_msg(&hsw->ipc, header);
a4b12990
MB		 561 if (msg == NULL) {
562 trace_ipc_error("error: can't find message header", header);
563 return -EIO;
564 }
565
566 /* first process the header */
567 switch (reply) {
568 case IPC_GLB_REPLY_PENDING:
569 trace_ipc_pending_reply("received", header);
570 msg->pending = true;
0e7921e9 571 hsw->ipc.pending = true;
a4b12990
MB		 572 return 1;
573 case IPC_GLB_REPLY_SUCCESS:
574 if (msg->pending) {
575 trace_ipc_pending_reply("completed", header);
576 sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
577 msg->rx_size);
0e7921e9 578 hsw->ipc.pending = false;
a4b12990
MB		 579 } else {
580 /* copy data from the DSP */
581 sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
582 msg->rx_size);
583 }
584 break;
585 /* these will be rare - but useful for debug */
586 case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
587 trace_ipc_error("error: unknown message type", header);
588 msg->errno = -EBADMSG;
589 break;
590 case IPC_GLB_REPLY_OUT_OF_RESOURCES:
591 trace_ipc_error("error: out of resources", header);
592 msg->errno = -ENOMEM;
593 break;
594 case IPC_GLB_REPLY_BUSY:
595 trace_ipc_error("error: reply busy", header);
596 msg->errno = -EBUSY;
597 break;
598 case IPC_GLB_REPLY_FAILURE:
599 trace_ipc_error("error: reply failure", header);
600 msg->errno = -EINVAL;
601 break;
602 case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
603 trace_ipc_error("error: stage uninitialized", header);
604 msg->errno = -EINVAL;
605 break;
606 case IPC_GLB_REPLY_NOT_FOUND:
607 trace_ipc_error("error: reply not found", header);
608 msg->errno = -EINVAL;
609 break;
610 case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
611 trace_ipc_error("error: source not started", header);
612 msg->errno = -EINVAL;
613 break;
614 case IPC_GLB_REPLY_INVALID_REQUEST:
615 trace_ipc_error("error: invalid request", header);
616 msg->errno = -EINVAL;
617 break;
618 case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
619 trace_ipc_error("error: invalid parameter", header);
620 msg->errno = -EINVAL;
621 break;
622 default:
623 trace_ipc_error("error: unknown reply", header);
624 msg->errno = -EINVAL;
625 break;
626 }
627
628 /* update any stream states */
d6e08617
PP		 629 if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
630 hsw_stream_update(hsw, msg);
a4b12990
MB		 631
632 /* wake up and return the error if we have waiters on this message ? */
633 list_del(&msg->list);
0e7921e9 634 sst_ipc_tx_msg_reply_complete(&hsw->ipc, msg);
a4b12990
MB		 635
636 return 1;
637}
638
e8e79ede
LH		 639static int hsw_module_message(struct sst_hsw *hsw, u32 header)
640{
641 u32 operation, module_id;
642 int handled = 0;
643
644 operation = msg_get_module_operation(header);
645 module_id = msg_get_module_id(header);
646 dev_dbg(hsw->dev, "received module message header: 0x%8.8x\n",
647 header);
648 dev_dbg(hsw->dev, "operation: 0x%8.8x module_id: 0x%8.8x\n",
649 operation, module_id);
650
651 switch (operation) {
652 case IPC_MODULE_NOTIFICATION:
653 dev_dbg(hsw->dev, "module notification received");
654 handled = 1;
655 break;
656 default:
657 handled = hsw_process_reply(hsw, header);
658 break;
659 }
660
661 return handled;
662}
663
a4b12990
MB		 664static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
665{
666 u32 stream_msg, stream_id, stage_type;
667 struct sst_hsw_stream *stream;
668 int handled = 0;
669
670 stream_msg = msg_get_stream_type(header);
671 stream_id = msg_get_stream_id(header);
672 stage_type = msg_get_stage_type(header);
673
674 stream = get_stream_by_id(hsw, stream_id);
675 if (stream == NULL)
676 return handled;
677
678 stream->header = header;
679
680 switch (stream_msg) {
681 case IPC_STR_STAGE_MESSAGE:
682 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
683 header);
684 break;
685 case IPC_STR_NOTIFICATION:
686 schedule_work(&stream->notify_work);
687 break;
688 default:
689 /* handle pending message complete request */
690 handled = hsw_process_reply(hsw, header);
691 break;
692 }
693
694 return handled;
695}
696
697static int hsw_log_message(struct sst_hsw *hsw, u32 header)
698{
699 u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
700 struct sst_hsw_log_stream *stream = &hsw->log_stream;
701 int ret = 1;
702
703 if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
704 dev_err(hsw->dev,
705 "error: log msg not implemented 0x%8.8x\n", header);
706 return 0;
707 }
708
709 mutex_lock(&stream->rw_mutex);
710 stream->last_pos = stream->curr_pos;
711 sst_dsp_inbox_read(
712 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
713 mutex_unlock(&stream->rw_mutex);
714
715 schedule_work(&stream->notify_work);
716
717 return ret;
718}
719
720static int hsw_process_notification(struct sst_hsw *hsw)
721{
722 struct sst_dsp *sst = hsw->dsp;
723 u32 type, header;
724 int handled = 1;
725
726 header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
727 type = msg_get_global_type(header);
728
729 trace_ipc_request("processing -->", header);
730
731 /* FW Ready is a special case */
732 if (!hsw->boot_complete && header & IPC_FW_READY) {
733 hsw_fw_ready(hsw, header);
734 return handled;
735 }
736
737 switch (type) {
738 case IPC_GLB_GET_FW_VERSION:
739 case IPC_GLB_ALLOCATE_STREAM:
740 case IPC_GLB_FREE_STREAM:
741 case IPC_GLB_GET_FW_CAPABILITIES:
742 case IPC_GLB_REQUEST_DUMP:
743 case IPC_GLB_GET_DEVICE_FORMATS:
744 case IPC_GLB_SET_DEVICE_FORMATS:
745 case IPC_GLB_ENTER_DX_STATE:
746 case IPC_GLB_GET_MIXER_STREAM_INFO:
747 case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
748 case IPC_GLB_RESTORE_CONTEXT:
749 case IPC_GLB_SHORT_REPLY:
750 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
751 type, header);
752 break;
753 case IPC_GLB_STREAM_MESSAGE:
754 handled = hsw_stream_message(hsw, header);
755 break;
756 case IPC_GLB_DEBUG_LOG_MESSAGE:
757 handled = hsw_log_message(hsw, header);
758 break;
e8e79ede
LH		 759 case IPC_GLB_MODULE_OPERATION:
760 handled = hsw_module_message(hsw, header);
761 break;
a4b12990
MB		 762 default:
763 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
764 type, header);
765 break;
766 }
767
768 return handled;
769}
770
771static irqreturn_t hsw_irq_thread(int irq, void *context)
772{
773 struct sst_dsp *sst = (struct sst_dsp *) context;
774 struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
0e7921e9 775 struct sst_generic_ipc *ipc = &hsw->ipc;
a4b12990
MB		 776 u32 ipcx, ipcd;
777 int handled;
778 unsigned long flags;
779
780 spin_lock_irqsave(&sst->spinlock, flags);
781
782 ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
783 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
784
785 /* reply message from DSP */
786 if (ipcx & SST_IPCX_DONE) {
787
788 /* Handle Immediate reply from DSP Core */
789 handled = hsw_process_reply(hsw, ipcx);
790
791 if (handled > 0) {
792 /* clear DONE bit - tell DSP we have completed */
793 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
794 SST_IPCX_DONE, 0);
795
796 /* unmask Done interrupt */
797 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
798 SST_IMRX_DONE, 0);
799 }
800 }
801
802 /* new message from DSP */
803 if (ipcd & SST_IPCD_BUSY) {
804
805 /* Handle Notification and Delayed reply from DSP Core */
806 handled = hsw_process_notification(hsw);
807
808 /* clear BUSY bit and set DONE bit - accept new messages */
809 if (handled > 0) {
810 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
811 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
812
813 /* unmask busy interrupt */
814 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
815 SST_IMRX_BUSY, 0);
816 }
817 }
818
819 spin_unlock_irqrestore(&sst->spinlock, flags);
820
821 /* continue to send any remaining messages... */
0e7921e9 822 queue_kthread_work(&ipc->kworker, &ipc->kwork);
a4b12990
MB		 823
824 return IRQ_HANDLED;
825}
826
827int sst_hsw_fw_get_version(struct sst_hsw *hsw,
828 struct sst_hsw_ipc_fw_version *version)
829{
830 int ret;
831
0e7921e9
JY		 832 ret = sst_ipc_tx_message_wait(&hsw->ipc,
833 IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
a4b12990
MB		 834 NULL, 0, version, sizeof(*version));
835 if (ret < 0)
836 dev_err(hsw->dev, "error: get version failed\n");
837
838 return ret;
839}
840
841/* Mixer Controls */
a4b12990
MB		 842int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
843 u32 stage_id, u32 channel, u32 *volume)
844{
845 if (channel > 1)
846 return -EINVAL;
847
848 sst_dsp_read(hsw->dsp, volume,
bf657d24
CE		 849 stream->reply.volume_register_address[channel],
850 sizeof(*volume));
a4b12990
MB		 851
852 return 0;
853}
854
a4b12990
MB		 855/* stream volume */
856int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
857 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
858{
859 struct sst_hsw_ipc_volume_req *req;
860 u32 header;
861 int ret;
862
863 trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
864
f1e59825 865 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
a4b12990
MB		 866 return -EINVAL;
867
a4b12990
MB		 868 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
869 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
870 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
871 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
872 header |= (stage_id << IPC_STG_ID_SHIFT);
873
874 req = &stream->vol_req;
a4b12990
MB		 875 req->target_volume = volume;
876
f1e59825
JY		 877 /* set both at same time ? */
878 if (channel == SST_HSW_CHANNELS_ALL) {
879 if (hsw->mute[0] && hsw->mute[1]) {
880 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
881 return 0;
882 } else if (hsw->mute[0])
883 req->channel = 1;
884 else if (hsw->mute[1])
885 req->channel = 0;
886 else
887 req->channel = SST_HSW_CHANNELS_ALL;
888 } else {
889 /* set only 1 channel */
890 if (hsw->mute[channel]) {
891 hsw->mute_volume[channel] = volume;
892 return 0;
893 }
894 req->channel = channel;
895 }
896
0e7921e9
JY		 897 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, req,
898 sizeof(*req), NULL, 0);
a4b12990
MB		 899 if (ret < 0) {
900 dev_err(hsw->dev, "error: set stream volume failed\n");
901 return ret;
902 }
903
904 return 0;
905}
906
a4b12990
MB		 907int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
908 u32 *volume)
909{
910 if (channel > 1)
911 return -EINVAL;
912
913 sst_dsp_read(hsw->dsp, volume,
914 hsw->mixer_info.volume_register_address[channel],
915 sizeof(*volume));
916
917 return 0;
918}
919
a4b12990
MB		 920/* global mixer volume */
921int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
922 u32 volume)
923{
924 struct sst_hsw_ipc_volume_req req;
925 u32 header;
926 int ret;
927
928 trace_ipc_request("set mixer volume", volume);
929
f1e59825
JY		 930 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
931 return -EINVAL;
932
a4b12990 933 /* set both at same time ? */
f1e59825 934 if (channel == SST_HSW_CHANNELS_ALL) {
a4b12990
MB		 935 if (hsw->mute[0] && hsw->mute[1]) {
936 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
937 return 0;
938 } else if (hsw->mute[0])
939 req.channel = 1;
940 else if (hsw->mute[1])
941 req.channel = 0;
942 else
f1e59825 943 req.channel = SST_HSW_CHANNELS_ALL;
a4b12990
MB		 944 } else {
945 /* set only 1 channel */
946 if (hsw->mute[channel]) {
947 hsw->mute_volume[channel] = volume;
948 return 0;
949 }
950 req.channel = channel;
951 }
952
953 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
954 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
955 header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
956 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
957 header |= (stage_id << IPC_STG_ID_SHIFT);
958
959 req.curve_duration = hsw->curve_duration;
960 req.curve_type = hsw->curve_type;
961 req.target_volume = volume;
962
0e7921e9
JY		 963 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &req,
964 sizeof(req), NULL, 0);
a4b12990
MB		 965 if (ret < 0) {
966 dev_err(hsw->dev, "error: set mixer volume failed\n");
967 return ret;
968 }
969
970 return 0;
971}
972
973/* Stream API */
974struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
975 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
976 void *data)
977{
978 struct sst_hsw_stream *stream;
d132cb0a
WD		 979 struct sst_dsp *sst = hsw->dsp;
980 unsigned long flags;
a4b12990
MB		 981
982 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
983 if (stream == NULL)
984 return NULL;
985
d132cb0a 986 spin_lock_irqsave(&sst->spinlock, flags);
a0a7c48f 987 stream->reply.stream_hw_id = INVALID_STREAM_HW_ID;
a4b12990
MB		 988 list_add(&stream->node, &hsw->stream_list);
989 stream->notify_position = notify_position;
990 stream->pdata = data;
991 stream->hsw = hsw;
992 stream->host_id = id;
993
994 /* work to process notification messages */
995 INIT_WORK(&stream->notify_work, hsw_notification_work);
d132cb0a 996 spin_unlock_irqrestore(&sst->spinlock, flags);
a4b12990
MB		 997
998 return stream;
999}
1000
1001int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1002{
1003 u32 header;
1004 int ret = 0;
d132cb0a
WD		 1005 struct sst_dsp *sst = hsw->dsp;
1006 unsigned long flags;
a4b12990 1007
f81677b4
JY		 1008 if (!stream) {
1009 dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n");
1010 return 0;
1011 }
1012
a4b12990
MB		 1013 /* dont free DSP streams that are not commited */
1014 if (!stream->commited)
1015 goto out;
1016
1017 trace_ipc_request("stream free", stream->host_id);
1018
1019 stream->free_req.stream_id = stream->reply.stream_hw_id;
1020 header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1021
0e7921e9 1022 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &stream->free_req,
a4b12990
MB		 1023 sizeof(stream->free_req), NULL, 0);
1024 if (ret < 0) {
1025 dev_err(hsw->dev, "error: free stream %d failed\n",
1026 stream->free_req.stream_id);
1027 return -EAGAIN;
1028 }
1029
1030 trace_hsw_stream_free_req(stream, &stream->free_req);
1031
1032out:
de30a2cc 1033 cancel_work_sync(&stream->notify_work);
d132cb0a 1034 spin_lock_irqsave(&sst->spinlock, flags);
a4b12990
MB		 1035 list_del(&stream->node);
1036 kfree(stream);
d132cb0a 1037 spin_unlock_irqrestore(&sst->spinlock, flags);
a4b12990
MB		 1038
1039 return ret;
1040}
1041
1042int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1043 struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1044{
1045 if (stream->commited) {
1046 dev_err(hsw->dev, "error: stream committed for set bits\n");
1047 return -EINVAL;
1048 }
1049
1050 stream->request.format.bitdepth = bits;
1051 return 0;
1052}
1053
1054int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1055 struct sst_hsw_stream *stream, int channels)
1056{
1057 if (stream->commited) {
1058 dev_err(hsw->dev, "error: stream committed for set channels\n");
1059 return -EINVAL;
1060 }
1061
a4b12990
MB		 1062 stream->request.format.ch_num = channels;
1063 return 0;
1064}
1065
1066int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1067 struct sst_hsw_stream *stream, int rate)
1068{
1069 if (stream->commited) {
1070 dev_err(hsw->dev, "error: stream committed for set rate\n");
1071 return -EINVAL;
1072 }
1073
1074 stream->request.format.frequency = rate;
1075 return 0;
1076}
1077
1078int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1079 struct sst_hsw_stream *stream, u32 map,
1080 enum sst_hsw_channel_config config)
1081{
1082 if (stream->commited) {
1083 dev_err(hsw->dev, "error: stream committed for set map\n");
1084 return -EINVAL;
1085 }
1086
1087 stream->request.format.map = map;
1088 stream->request.format.config = config;
1089 return 0;
1090}
1091
1092int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1093 struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1094{
1095 if (stream->commited) {
1096 dev_err(hsw->dev, "error: stream committed for set style\n");
1097 return -EINVAL;
1098 }
1099
1100 stream->request.format.style = style;
1101 return 0;
1102}
1103
1104int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1105 struct sst_hsw_stream *stream, u32 bits)
1106{
1107 if (stream->commited) {
1108 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1109 return -EINVAL;
1110 }
1111
1112 stream->request.format.valid_bit = bits;
1113 return 0;
1114}
1115
1116/* Stream Configuration */
1117int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1118 enum sst_hsw_stream_path_id path_id,
1119 enum sst_hsw_stream_type stream_type,
1120 enum sst_hsw_stream_format format_id)
1121{
1122 if (stream->commited) {
1123 dev_err(hsw->dev, "error: stream committed for set format\n");
1124 return -EINVAL;
1125 }
1126
1127 stream->request.path_id = path_id;
1128 stream->request.stream_type = stream_type;
1129 stream->request.format_id = format_id;
1130
1131 trace_hsw_stream_alloc_request(stream, &stream->request);
1132
1133 return 0;
1134}
1135
1136int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1137 u32 ring_pt_address, u32 num_pages,
1138 u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1139{
1140 if (stream->commited) {
1141 dev_err(hsw->dev, "error: stream committed for buffer\n");
1142 return -EINVAL;
1143 }
1144
1145 stream->request.ringinfo.ring_pt_address = ring_pt_address;
1146 stream->request.ringinfo.num_pages = num_pages;
1147 stream->request.ringinfo.ring_size = ring_size;
1148 stream->request.ringinfo.ring_offset = ring_offset;
1149 stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1150
1151 trace_hsw_stream_buffer(stream);
1152
1153 return 0;
1154}
1155
1156int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
e9600bc1 1157 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime)
a4b12990
MB		 1158{
1159 struct sst_hsw_module_map *map = &stream->request.map;
e9600bc1
LG		 1160 struct sst_dsp *dsp = sst_hsw_get_dsp(hsw);
1161 struct sst_module *module = runtime->module;
a4b12990
MB		 1162
1163 if (stream->commited) {
1164 dev_err(hsw->dev, "error: stream committed for set module\n");
1165 return -EINVAL;
1166 }
1167
1168 /* only support initial module atm */
1169 map->module_entries_count = 1;
e9600bc1
LG		 1170 map->module_entries[0].module_id = module->id;
1171 map->module_entries[0].entry_point = module->entry;
1172
1173 stream->request.persistent_mem.offset =
1174 sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM);
1175 stream->request.persistent_mem.size = module->persistent_size;
1176
1177 stream->request.scratch_mem.offset =
1178 sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM);
1179 stream->request.scratch_mem.size = dsp->scratch_size;
1180
1181 dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id,
1182 runtime->id);
1183 dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n",
1184 stream->request.persistent_mem.offset,
1185 stream->request.persistent_mem.size);
1186 dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n",
1187 stream->request.scratch_mem.offset,
1188 stream->request.scratch_mem.size);
a4b12990
MB		 1189
1190 return 0;
1191}
1192
1193int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1194{
1195 struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1196 struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1197 u32 header;
1198 int ret;
1199
f81677b4
JY		 1200 if (!stream) {
1201 dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n");
1202 return 0;
1203 }
1204
1205 if (stream->commited) {
1206 dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n");
1207 return 0;
1208 }
1209
a4b12990
MB		 1210 trace_ipc_request("stream alloc", stream->host_id);
1211
1212 header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1213
0e7921e9
JY		 1214 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, str_req,
1215 sizeof(*str_req), reply, sizeof(*reply));
a4b12990
MB		 1216 if (ret < 0) {
1217 dev_err(hsw->dev, "error: stream commit failed\n");
1218 return ret;
1219 }
1220
1221 stream->commited = 1;
1222 trace_hsw_stream_alloc_reply(stream);
1223
1224 return 0;
1225}
1226
1b006996
LY		 1227snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
1228 struct sst_hsw_stream *stream)
1229{
1230 return stream->old_position;
1231}
1232
1233void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
1234 struct sst_hsw_stream *stream, snd_pcm_uframes_t val)
1235{
1236 stream->old_position = val;
1237}
1238
1239bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
1240 struct sst_hsw_stream *stream)
1241{
1242 return stream->play_silence;
1243}
1244
1245void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
1246 struct sst_hsw_stream *stream, bool val)
1247{
1248 stream->play_silence = val;
1249}
1250
a4b12990
MB		 1251/* Stream Information - these calls could be inline but we want the IPC
1252 ABI to be opaque to client PCM drivers to cope with any future ABI changes */
a4b12990
MB		 1253int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1254{
1255 struct sst_hsw_ipc_stream_info_reply *reply;
1256 u32 header;
1257 int ret;
1258
1259 reply = &hsw->mixer_info;
1260 header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1261
1262 trace_ipc_request("get global mixer info", 0);
1263
0e7921e9
JY		 1264 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0,
1265 reply, sizeof(*reply));
a4b12990
MB		 1266 if (ret < 0) {
1267 dev_err(hsw->dev, "error: get stream info failed\n");
1268 return ret;
1269 }
1270
1271 trace_hsw_mixer_info_reply(reply);
1272
1273 return 0;
1274}
1275
1276/* Send stream command */
1277static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1278 int stream_id, int wait)
1279{
1280 u32 header;
1281
1282 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1283 header |= (stream_id << IPC_STR_ID_SHIFT);
1284
1285 if (wait)
0e7921e9
JY		 1286 return sst_ipc_tx_message_wait(&hsw->ipc, header,
1287 NULL, 0, NULL, 0);
a4b12990 1288 else
0e7921e9 1289 return sst_ipc_tx_message_nowait(&hsw->ipc, header, NULL, 0);
a4b12990
MB		 1290}
1291
1292/* Stream ALSA trigger operations */
1293int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1294 int wait)
1295{
1296 int ret;
1297
f81677b4
JY		 1298 if (!stream) {
1299 dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n");
1300 return 0;
1301 }
1302
a4b12990
MB		 1303 trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1304
1305 ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1306 stream->reply.stream_hw_id, wait);
1307 if (ret < 0)
1308 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1309 stream->reply.stream_hw_id);
1310
1311 return ret;
1312}
1313
1314int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1315 int wait)
1316{
1317 int ret;
1318
f81677b4
JY		 1319 if (!stream) {
1320 dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n");
1321 return 0;
1322 }
1323
a4b12990
MB		 1324 trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1325
1326 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1327 stream->reply.stream_hw_id, wait);
1328 if (ret < 0)
1329 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1330 stream->reply.stream_hw_id);
1331
1332 return ret;
1333}
1334
1335int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1336{
1337 int ret, tries = 10;
1338
f81677b4
JY		 1339 if (!stream) {
1340 dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n");
1341 return 0;
1342 }
1343
a4b12990
MB		 1344 /* dont reset streams that are not commited */
1345 if (!stream->commited)
1346 return 0;
1347
1348 /* wait for pause to complete before we reset the stream */
1349 while (stream->running && tries--)
1350 msleep(1);
1351 if (!tries) {
1352 dev_err(hsw->dev, "error: reset stream %d still running\n",
1353 stream->reply.stream_hw_id);
1354 return -EINVAL;
1355 }
1356
1357 trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1358
1359 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1360 stream->reply.stream_hw_id, 1);
1361 if (ret < 0)
1362 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1363 stream->reply.stream_hw_id);
1364 return ret;
1365}
1366
1367/* Stream pointer positions */
51b4e24f 1368u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
a4b12990
MB		 1369 struct sst_hsw_stream *stream)
1370{
51b4e24f
LG		 1371 u32 rpos;
1372
1373 sst_dsp_read(hsw->dsp, &rpos,
1374 stream->reply.read_position_register_address, sizeof(rpos));
1375
1376 return rpos;
1377}
1378
1379/* Stream presentation (monotonic) positions */
1380u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1381 struct sst_hsw_stream *stream)
1382{
1383 u64 ppos;
1384
1385 sst_dsp_read(hsw->dsp, &ppos,
1386 stream->reply.presentation_position_register_address,
1387 sizeof(ppos));
1388
1389 return ppos;
a4b12990
MB		 1390}
1391
a4b12990
MB		 1392/* physical BE config */
1393int sst_hsw_device_set_config(struct sst_hsw *hsw,
1394 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1395 enum sst_hsw_device_mode mode, u32 clock_divider)
1396{
1397 struct sst_hsw_ipc_device_config_req config;
1398 u32 header;
1399 int ret;
1400
1401 trace_ipc_request("set device config", dev);
1402
1403 config.ssp_interface = dev;
1404 config.clock_frequency = mclk;
1405 config.mode = mode;
1406 config.clock_divider = clock_divider;
f07e51c5
LG		 1407 if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
1408 config.channels = 4;
1409 else
1410 config.channels = 2;
a4b12990
MB		 1411
1412 trace_hsw_device_config_req(&config);
1413
1414 header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1415
0e7921e9
JY		 1416 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &config,
1417 sizeof(config), NULL, 0);
a4b12990
MB		 1418 if (ret < 0)
1419 dev_err(hsw->dev, "error: set device formats failed\n");
1420
1421 return ret;
1422}
1423EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1424
1425/* DX Config */
1426int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1427 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1428{
1429 u32 header, state_;
543ec637 1430 int ret, item;
a4b12990
MB		 1431
1432 header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1433 state_ = state;
1434
1435 trace_ipc_request("PM enter Dx state", state);
1436
0e7921e9
JY		 1437 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &state_,
1438 sizeof(state_), dx, sizeof(*dx));
a4b12990
MB		 1439 if (ret < 0) {
1440 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1441 return ret;
1442 }
1443
543ec637
LG		 1444 for (item = 0; item < dx->entries_no; item++) {
1445 dev_dbg(hsw->dev,
1446 "Item[%d] offset[%x] - size[%x] - source[%x]\n",
1447 item, dx->mem_info[item].offset,
1448 dx->mem_info[item].size,
1449 dx->mem_info[item].source);
1450 }
a4b12990
MB		 1451 dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1452 dx->entries_no, state);
1453
e9600bc1 1454 return ret;
a4b12990
MB		 1455}
1456
e9600bc1
LG		 1457struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
1458 int mod_id, int offset)
a4b12990 1459{
e9600bc1
LG		 1460 struct sst_dsp *dsp = hsw->dsp;
1461 struct sst_module *module;
1462 struct sst_module_runtime *runtime;
1463 int err;
a4b12990 1464
e9600bc1
LG		 1465 module = sst_module_get_from_id(dsp, mod_id);
1466 if (module == NULL) {
1467 dev_err(dsp->dev, "error: failed to get module %d for pcm\n",
1468 mod_id);
1469 return NULL;
1470 }
a4b12990 1471
e9600bc1
LG		 1472 runtime = sst_module_runtime_new(module, mod_id, NULL);
1473 if (runtime == NULL) {
1474 dev_err(dsp->dev, "error: failed to create module %d runtime\n",
1475 mod_id);
1476 return NULL;
1477 }
a4b12990 1478
e9600bc1
LG		 1479 err = sst_module_runtime_alloc_blocks(runtime, offset);
1480 if (err < 0) {
1481 dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n",
1482 mod_id);
1483 sst_module_runtime_free(runtime);
1484 return NULL;
1485 }
a4b12990 1486
e9600bc1
LG		 1487 dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id,
1488 mod_id);
1489 return runtime;
1490}
a4b12990 1491
e9600bc1
LG		 1492void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime)
1493{
1494 sst_module_runtime_free_blocks(runtime);
1495 sst_module_runtime_free(runtime);
a4b12990
MB		 1496}
1497
35e03a88 1498#ifdef CONFIG_PM
aed3c7b7
LG		 1499static int sst_hsw_dx_state_dump(struct sst_hsw *hsw)
1500{
1501 struct sst_dsp *sst = hsw->dsp;
1502 u32 item, offset, size;
1503 int ret = 0;
1504
1505 trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS);
1506
1507 if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {
1508 dev_err(hsw->dev,
1509 "error: number of FW context regions greater than %d\n",
1510 SST_HSW_MAX_DX_REGIONS);
1511 memset(&hsw->dx, 0, sizeof(hsw->dx));
1512 return -EINVAL;
1513 }
1514
1515 ret = sst_dsp_dma_get_channel(sst, 0);
1516 if (ret < 0) {
1517 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1518 return ret;
1519 }
1520
1521 /* set on-demond mode on engine 0 channel 3 */
1522 sst_dsp_shim_update_bits(sst, SST_HMDC,
1523 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
1524 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
1525
1526 for (item = 0; item < hsw->dx.entries_no; item++) {
1527 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1528 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1529 && hsw->dx.mem_info[item].offset <
1530 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1531
1532 offset = hsw->dx.mem_info[item].offset
1533 - DSP_DRAM_ADDR_OFFSET;
1534 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1535
1536 ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset,
1537 sst->addr.lpe_base + offset, size);
1538 if (ret < 0) {
1539 dev_err(hsw->dev,
1540 "error: FW context dump failed\n");
1541 memset(&hsw->dx, 0, sizeof(hsw->dx));
1542 goto out;
1543 }
1544 }
1545 }
1546
1547out:
1548 sst_dsp_dma_put_channel(sst);
1549 return ret;
1550}
1551
1552static int sst_hsw_dx_state_restore(struct sst_hsw *hsw)
1553{
1554 struct sst_dsp *sst = hsw->dsp;
1555 u32 item, offset, size;
1556 int ret;
1557
1558 for (item = 0; item < hsw->dx.entries_no; item++) {
1559 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1560 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1561 && hsw->dx.mem_info[item].offset <
1562 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1563
1564 offset = hsw->dx.mem_info[item].offset
1565 - DSP_DRAM_ADDR_OFFSET;
1566 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1567
1568 ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset,
1569 hsw->dx_context_paddr + offset, size);
1570 if (ret < 0) {
1571 dev_err(hsw->dev,
1572 "error: FW context restore failed\n");
1573 return ret;
1574 }
1575 }
1576 }
1577
1578 return 0;
1579}
1580
aed3c7b7
LG		 1581int sst_hsw_dsp_load(struct sst_hsw *hsw)
1582{
1583 struct sst_dsp *dsp = hsw->dsp;
3fe0607a 1584 struct sst_fw *sst_fw, *t;
aed3c7b7
LG		 1585 int ret;
1586
1587 dev_dbg(hsw->dev, "loading audio DSP....");
1588
1589 ret = sst_dsp_wake(dsp);
1590 if (ret < 0) {
1591 dev_err(hsw->dev, "error: failed to wake audio DSP\n");
1592 return -ENODEV;
1593 }
1594
1595 ret = sst_dsp_dma_get_channel(dsp, 0);
1596 if (ret < 0) {
1597 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1598 return ret;
1599 }
1600
3fe0607a
LH		 1601 list_for_each_entry_safe_reverse(sst_fw, t, &dsp->fw_list, list) {
1602 ret = sst_fw_reload(sst_fw);
1603 if (ret < 0) {
1604 dev_err(hsw->dev, "error: SST FW reload failed\n");
1605 sst_dsp_dma_put_channel(dsp);
1606 return -ENOMEM;
1607 }
aed3c7b7 1608 }
3fe0607a
LH		 1609 ret = sst_block_alloc_scratch(hsw->dsp);
1610 if (ret < 0)
1611 return -EINVAL;
aed3c7b7
LG		 1612
1613 sst_dsp_dma_put_channel(dsp);
1614 return 0;
1615}
1616
1617static int sst_hsw_dsp_restore(struct sst_hsw *hsw)
1618{
1619 struct sst_dsp *dsp = hsw->dsp;
1620 int ret;
1621
1622 dev_dbg(hsw->dev, "restoring audio DSP....");
1623
1624 ret = sst_dsp_dma_get_channel(dsp, 0);
1625 if (ret < 0) {
1626 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1627 return ret;
1628 }
1629
1630 ret = sst_hsw_dx_state_restore(hsw);
1631 if (ret < 0) {
1632 dev_err(hsw->dev, "error: SST FW context restore failed\n");
1633 sst_dsp_dma_put_channel(dsp);
1634 return -ENOMEM;
1635 }
1636 sst_dsp_dma_put_channel(dsp);
1637
1638 /* wait for DSP boot completion */
1639 sst_dsp_boot(dsp);
1640
1641 return ret;
1642}
1643
1644int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw)
1645{
1646 int ret;
1647
1648 dev_dbg(hsw->dev, "audio dsp runtime suspend\n");
1649
1650 ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);
1651 if (ret < 0)
1652 return ret;
1653
1654 sst_dsp_stall(hsw->dsp);
1655
1656 ret = sst_hsw_dx_state_dump(hsw);
1657 if (ret < 0)
1658 return ret;
1659
0e7921e9 1660 sst_ipc_drop_all(&hsw->ipc);
aed3c7b7
LG		 1661
1662 return 0;
1663}
1664
1665int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw)
1666{
3fe0607a
LH		 1667 struct sst_fw *sst_fw, *t;
1668 struct sst_dsp *dsp = hsw->dsp;
1669
1670 list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) {
1671 sst_fw_unload(sst_fw);
1672 }
1673 sst_block_free_scratch(dsp);
aed3c7b7
LG		 1674
1675 hsw->boot_complete = false;
1676
3fe0607a 1677 sst_dsp_sleep(dsp);
aed3c7b7
LG		 1678
1679 return 0;
1680}
1681
1682int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
1683{
1684 struct device *dev = hsw->dev;
1685 int ret;
1686
1687 dev_dbg(dev, "audio dsp runtime resume\n");
1688
1689 if (hsw->boot_complete)
1690 return 1; /* tell caller no action is required */
1691
1692 ret = sst_hsw_dsp_restore(hsw);
1693 if (ret < 0)
1694 dev_err(dev, "error: audio DSP boot failure\n");
1695
9449d39b
LH		 1696 sst_hsw_init_module_state(hsw);
1697
aed3c7b7
LG		 1698 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1699 msecs_to_jiffies(IPC_BOOT_MSECS));
1700 if (ret == 0) {
b891f62f
LG		 1701 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
1702 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
1703 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
aed3c7b7
LG		 1704 return -EIO;
1705 }
1706
1707 /* Set ADSP SSP port settings */
1708 ret = sst_hsw_device_set_config(hsw, SST_HSW_DEVICE_SSP_0,
1709 SST_HSW_DEVICE_MCLK_FREQ_24_MHZ,
1710 SST_HSW_DEVICE_CLOCK_MASTER, 9);
1711 if (ret < 0)
1712 dev_err(dev, "error: SSP re-initialization failed\n");
1713
1714 return ret;
1715}
1716#endif
1717
a4b12990
MB		 1718struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1719{
1720 return hsw->dsp;
1721}
1722
9449d39b
LH		 1723void sst_hsw_init_module_state(struct sst_hsw *hsw)
1724{
1725 struct sst_module *module;
1726 enum sst_hsw_module_id id;
1727
1728 /* the base fw contains several modules */
1729 for (id = SST_HSW_MODULE_BASE_FW; id < SST_HSW_MAX_MODULE_ID; id++) {
1730 module = sst_module_get_from_id(hsw->dsp, id);
8c43fc2f
LH		 1731 if (module) {
1732 /* module waves is active only after being enabled */
1733 if (id == SST_HSW_MODULE_WAVES)
1734 module->state = SST_MODULE_STATE_INITIALIZED;
1735 else
1736 module->state = SST_MODULE_STATE_ACTIVE;
1737 }
9449d39b
LH		 1738 }
1739}
1740
8c43fc2f
LH		 1741bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id)
1742{
1743 struct sst_module *module;
1744
1745 module = sst_module_get_from_id(hsw->dsp, module_id);
1746 if (module == NULL || module->state == SST_MODULE_STATE_UNLOADED)
1747 return false;
1748 else
1749 return true;
1750}
1751
e8e79ede
LH		 1752bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id)
1753{
1754 struct sst_module *module;
1755
1756 module = sst_module_get_from_id(hsw->dsp, module_id);
1757 if (module != NULL && module->state == SST_MODULE_STATE_ACTIVE)
1758 return true;
1759 else
1760 return false;
1761}
1762
76c07b82
LH		 1763void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1764{
1765 hsw->enabled_modules_rtd3 |= (1 << module_id);
1766}
1767
1768void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1769{
1770 hsw->enabled_modules_rtd3 &= ~(1 << module_id);
1771}
1772
1773bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1774{
1775 return hsw->enabled_modules_rtd3 & (1 << module_id);
1776}
1777
3814c204
LH		 1778void sst_hsw_reset_param_buf(struct sst_hsw *hsw)
1779{
1780 hsw->param_idx_w = 0;
1781 hsw->param_idx_r = 0;
1782 memset((void *)hsw->param_buf, 0, sizeof(hsw->param_buf));
1783}
1784
1785int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf)
1786{
1787 /* save line to the first available position of param buffer */
1788 if (hsw->param_idx_w > WAVES_PARAM_LINES - 1) {
1789 dev_warn(hsw->dev, "warning: param buffer overflow!\n");
1790 return -EPERM;
1791 }
1792 memcpy(hsw->param_buf[hsw->param_idx_w], buf, WAVES_PARAM_COUNT);
1793 hsw->param_idx_w++;
1794 return 0;
1795}
1796
1797int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf)
1798{
1799 u8 id = 0;
1800
1801 /* read the first matching line from param buffer */
1802 while (hsw->param_idx_r < WAVES_PARAM_LINES) {
1803 id = hsw->param_buf[hsw->param_idx_r][0];
1804 hsw->param_idx_r++;
1805 if (buf[0] == id) {
1806 memcpy(buf, hsw->param_buf[hsw->param_idx_r],
1807 WAVES_PARAM_COUNT);
1808 break;
1809 }
1810 }
1811 if (hsw->param_idx_r > WAVES_PARAM_LINES - 1) {
1812 dev_dbg(hsw->dev, "end of buffer, roll to the beginning\n");
1813 hsw->param_idx_r = 0;
1814 return 0;
1815 }
1816 return 0;
1817}
1818
1819int sst_hsw_launch_param_buf(struct sst_hsw *hsw)
1820{
1821 int ret, idx;
1822
5d5b275d
LH		 1823 if (!sst_hsw_is_module_active(hsw, SST_HSW_MODULE_WAVES)) {
1824 dev_dbg(hsw->dev, "module waves is not active\n");
1825 return 0;
1826 }
1827
3814c204
LH		 1828 /* put all param lines to DSP through ipc */
1829 for (idx = 0; idx < hsw->param_idx_w; idx++) {
1830 ret = sst_hsw_module_set_param(hsw,
1831 SST_HSW_MODULE_WAVES, 0, hsw->param_buf[idx][0],
1832 WAVES_PARAM_COUNT, hsw->param_buf[idx]);
1833 if (ret < 0)
1834 return ret;
1835 }
1836 return 0;
1837}
1838
9449d39b
LH		 1839int sst_hsw_module_load(struct sst_hsw *hsw,
1840 u32 module_id, u32 instance_id, char *name)
1841{
1842 int ret = 0;
1843 const struct firmware *fw = NULL;
1844 struct sst_fw *hsw_sst_fw;
1845 struct sst_module *module;
1846 struct device *dev = hsw->dev;
1847 struct sst_dsp *dsp = hsw->dsp;
1848
1849 dev_dbg(dev, "sst_hsw_module_load id=%d, name='%s'", module_id, name);
1850
1851 module = sst_module_get_from_id(dsp, module_id);
1852 if (module == NULL) {
1853 /* loading for the first time */
1854 if (module_id == SST_HSW_MODULE_BASE_FW) {
1855 /* for base module: use fw requested in acpi probe */
1856 fw = dsp->pdata->fw;
1857 if (!fw) {
1858 dev_err(dev, "request Base fw failed\n");
1859 return -ENODEV;
1860 }
1861 } else {
1862 /* try and load any other optional modules if they are
1863 * available. Use dev_info instead of dev_err in case
1864 * request firmware failed */
1865 ret = request_firmware(&fw, name, dev);
1866 if (ret) {
1867 dev_info(dev, "fw image %s not available(%d)\n",
1868 name, ret);
1869 return ret;
1870 }
1871 }
1872 hsw_sst_fw = sst_fw_new(dsp, fw, hsw);
1873 if (hsw_sst_fw == NULL) {
1874 dev_err(dev, "error: failed to load firmware\n");
1875 ret = -ENOMEM;
1876 goto out;
1877 }
1878 module = sst_module_get_from_id(dsp, module_id);
1879 if (module == NULL) {
1880 dev_err(dev, "error: no module %d in firmware %s\n",
1881 module_id, name);
1882 }
1883 } else
1884 dev_info(dev, "module %d (%s) already loaded\n",
1885 module_id, name);
1886out:
1887 /* release fw, but base fw should be released by acpi driver */
1888 if (fw && module_id != SST_HSW_MODULE_BASE_FW)
1889 release_firmware(fw);
1890
1891 return ret;
1892}
1893
e8e79ede
LH		 1894int sst_hsw_module_enable(struct sst_hsw *hsw,
1895 u32 module_id, u32 instance_id)
1896{
1897 int ret;
1898 u32 header = 0;
1899 struct sst_hsw_ipc_module_config config;
1900 struct sst_module *module;
1901 struct sst_module_runtime *runtime;
1902 struct device *dev = hsw->dev;
1903 struct sst_dsp *dsp = hsw->dsp;
1904
1905 if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1906 dev_dbg(dev, "module %d not loaded\n", module_id);
1907 return 0;
1908 }
1909
1910 if (sst_hsw_is_module_active(hsw, module_id)) {
1911 dev_info(dev, "module %d already enabled\n", module_id);
1912 return 0;
1913 }
1914
1915 module = sst_module_get_from_id(dsp, module_id);
1916 if (module == NULL) {
1917 dev_err(dev, "module %d not valid\n", module_id);
1918 return -ENXIO;
1919 }
1920
1921 runtime = sst_module_runtime_get_from_id(module, module_id);
1922 if (runtime == NULL) {
1923 dev_err(dev, "runtime %d not valid", module_id);
1924 return -ENXIO;
1925 }
1926
1927 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1928 IPC_MODULE_OPERATION(IPC_MODULE_ENABLE) |
1929 IPC_MODULE_ID(module_id);
1930 dev_dbg(dev, "module enable header: %x\n", header);
1931
1932 config.map.module_entries_count = 1;
1933 config.map.module_entries[0].module_id = module->id;
1934 config.map.module_entries[0].entry_point = module->entry;
1935
1936 config.persistent_mem.offset =
1937 sst_dsp_get_offset(dsp,
1938 runtime->persistent_offset, SST_MEM_DRAM);
1939 config.persistent_mem.size = module->persistent_size;
1940
1941 config.scratch_mem.offset =
1942 sst_dsp_get_offset(dsp,
1943 dsp->scratch_offset, SST_MEM_DRAM);
1944 config.scratch_mem.size = module->scratch_size;
1945 dev_dbg(dev, "mod %d enable p:%d @ %x, s:%d @ %x, ep: %x",
1946 config.map.module_entries[0].module_id,
1947 config.persistent_mem.size,
1948 config.persistent_mem.offset,
1949 config.scratch_mem.size, config.scratch_mem.offset,
1950 config.map.module_entries[0].entry_point);
1951
0e7921e9 1952 ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
e8e79ede
LH		 1953 &config, sizeof(config), NULL, 0);
1954 if (ret < 0)
1955 dev_err(dev, "ipc: module enable failed - %d\n", ret);
1956 else
1957 module->state = SST_MODULE_STATE_ACTIVE;
1958
1959 return ret;
1960}
1961
1962int sst_hsw_module_disable(struct sst_hsw *hsw,
1963 u32 module_id, u32 instance_id)
1964{
1965 int ret;
1966 u32 header;
1967 struct sst_module *module;
1968 struct device *dev = hsw->dev;
1969 struct sst_dsp *dsp = hsw->dsp;
1970
1971 if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1972 dev_dbg(dev, "module %d not loaded\n", module_id);
1973 return 0;
1974 }
1975
1976 if (!sst_hsw_is_module_active(hsw, module_id)) {
1977 dev_info(dev, "module %d already disabled\n", module_id);
1978 return 0;
1979 }
1980
1981 module = sst_module_get_from_id(dsp, module_id);
1982 if (module == NULL) {
1983 dev_err(dev, "module %d not valid\n", module_id);
1984 return -ENXIO;
1985 }
1986
1987 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1988 IPC_MODULE_OPERATION(IPC_MODULE_DISABLE) |
1989 IPC_MODULE_ID(module_id);
1990
0e7921e9 1991 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0, NULL, 0);
e8e79ede
LH		 1992 if (ret < 0)
1993 dev_err(dev, "module disable failed - %d\n", ret);
1994 else
1995 module->state = SST_MODULE_STATE_INITIALIZED;
1996
1997 return ret;
1998}
1999
20189226
LH		 2000int sst_hsw_module_set_param(struct sst_hsw *hsw,
2001 u32 module_id, u32 instance_id, u32 parameter_id,
2002 u32 param_size, char *param)
2003{
2004 int ret;
2005 unsigned char *data = NULL;
2006 u32 header = 0;
2007 u32 payload_size = 0, transfer_parameter_size = 0;
2008 dma_addr_t dma_addr = 0;
2009 struct sst_hsw_transfer_parameter *parameter;
2010 struct device *dev = hsw->dev;
2011
2012 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
2013 IPC_MODULE_OPERATION(IPC_MODULE_SET_PARAMETER) |
2014 IPC_MODULE_ID(module_id);
2015 dev_dbg(dev, "sst_hsw_module_set_param header=%x\n", header);
2016
2017 payload_size = param_size +
2018 sizeof(struct sst_hsw_transfer_parameter) -
2019 sizeof(struct sst_hsw_transfer_list);
2020 dev_dbg(dev, "parameter size : %d\n", param_size);
2021 dev_dbg(dev, "payload size : %d\n", payload_size);
2022
2023 if (payload_size <= SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE) {
2024 /* short parameter, mailbox can contain data */
2025 dev_dbg(dev, "transfer parameter size : %d\n",
2026 transfer_parameter_size);
2027
2028 transfer_parameter_size = ALIGN(payload_size, 4);
2029 dev_dbg(dev, "transfer parameter aligned size : %d\n",
2030 transfer_parameter_size);
2031
2032 parameter = kzalloc(transfer_parameter_size, GFP_KERNEL);
2033 if (parameter == NULL)
2034 return -ENOMEM;
2035
2036 memcpy(parameter->data, param, param_size);
2037 } else {
2038 dev_warn(dev, "transfer parameter size too large!");
2039 return 0;
2040 }
2041
2042 parameter->parameter_id = parameter_id;
2043 parameter->data_size = param_size;
2044
0e7921e9 2045 ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
20189226
LH		 2046 parameter, transfer_parameter_size , NULL, 0);
2047 if (ret < 0)
2048 dev_err(dev, "ipc: module set parameter failed - %d\n", ret);
2049
2050 kfree(parameter);
2051
2052 if (data)
2053 dma_free_coherent(hsw->dsp->dma_dev,
2054 param_size, (void *)data, dma_addr);
2055
2056 return ret;
2057}
2058
a4b12990
MB		 2059static struct sst_dsp_device hsw_dev = {
2060 .thread = hsw_irq_thread,
2061 .ops = &haswell_ops,
2062};
2063
0e7921e9
JY		 2064static void hsw_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
2065{
2066 /* send the message */
2067 sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
2068 sst_dsp_ipc_msg_tx(ipc->dsp, msg->header);
2069}
2070
2071static void hsw_shim_dbg(struct sst_generic_ipc *ipc, const char *text)
2072{
2073 struct sst_dsp *sst = ipc->dsp;
2074 u32 isr, ipcd, imrx, ipcx;
2075
2076 ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
2077 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
2078 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
2079 imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
2080
2081 dev_err(ipc->dev,
2082 "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
2083 text, ipcx, isr, ipcd, imrx);
2084}
2085
2086static void hsw_tx_data_copy(struct ipc_message *msg, char *tx_data,
2087 size_t tx_size)
2088{
2089 memcpy(msg->tx_data, tx_data, tx_size);
2090}
2091
2092static u64 hsw_reply_msg_match(u64 header, u64 *mask)
2093{
2094 /* clear reply bits & status bits */
2095 header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
2096 *mask = (u64)-1;
2097
2098 return header;
2099}
2100
a4b12990
MB		 2101int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
2102{
2103 struct sst_hsw_ipc_fw_version version;
2104 struct sst_hsw *hsw;
0e7921e9 2105 struct sst_generic_ipc *ipc;
a4b12990
MB		 2106 int ret;
2107
2108 dev_dbg(dev, "initialising Audio DSP IPC\n");
2109
2110 hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
2111 if (hsw == NULL)
2112 return -ENOMEM;
2113
0e7921e9
JY		 2114 ipc = &hsw->ipc;
2115 ipc->dev = dev;
2116 ipc->ops.tx_msg = hsw_tx_msg;
2117 ipc->ops.shim_dbg = hsw_shim_dbg;
2118 ipc->ops.tx_data_copy = hsw_tx_data_copy;
2119 ipc->ops.reply_msg_match = hsw_reply_msg_match;
a4b12990 2120
0e7921e9
JY		 2121 ret = sst_ipc_init(ipc);
2122 if (ret != 0)
2123 goto ipc_init_err;
a4b12990 2124
0e7921e9
JY		 2125 INIT_LIST_HEAD(&hsw->stream_list);
2126 init_waitqueue_head(&hsw->boot_wait);
a4b12990
MB		 2127 hsw_dev.thread_context = hsw;
2128
2129 /* init SST shim */
2130 hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
2131 if (hsw->dsp == NULL) {
2132 ret = -ENODEV;
0e7921e9 2133 goto dsp_new_err;
a4b12990
MB		 2134 }
2135
0e7921e9
JY		 2136 ipc->dsp = hsw->dsp;
2137
aed3c7b7
LG		 2138 /* allocate DMA buffer for context storage */
2139 hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev,
2140 SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL);
2141 if (hsw->dx_context == NULL) {
2142 ret = -ENOMEM;
2143 goto dma_err;
2144 }
2145
a4b12990
MB		 2146 /* keep the DSP in reset state for base FW loading */
2147 sst_dsp_reset(hsw->dsp);
2148
9449d39b
LH		 2149 /* load base module and other modules in base firmware image */
2150 ret = sst_hsw_module_load(hsw, SST_HSW_MODULE_BASE_FW, 0, "Base");
2151 if (ret < 0)
a4b12990 2152 goto fw_err;
a4b12990 2153
8c43fc2f
LH		 2154 /* try to load module waves */
2155 sst_hsw_module_load(hsw, SST_HSW_MODULE_WAVES, 0, "intel/IntcPP01.bin");
2156
3fe0607a
LH		 2157 /* allocate scratch mem regions */
2158 ret = sst_block_alloc_scratch(hsw->dsp);
2159 if (ret < 0)
2160 goto boot_err;
2161
3814c204
LH		 2162 /* init param buffer */
2163 sst_hsw_reset_param_buf(hsw);
2164
a4b12990
MB		 2165 /* wait for DSP boot completion */
2166 sst_dsp_boot(hsw->dsp);
2167 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
2168 msecs_to_jiffies(IPC_BOOT_MSECS));
2169 if (ret == 0) {
2170 ret = -EIO;
b891f62f
LG		 2171 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
2172 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
2173 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
a4b12990
MB		 2174 goto boot_err;
2175 }
2176
9449d39b
LH		 2177 /* init module state after boot */
2178 sst_hsw_init_module_state(hsw);
2179
a4b12990
MB		 2180 /* get the FW version */
2181 sst_hsw_fw_get_version(hsw, &version);
a4b12990
MB		 2182
2183 /* get the globalmixer */
2184 ret = sst_hsw_mixer_get_info(hsw);
2185 if (ret < 0) {
2186 dev_err(hsw->dev, "error: failed to get stream info\n");
2187 goto boot_err;
2188 }
2189
2190 pdata->dsp = hsw;
2191 return 0;
2192
2193boot_err:
2194 sst_dsp_reset(hsw->dsp);
9449d39b 2195 sst_fw_free_all(hsw->dsp);
a4b12990 2196fw_err:
aed3c7b7
LG		 2197 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2198 hsw->dx_context, hsw->dx_context_paddr);
2199dma_err:
a4b12990 2200 sst_dsp_free(hsw->dsp);
0e7921e9
JY		 2201dsp_new_err:
2202 sst_ipc_fini(ipc);
2203ipc_init_err:
a4b12990
MB		 2204 return ret;
2205}
2206EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
2207
2208void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
2209{
2210 struct sst_hsw *hsw = pdata->dsp;
2211
2212 sst_dsp_reset(hsw->dsp);
2213 sst_fw_free_all(hsw->dsp);
aed3c7b7
LG		 2214 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2215 hsw->dx_context, hsw->dx_context_paddr);
a4b12990 2216 sst_dsp_free(hsw->dsp);
0e7921e9 2217 sst_ipc_fini(&hsw->ipc);
a4b12990
MB		 2218}
2219EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);
Linux 6.x block layer and io_uring tree(s)