Merge tag 'v4.1-rockchip-socfixes1' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / lib / atomic64.c
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1/*
2 * Generic implementation of 64-bit atomics using spinlocks,
3 * useful on processors that don't have 64-bit atomic instructions.
4 *
5 * Copyright © 2009 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#include <linux/types.h>
13#include <linux/cache.h>
14#include <linux/spinlock.h>
15#include <linux/init.h>
8bc3bcc9 16#include <linux/export.h>
60063497 17#include <linux/atomic.h>
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18
19/*
20 * We use a hashed array of spinlocks to provide exclusive access
21 * to each atomic64_t variable. Since this is expected to used on
22 * systems with small numbers of CPUs (<= 4 or so), we use a
23 * relatively small array of 16 spinlocks to avoid wasting too much
24 * memory on the spinlock array.
25 */
26#define NR_LOCKS 16
27
28/*
29 * Ensure each lock is in a separate cacheline.
30 */
31static union {
f59ca058 32 raw_spinlock_t lock;
09d4e0ed 33 char pad[L1_CACHE_BYTES];
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34} atomic64_lock[NR_LOCKS] __cacheline_aligned_in_smp = {
35 [0 ... (NR_LOCKS - 1)] = {
36 .lock = __RAW_SPIN_LOCK_UNLOCKED(atomic64_lock.lock),
37 },
38};
09d4e0ed 39
cb475de3 40static inline raw_spinlock_t *lock_addr(const atomic64_t *v)
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41{
42 unsigned long addr = (unsigned long) v;
43
44 addr >>= L1_CACHE_SHIFT;
45 addr ^= (addr >> 8) ^ (addr >> 16);
46 return &atomic64_lock[addr & (NR_LOCKS - 1)].lock;
47}
48
49long long atomic64_read(const atomic64_t *v)
50{
51 unsigned long flags;
cb475de3 52 raw_spinlock_t *lock = lock_addr(v);
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53 long long val;
54
f59ca058 55 raw_spin_lock_irqsave(lock, flags);
09d4e0ed 56 val = v->counter;
f59ca058 57 raw_spin_unlock_irqrestore(lock, flags);
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58 return val;
59}
3fc7b4b2 60EXPORT_SYMBOL(atomic64_read);
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61
62void atomic64_set(atomic64_t *v, long long i)
63{
64 unsigned long flags;
cb475de3 65 raw_spinlock_t *lock = lock_addr(v);
09d4e0ed 66
f59ca058 67 raw_spin_lock_irqsave(lock, flags);
09d4e0ed 68 v->counter = i;
f59ca058 69 raw_spin_unlock_irqrestore(lock, flags);
09d4e0ed 70}
3fc7b4b2 71EXPORT_SYMBOL(atomic64_set);
09d4e0ed 72
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73#define ATOMIC64_OP(op, c_op) \
74void atomic64_##op(long long a, atomic64_t *v) \
75{ \
76 unsigned long flags; \
77 raw_spinlock_t *lock = lock_addr(v); \
78 \
79 raw_spin_lock_irqsave(lock, flags); \
80 v->counter c_op a; \
81 raw_spin_unlock_irqrestore(lock, flags); \
82} \
83EXPORT_SYMBOL(atomic64_##op);
84
85#define ATOMIC64_OP_RETURN(op, c_op) \
86long long atomic64_##op##_return(long long a, atomic64_t *v) \
87{ \
88 unsigned long flags; \
89 raw_spinlock_t *lock = lock_addr(v); \
90 long long val; \
91 \
92 raw_spin_lock_irqsave(lock, flags); \
93 val = (v->counter c_op a); \
94 raw_spin_unlock_irqrestore(lock, flags); \
95 return val; \
96} \
97EXPORT_SYMBOL(atomic64_##op##_return);
98
99#define ATOMIC64_OPS(op, c_op) \
100 ATOMIC64_OP(op, c_op) \
101 ATOMIC64_OP_RETURN(op, c_op)
102
103ATOMIC64_OPS(add, +=)
104ATOMIC64_OPS(sub, -=)
105
106#undef ATOMIC64_OPS
107#undef ATOMIC64_OP_RETURN
108#undef ATOMIC64_OP
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109
110long long atomic64_dec_if_positive(atomic64_t *v)
111{
112 unsigned long flags;
cb475de3 113 raw_spinlock_t *lock = lock_addr(v);
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114 long long val;
115
f59ca058 116 raw_spin_lock_irqsave(lock, flags);
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117 val = v->counter - 1;
118 if (val >= 0)
119 v->counter = val;
f59ca058 120 raw_spin_unlock_irqrestore(lock, flags);
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121 return val;
122}
3fc7b4b2 123EXPORT_SYMBOL(atomic64_dec_if_positive);
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124
125long long atomic64_cmpxchg(atomic64_t *v, long long o, long long n)
126{
127 unsigned long flags;
cb475de3 128 raw_spinlock_t *lock = lock_addr(v);
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129 long long val;
130
f59ca058 131 raw_spin_lock_irqsave(lock, flags);
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132 val = v->counter;
133 if (val == o)
134 v->counter = n;
f59ca058 135 raw_spin_unlock_irqrestore(lock, flags);
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136 return val;
137}
3fc7b4b2 138EXPORT_SYMBOL(atomic64_cmpxchg);
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139
140long long atomic64_xchg(atomic64_t *v, long long new)
141{
142 unsigned long flags;
cb475de3 143 raw_spinlock_t *lock = lock_addr(v);
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144 long long val;
145
f59ca058 146 raw_spin_lock_irqsave(lock, flags);
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147 val = v->counter;
148 v->counter = new;
f59ca058 149 raw_spin_unlock_irqrestore(lock, flags);
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150 return val;
151}
3fc7b4b2 152EXPORT_SYMBOL(atomic64_xchg);
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153
154int atomic64_add_unless(atomic64_t *v, long long a, long long u)
155{
156 unsigned long flags;
cb475de3 157 raw_spinlock_t *lock = lock_addr(v);
97577896 158 int ret = 0;
09d4e0ed 159
f59ca058 160 raw_spin_lock_irqsave(lock, flags);
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161 if (v->counter != u) {
162 v->counter += a;
97577896 163 ret = 1;
09d4e0ed 164 }
f59ca058 165 raw_spin_unlock_irqrestore(lock, flags);
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166 return ret;
167}
3fc7b4b2 168EXPORT_SYMBOL(atomic64_add_unless);