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607ca46e DH |
1 | /* |
2 | * Performance events: | |
3 | * | |
4 | * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra | |
7 | * | |
8 | * Data type definitions, declarations, prototypes. | |
9 | * | |
10 | * Started by: Thomas Gleixner and Ingo Molnar | |
11 | * | |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | #ifndef _UAPI_LINUX_PERF_EVENT_H | |
15 | #define _UAPI_LINUX_PERF_EVENT_H | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/ioctl.h> | |
19 | #include <asm/byteorder.h> | |
20 | ||
21 | /* | |
22 | * User-space ABI bits: | |
23 | */ | |
24 | ||
25 | /* | |
26 | * attr.type | |
27 | */ | |
28 | enum perf_type_id { | |
29 | PERF_TYPE_HARDWARE = 0, | |
30 | PERF_TYPE_SOFTWARE = 1, | |
31 | PERF_TYPE_TRACEPOINT = 2, | |
32 | PERF_TYPE_HW_CACHE = 3, | |
33 | PERF_TYPE_RAW = 4, | |
34 | PERF_TYPE_BREAKPOINT = 5, | |
35 | ||
36 | PERF_TYPE_MAX, /* non-ABI */ | |
37 | }; | |
38 | ||
39 | /* | |
40 | * Generalized performance event event_id types, used by the | |
41 | * attr.event_id parameter of the sys_perf_event_open() | |
42 | * syscall: | |
43 | */ | |
44 | enum perf_hw_id { | |
45 | /* | |
46 | * Common hardware events, generalized by the kernel: | |
47 | */ | |
48 | PERF_COUNT_HW_CPU_CYCLES = 0, | |
49 | PERF_COUNT_HW_INSTRUCTIONS = 1, | |
50 | PERF_COUNT_HW_CACHE_REFERENCES = 2, | |
51 | PERF_COUNT_HW_CACHE_MISSES = 3, | |
52 | PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, | |
53 | PERF_COUNT_HW_BRANCH_MISSES = 5, | |
54 | PERF_COUNT_HW_BUS_CYCLES = 6, | |
55 | PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, | |
56 | PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, | |
57 | PERF_COUNT_HW_REF_CPU_CYCLES = 9, | |
58 | ||
59 | PERF_COUNT_HW_MAX, /* non-ABI */ | |
60 | }; | |
61 | ||
62 | /* | |
63 | * Generalized hardware cache events: | |
64 | * | |
65 | * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x | |
66 | * { read, write, prefetch } x | |
67 | * { accesses, misses } | |
68 | */ | |
69 | enum perf_hw_cache_id { | |
70 | PERF_COUNT_HW_CACHE_L1D = 0, | |
71 | PERF_COUNT_HW_CACHE_L1I = 1, | |
72 | PERF_COUNT_HW_CACHE_LL = 2, | |
73 | PERF_COUNT_HW_CACHE_DTLB = 3, | |
74 | PERF_COUNT_HW_CACHE_ITLB = 4, | |
75 | PERF_COUNT_HW_CACHE_BPU = 5, | |
76 | PERF_COUNT_HW_CACHE_NODE = 6, | |
77 | ||
78 | PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ | |
79 | }; | |
80 | ||
81 | enum perf_hw_cache_op_id { | |
82 | PERF_COUNT_HW_CACHE_OP_READ = 0, | |
83 | PERF_COUNT_HW_CACHE_OP_WRITE = 1, | |
84 | PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, | |
85 | ||
86 | PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ | |
87 | }; | |
88 | ||
89 | enum perf_hw_cache_op_result_id { | |
90 | PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, | |
91 | PERF_COUNT_HW_CACHE_RESULT_MISS = 1, | |
92 | ||
93 | PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ | |
94 | }; | |
95 | ||
96 | /* | |
97 | * Special "software" events provided by the kernel, even if the hardware | |
98 | * does not support performance events. These events measure various | |
99 | * physical and sw events of the kernel (and allow the profiling of them as | |
100 | * well): | |
101 | */ | |
102 | enum perf_sw_ids { | |
103 | PERF_COUNT_SW_CPU_CLOCK = 0, | |
104 | PERF_COUNT_SW_TASK_CLOCK = 1, | |
105 | PERF_COUNT_SW_PAGE_FAULTS = 2, | |
106 | PERF_COUNT_SW_CONTEXT_SWITCHES = 3, | |
107 | PERF_COUNT_SW_CPU_MIGRATIONS = 4, | |
108 | PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, | |
109 | PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, | |
110 | PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, | |
111 | PERF_COUNT_SW_EMULATION_FAULTS = 8, | |
fa0097ee | 112 | PERF_COUNT_SW_DUMMY = 9, |
607ca46e DH |
113 | |
114 | PERF_COUNT_SW_MAX, /* non-ABI */ | |
115 | }; | |
116 | ||
117 | /* | |
118 | * Bits that can be set in attr.sample_type to request information | |
119 | * in the overflow packets. | |
120 | */ | |
121 | enum perf_event_sample_format { | |
122 | PERF_SAMPLE_IP = 1U << 0, | |
123 | PERF_SAMPLE_TID = 1U << 1, | |
124 | PERF_SAMPLE_TIME = 1U << 2, | |
125 | PERF_SAMPLE_ADDR = 1U << 3, | |
126 | PERF_SAMPLE_READ = 1U << 4, | |
127 | PERF_SAMPLE_CALLCHAIN = 1U << 5, | |
128 | PERF_SAMPLE_ID = 1U << 6, | |
129 | PERF_SAMPLE_CPU = 1U << 7, | |
130 | PERF_SAMPLE_PERIOD = 1U << 8, | |
131 | PERF_SAMPLE_STREAM_ID = 1U << 9, | |
132 | PERF_SAMPLE_RAW = 1U << 10, | |
133 | PERF_SAMPLE_BRANCH_STACK = 1U << 11, | |
134 | PERF_SAMPLE_REGS_USER = 1U << 12, | |
135 | PERF_SAMPLE_STACK_USER = 1U << 13, | |
c3feedf2 | 136 | PERF_SAMPLE_WEIGHT = 1U << 14, |
d6be9ad6 | 137 | PERF_SAMPLE_DATA_SRC = 1U << 15, |
ff3d527c | 138 | PERF_SAMPLE_IDENTIFIER = 1U << 16, |
fdfbbd07 | 139 | PERF_SAMPLE_TRANSACTION = 1U << 17, |
60e2364e | 140 | PERF_SAMPLE_REGS_INTR = 1U << 18, |
c3feedf2 | 141 | |
60e2364e | 142 | PERF_SAMPLE_MAX = 1U << 19, /* non-ABI */ |
607ca46e DH |
143 | }; |
144 | ||
145 | /* | |
146 | * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set | |
147 | * | |
148 | * If the user does not pass priv level information via branch_sample_type, | |
149 | * the kernel uses the event's priv level. Branch and event priv levels do | |
150 | * not have to match. Branch priv level is checked for permissions. | |
151 | * | |
152 | * The branch types can be combined, however BRANCH_ANY covers all types | |
153 | * of branches and therefore it supersedes all the other types. | |
154 | */ | |
27ac905b YZ |
155 | enum perf_branch_sample_type_shift { |
156 | PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ | |
157 | PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ | |
158 | PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ | |
159 | ||
160 | PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ | |
161 | PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ | |
162 | PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ | |
163 | PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ | |
164 | PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ | |
165 | PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ | |
166 | PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ | |
167 | PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ | |
168 | ||
2c44b193 | 169 | PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ |
c9fdfa14 | 170 | PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ |
2c44b193 | 171 | |
27ac905b YZ |
172 | PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ |
173 | }; | |
174 | ||
607ca46e | 175 | enum perf_branch_sample_type { |
27ac905b YZ |
176 | PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, |
177 | PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, | |
178 | PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, | |
179 | ||
180 | PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, | |
2c44b193 PZ |
181 | PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, |
182 | PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, | |
183 | PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, | |
184 | PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, | |
27ac905b YZ |
185 | PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, |
186 | PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, | |
187 | PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, | |
188 | ||
2c44b193 | 189 | PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, |
c9fdfa14 | 190 | PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, |
2c44b193 | 191 | |
27ac905b | 192 | PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, |
607ca46e DH |
193 | }; |
194 | ||
195 | #define PERF_SAMPLE_BRANCH_PLM_ALL \ | |
196 | (PERF_SAMPLE_BRANCH_USER|\ | |
197 | PERF_SAMPLE_BRANCH_KERNEL|\ | |
198 | PERF_SAMPLE_BRANCH_HV) | |
199 | ||
200 | /* | |
201 | * Values to determine ABI of the registers dump. | |
202 | */ | |
203 | enum perf_sample_regs_abi { | |
204 | PERF_SAMPLE_REGS_ABI_NONE = 0, | |
205 | PERF_SAMPLE_REGS_ABI_32 = 1, | |
206 | PERF_SAMPLE_REGS_ABI_64 = 2, | |
207 | }; | |
208 | ||
fdfbbd07 AK |
209 | /* |
210 | * Values for the memory transaction event qualifier, mostly for | |
211 | * abort events. Multiple bits can be set. | |
212 | */ | |
213 | enum { | |
214 | PERF_TXN_ELISION = (1 << 0), /* From elision */ | |
215 | PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ | |
216 | PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ | |
217 | PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ | |
218 | PERF_TXN_RETRY = (1 << 4), /* Retry possible */ | |
219 | PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ | |
220 | PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ | |
221 | PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ | |
222 | ||
223 | PERF_TXN_MAX = (1 << 8), /* non-ABI */ | |
224 | ||
225 | /* bits 32..63 are reserved for the abort code */ | |
226 | ||
227 | PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), | |
228 | PERF_TXN_ABORT_SHIFT = 32, | |
229 | }; | |
230 | ||
607ca46e DH |
231 | /* |
232 | * The format of the data returned by read() on a perf event fd, | |
233 | * as specified by attr.read_format: | |
234 | * | |
235 | * struct read_format { | |
236 | * { u64 value; | |
237 | * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED | |
238 | * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING | |
239 | * { u64 id; } && PERF_FORMAT_ID | |
240 | * } && !PERF_FORMAT_GROUP | |
241 | * | |
242 | * { u64 nr; | |
243 | * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED | |
244 | * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING | |
245 | * { u64 value; | |
246 | * { u64 id; } && PERF_FORMAT_ID | |
247 | * } cntr[nr]; | |
248 | * } && PERF_FORMAT_GROUP | |
249 | * }; | |
250 | */ | |
251 | enum perf_event_read_format { | |
252 | PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, | |
253 | PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, | |
254 | PERF_FORMAT_ID = 1U << 2, | |
255 | PERF_FORMAT_GROUP = 1U << 3, | |
256 | ||
257 | PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ | |
258 | }; | |
259 | ||
260 | #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ | |
261 | #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ | |
262 | #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ | |
263 | #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ | |
264 | /* add: sample_stack_user */ | |
60e2364e | 265 | #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ |
1a594131 | 266 | #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ |
607ca46e DH |
267 | |
268 | /* | |
269 | * Hardware event_id to monitor via a performance monitoring event: | |
270 | */ | |
271 | struct perf_event_attr { | |
272 | ||
273 | /* | |
274 | * Major type: hardware/software/tracepoint/etc. | |
275 | */ | |
276 | __u32 type; | |
277 | ||
278 | /* | |
279 | * Size of the attr structure, for fwd/bwd compat. | |
280 | */ | |
281 | __u32 size; | |
282 | ||
283 | /* | |
284 | * Type specific configuration information. | |
285 | */ | |
286 | __u64 config; | |
287 | ||
288 | union { | |
289 | __u64 sample_period; | |
290 | __u64 sample_freq; | |
291 | }; | |
292 | ||
293 | __u64 sample_type; | |
294 | __u64 read_format; | |
295 | ||
296 | __u64 disabled : 1, /* off by default */ | |
297 | inherit : 1, /* children inherit it */ | |
298 | pinned : 1, /* must always be on PMU */ | |
299 | exclusive : 1, /* only group on PMU */ | |
300 | exclude_user : 1, /* don't count user */ | |
301 | exclude_kernel : 1, /* ditto kernel */ | |
302 | exclude_hv : 1, /* ditto hypervisor */ | |
303 | exclude_idle : 1, /* don't count when idle */ | |
304 | mmap : 1, /* include mmap data */ | |
305 | comm : 1, /* include comm data */ | |
306 | freq : 1, /* use freq, not period */ | |
307 | inherit_stat : 1, /* per task counts */ | |
308 | enable_on_exec : 1, /* next exec enables */ | |
309 | task : 1, /* trace fork/exit */ | |
310 | watermark : 1, /* wakeup_watermark */ | |
311 | /* | |
312 | * precise_ip: | |
313 | * | |
314 | * 0 - SAMPLE_IP can have arbitrary skid | |
315 | * 1 - SAMPLE_IP must have constant skid | |
316 | * 2 - SAMPLE_IP requested to have 0 skid | |
317 | * 3 - SAMPLE_IP must have 0 skid | |
318 | * | |
319 | * See also PERF_RECORD_MISC_EXACT_IP | |
320 | */ | |
321 | precise_ip : 2, /* skid constraint */ | |
322 | mmap_data : 1, /* non-exec mmap data */ | |
323 | sample_id_all : 1, /* sample_type all events */ | |
324 | ||
325 | exclude_host : 1, /* don't count in host */ | |
326 | exclude_guest : 1, /* don't count in guest */ | |
327 | ||
328 | exclude_callchain_kernel : 1, /* exclude kernel callchains */ | |
329 | exclude_callchain_user : 1, /* exclude user callchains */ | |
13d7a241 | 330 | mmap2 : 1, /* include mmap with inode data */ |
82b89778 | 331 | comm_exec : 1, /* flag comm events that are due to an exec */ |
34f43927 PZ |
332 | use_clockid : 1, /* use @clockid for time fields */ |
333 | __reserved_1 : 38; | |
607ca46e DH |
334 | |
335 | union { | |
336 | __u32 wakeup_events; /* wakeup every n events */ | |
337 | __u32 wakeup_watermark; /* bytes before wakeup */ | |
338 | }; | |
339 | ||
340 | __u32 bp_type; | |
341 | union { | |
342 | __u64 bp_addr; | |
343 | __u64 config1; /* extension of config */ | |
344 | }; | |
345 | union { | |
346 | __u64 bp_len; | |
347 | __u64 config2; /* extension of config1 */ | |
348 | }; | |
349 | __u64 branch_sample_type; /* enum perf_branch_sample_type */ | |
350 | ||
351 | /* | |
352 | * Defines set of user regs to dump on samples. | |
353 | * See asm/perf_regs.h for details. | |
354 | */ | |
355 | __u64 sample_regs_user; | |
356 | ||
357 | /* | |
358 | * Defines size of the user stack to dump on samples. | |
359 | */ | |
360 | __u32 sample_stack_user; | |
361 | ||
34f43927 | 362 | __s32 clockid; |
60e2364e SE |
363 | /* |
364 | * Defines set of regs to dump for each sample | |
365 | * state captured on: | |
366 | * - precise = 0: PMU interrupt | |
367 | * - precise > 0: sampled instruction | |
368 | * | |
369 | * See asm/perf_regs.h for details. | |
370 | */ | |
371 | __u64 sample_regs_intr; | |
1a594131 AS |
372 | |
373 | /* | |
374 | * Wakeup watermark for AUX area | |
375 | */ | |
376 | __u32 aux_watermark; | |
377 | __u32 __reserved_2; /* align to __u64 */ | |
607ca46e DH |
378 | }; |
379 | ||
380 | #define perf_flags(attr) (*(&(attr)->read_format + 1)) | |
381 | ||
382 | /* | |
383 | * Ioctls that can be done on a perf event fd: | |
384 | */ | |
385 | #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) | |
386 | #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) | |
387 | #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) | |
388 | #define PERF_EVENT_IOC_RESET _IO ('$', 3) | |
389 | #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) | |
390 | #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) | |
391 | #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) | |
a8e0108c | 392 | #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) |
2541517c | 393 | #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) |
607ca46e DH |
394 | |
395 | enum perf_event_ioc_flags { | |
396 | PERF_IOC_FLAG_GROUP = 1U << 0, | |
397 | }; | |
398 | ||
399 | /* | |
400 | * Structure of the page that can be mapped via mmap | |
401 | */ | |
402 | struct perf_event_mmap_page { | |
403 | __u32 version; /* version number of this structure */ | |
404 | __u32 compat_version; /* lowest version this is compat with */ | |
405 | ||
406 | /* | |
407 | * Bits needed to read the hw events in user-space. | |
408 | * | |
b438b1ab | 409 | * u32 seq, time_mult, time_shift, index, width; |
607ca46e DH |
410 | * u64 count, enabled, running; |
411 | * u64 cyc, time_offset; | |
412 | * s64 pmc = 0; | |
413 | * | |
414 | * do { | |
415 | * seq = pc->lock; | |
416 | * barrier() | |
417 | * | |
418 | * enabled = pc->time_enabled; | |
419 | * running = pc->time_running; | |
420 | * | |
421 | * if (pc->cap_usr_time && enabled != running) { | |
422 | * cyc = rdtsc(); | |
423 | * time_offset = pc->time_offset; | |
424 | * time_mult = pc->time_mult; | |
425 | * time_shift = pc->time_shift; | |
426 | * } | |
427 | * | |
b438b1ab | 428 | * index = pc->index; |
607ca46e | 429 | * count = pc->offset; |
b438b1ab | 430 | * if (pc->cap_user_rdpmc && index) { |
607ca46e | 431 | * width = pc->pmc_width; |
b438b1ab | 432 | * pmc = rdpmc(index - 1); |
607ca46e DH |
433 | * } |
434 | * | |
435 | * barrier(); | |
436 | * } while (pc->lock != seq); | |
437 | * | |
438 | * NOTE: for obvious reason this only works on self-monitoring | |
439 | * processes. | |
440 | */ | |
441 | __u32 lock; /* seqlock for synchronization */ | |
442 | __u32 index; /* hardware event identifier */ | |
443 | __s64 offset; /* add to hardware event value */ | |
444 | __u64 time_enabled; /* time event active */ | |
445 | __u64 time_running; /* time event on cpu */ | |
446 | union { | |
447 | __u64 capabilities; | |
860f085b | 448 | struct { |
fa731587 PZ |
449 | __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ |
450 | cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ | |
451 | ||
452 | cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ | |
453 | cap_user_time : 1, /* The time_* fields are used */ | |
454 | cap_user_time_zero : 1, /* The time_zero field is used */ | |
455 | cap_____res : 59; | |
860f085b | 456 | }; |
607ca46e DH |
457 | }; |
458 | ||
459 | /* | |
b438b1ab | 460 | * If cap_user_rdpmc this field provides the bit-width of the value |
607ca46e DH |
461 | * read using the rdpmc() or equivalent instruction. This can be used |
462 | * to sign extend the result like: | |
463 | * | |
464 | * pmc <<= 64 - width; | |
465 | * pmc >>= 64 - width; // signed shift right | |
466 | * count += pmc; | |
467 | */ | |
468 | __u16 pmc_width; | |
469 | ||
470 | /* | |
471 | * If cap_usr_time the below fields can be used to compute the time | |
472 | * delta since time_enabled (in ns) using rdtsc or similar. | |
473 | * | |
474 | * u64 quot, rem; | |
475 | * u64 delta; | |
476 | * | |
477 | * quot = (cyc >> time_shift); | |
478 | * rem = cyc & ((1 << time_shift) - 1); | |
479 | * delta = time_offset + quot * time_mult + | |
480 | * ((rem * time_mult) >> time_shift); | |
481 | * | |
482 | * Where time_offset,time_mult,time_shift and cyc are read in the | |
483 | * seqcount loop described above. This delta can then be added to | |
b438b1ab | 484 | * enabled and possible running (if index), improving the scaling: |
607ca46e DH |
485 | * |
486 | * enabled += delta; | |
b438b1ab | 487 | * if (index) |
607ca46e DH |
488 | * running += delta; |
489 | * | |
490 | * quot = count / running; | |
491 | * rem = count % running; | |
492 | * count = quot * enabled + (rem * enabled) / running; | |
493 | */ | |
494 | __u16 time_shift; | |
495 | __u32 time_mult; | |
496 | __u64 time_offset; | |
c73deb6a AH |
497 | /* |
498 | * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated | |
499 | * from sample timestamps. | |
500 | * | |
501 | * time = timestamp - time_zero; | |
502 | * quot = time / time_mult; | |
503 | * rem = time % time_mult; | |
504 | * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; | |
505 | * | |
506 | * And vice versa: | |
507 | * | |
508 | * quot = cyc >> time_shift; | |
509 | * rem = cyc & ((1 << time_shift) - 1); | |
510 | * timestamp = time_zero + quot * time_mult + | |
511 | * ((rem * time_mult) >> time_shift); | |
512 | */ | |
513 | __u64 time_zero; | |
fa731587 | 514 | __u32 size; /* Header size up to __reserved[] fields. */ |
607ca46e DH |
515 | |
516 | /* | |
517 | * Hole for extension of the self monitor capabilities | |
518 | */ | |
519 | ||
fa731587 | 520 | __u8 __reserved[118*8+4]; /* align to 1k. */ |
607ca46e DH |
521 | |
522 | /* | |
523 | * Control data for the mmap() data buffer. | |
524 | * | |
bf378d34 PZ |
525 | * User-space reading the @data_head value should issue an smp_rmb(), |
526 | * after reading this value. | |
607ca46e DH |
527 | * |
528 | * When the mapping is PROT_WRITE the @data_tail value should be | |
bf378d34 PZ |
529 | * written by userspace to reflect the last read data, after issueing |
530 | * an smp_mb() to separate the data read from the ->data_tail store. | |
531 | * In this case the kernel will not over-write unread data. | |
532 | * | |
533 | * See perf_output_put_handle() for the data ordering. | |
e8c6deac AS |
534 | * |
535 | * data_{offset,size} indicate the location and size of the perf record | |
536 | * buffer within the mmapped area. | |
607ca46e DH |
537 | */ |
538 | __u64 data_head; /* head in the data section */ | |
539 | __u64 data_tail; /* user-space written tail */ | |
e8c6deac AS |
540 | __u64 data_offset; /* where the buffer starts */ |
541 | __u64 data_size; /* data buffer size */ | |
45bfb2e5 PZ |
542 | |
543 | /* | |
544 | * AUX area is defined by aux_{offset,size} fields that should be set | |
545 | * by the userspace, so that | |
546 | * | |
547 | * aux_offset >= data_offset + data_size | |
548 | * | |
549 | * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. | |
550 | * | |
551 | * Ring buffer pointers aux_{head,tail} have the same semantics as | |
552 | * data_{head,tail} and same ordering rules apply. | |
553 | */ | |
554 | __u64 aux_head; | |
555 | __u64 aux_tail; | |
556 | __u64 aux_offset; | |
557 | __u64 aux_size; | |
607ca46e DH |
558 | }; |
559 | ||
560 | #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) | |
561 | #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) | |
562 | #define PERF_RECORD_MISC_KERNEL (1 << 0) | |
563 | #define PERF_RECORD_MISC_USER (2 << 0) | |
564 | #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) | |
565 | #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) | |
566 | #define PERF_RECORD_MISC_GUEST_USER (5 << 0) | |
567 | ||
82b89778 AH |
568 | /* |
569 | * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on | |
570 | * different events so can reuse the same bit position. | |
571 | */ | |
2fe85427 | 572 | #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) |
82b89778 | 573 | #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) |
607ca46e DH |
574 | /* |
575 | * Indicates that the content of PERF_SAMPLE_IP points to | |
576 | * the actual instruction that triggered the event. See also | |
577 | * perf_event_attr::precise_ip. | |
578 | */ | |
579 | #define PERF_RECORD_MISC_EXACT_IP (1 << 14) | |
580 | /* | |
581 | * Reserve the last bit to indicate some extended misc field | |
582 | */ | |
583 | #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) | |
584 | ||
585 | struct perf_event_header { | |
586 | __u32 type; | |
587 | __u16 misc; | |
588 | __u16 size; | |
589 | }; | |
590 | ||
591 | enum perf_event_type { | |
592 | ||
593 | /* | |
594 | * If perf_event_attr.sample_id_all is set then all event types will | |
595 | * have the sample_type selected fields related to where/when | |
ff3d527c AH |
596 | * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, |
597 | * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed | |
598 | * just after the perf_event_header and the fields already present for | |
599 | * the existing fields, i.e. at the end of the payload. That way a newer | |
600 | * perf.data file will be supported by older perf tools, with these new | |
601 | * optional fields being ignored. | |
607ca46e | 602 | * |
a5cdd40c PZ |
603 | * struct sample_id { |
604 | * { u32 pid, tid; } && PERF_SAMPLE_TID | |
605 | * { u64 time; } && PERF_SAMPLE_TIME | |
606 | * { u64 id; } && PERF_SAMPLE_ID | |
607 | * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID | |
608 | * { u32 cpu, res; } && PERF_SAMPLE_CPU | |
ff3d527c | 609 | * { u64 id; } && PERF_SAMPLE_IDENTIFIER |
a5cdd40c | 610 | * } && perf_event_attr::sample_id_all |
ff3d527c AH |
611 | * |
612 | * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The | |
613 | * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed | |
614 | * relative to header.size. | |
a5cdd40c PZ |
615 | */ |
616 | ||
617 | /* | |
607ca46e DH |
618 | * The MMAP events record the PROT_EXEC mappings so that we can |
619 | * correlate userspace IPs to code. They have the following structure: | |
620 | * | |
621 | * struct { | |
622 | * struct perf_event_header header; | |
623 | * | |
624 | * u32 pid, tid; | |
625 | * u64 addr; | |
626 | * u64 len; | |
627 | * u64 pgoff; | |
628 | * char filename[]; | |
c5ecceef | 629 | * struct sample_id sample_id; |
607ca46e DH |
630 | * }; |
631 | */ | |
632 | PERF_RECORD_MMAP = 1, | |
633 | ||
634 | /* | |
635 | * struct { | |
636 | * struct perf_event_header header; | |
637 | * u64 id; | |
638 | * u64 lost; | |
a5cdd40c | 639 | * struct sample_id sample_id; |
607ca46e DH |
640 | * }; |
641 | */ | |
642 | PERF_RECORD_LOST = 2, | |
643 | ||
644 | /* | |
645 | * struct { | |
646 | * struct perf_event_header header; | |
647 | * | |
648 | * u32 pid, tid; | |
649 | * char comm[]; | |
a5cdd40c | 650 | * struct sample_id sample_id; |
607ca46e DH |
651 | * }; |
652 | */ | |
653 | PERF_RECORD_COMM = 3, | |
654 | ||
655 | /* | |
656 | * struct { | |
657 | * struct perf_event_header header; | |
658 | * u32 pid, ppid; | |
659 | * u32 tid, ptid; | |
660 | * u64 time; | |
a5cdd40c | 661 | * struct sample_id sample_id; |
607ca46e DH |
662 | * }; |
663 | */ | |
664 | PERF_RECORD_EXIT = 4, | |
665 | ||
666 | /* | |
667 | * struct { | |
668 | * struct perf_event_header header; | |
669 | * u64 time; | |
670 | * u64 id; | |
671 | * u64 stream_id; | |
a5cdd40c | 672 | * struct sample_id sample_id; |
607ca46e DH |
673 | * }; |
674 | */ | |
675 | PERF_RECORD_THROTTLE = 5, | |
676 | PERF_RECORD_UNTHROTTLE = 6, | |
677 | ||
678 | /* | |
679 | * struct { | |
680 | * struct perf_event_header header; | |
681 | * u32 pid, ppid; | |
682 | * u32 tid, ptid; | |
683 | * u64 time; | |
a5cdd40c | 684 | * struct sample_id sample_id; |
607ca46e DH |
685 | * }; |
686 | */ | |
687 | PERF_RECORD_FORK = 7, | |
688 | ||
689 | /* | |
690 | * struct { | |
691 | * struct perf_event_header header; | |
692 | * u32 pid, tid; | |
693 | * | |
694 | * struct read_format values; | |
a5cdd40c | 695 | * struct sample_id sample_id; |
607ca46e DH |
696 | * }; |
697 | */ | |
698 | PERF_RECORD_READ = 8, | |
699 | ||
700 | /* | |
701 | * struct { | |
702 | * struct perf_event_header header; | |
703 | * | |
ff3d527c AH |
704 | * # |
705 | * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. | |
706 | * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position | |
707 | * # is fixed relative to header. | |
708 | * # | |
709 | * | |
710 | * { u64 id; } && PERF_SAMPLE_IDENTIFIER | |
607ca46e DH |
711 | * { u64 ip; } && PERF_SAMPLE_IP |
712 | * { u32 pid, tid; } && PERF_SAMPLE_TID | |
713 | * { u64 time; } && PERF_SAMPLE_TIME | |
714 | * { u64 addr; } && PERF_SAMPLE_ADDR | |
715 | * { u64 id; } && PERF_SAMPLE_ID | |
716 | * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID | |
717 | * { u32 cpu, res; } && PERF_SAMPLE_CPU | |
718 | * { u64 period; } && PERF_SAMPLE_PERIOD | |
719 | * | |
720 | * { struct read_format values; } && PERF_SAMPLE_READ | |
721 | * | |
722 | * { u64 nr, | |
723 | * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN | |
724 | * | |
725 | * # | |
726 | * # The RAW record below is opaque data wrt the ABI | |
727 | * # | |
728 | * # That is, the ABI doesn't make any promises wrt to | |
729 | * # the stability of its content, it may vary depending | |
730 | * # on event, hardware, kernel version and phase of | |
731 | * # the moon. | |
732 | * # | |
733 | * # In other words, PERF_SAMPLE_RAW contents are not an ABI. | |
734 | * # | |
735 | * | |
736 | * { u32 size; | |
737 | * char data[size];}&& PERF_SAMPLE_RAW | |
738 | * | |
b878e7fb VW |
739 | * { u64 nr; |
740 | * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK | |
607ca46e DH |
741 | * |
742 | * { u64 abi; # enum perf_sample_regs_abi | |
743 | * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER | |
744 | * | |
745 | * { u64 size; | |
746 | * char data[size]; | |
747 | * u64 dyn_size; } && PERF_SAMPLE_STACK_USER | |
c3feedf2 AK |
748 | * |
749 | * { u64 weight; } && PERF_SAMPLE_WEIGHT | |
a5cdd40c | 750 | * { u64 data_src; } && PERF_SAMPLE_DATA_SRC |
189b84fb | 751 | * { u64 transaction; } && PERF_SAMPLE_TRANSACTION |
60e2364e SE |
752 | * { u64 abi; # enum perf_sample_regs_abi |
753 | * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR | |
607ca46e DH |
754 | * }; |
755 | */ | |
756 | PERF_RECORD_SAMPLE = 9, | |
757 | ||
13d7a241 SE |
758 | /* |
759 | * The MMAP2 records are an augmented version of MMAP, they add | |
760 | * maj, min, ino numbers to be used to uniquely identify each mapping | |
761 | * | |
762 | * struct { | |
763 | * struct perf_event_header header; | |
764 | * | |
765 | * u32 pid, tid; | |
766 | * u64 addr; | |
767 | * u64 len; | |
768 | * u64 pgoff; | |
769 | * u32 maj; | |
770 | * u32 min; | |
771 | * u64 ino; | |
772 | * u64 ino_generation; | |
f972eb63 | 773 | * u32 prot, flags; |
13d7a241 SE |
774 | * char filename[]; |
775 | * struct sample_id sample_id; | |
776 | * }; | |
777 | */ | |
778 | PERF_RECORD_MMAP2 = 10, | |
779 | ||
68db7e98 AS |
780 | /* |
781 | * Records that new data landed in the AUX buffer part. | |
782 | * | |
783 | * struct { | |
784 | * struct perf_event_header header; | |
785 | * | |
786 | * u64 aux_offset; | |
787 | * u64 aux_size; | |
788 | * u64 flags; | |
789 | * struct sample_id sample_id; | |
790 | * }; | |
791 | */ | |
792 | PERF_RECORD_AUX = 11, | |
793 | ||
ec0d7729 AS |
794 | /* |
795 | * Indicates that instruction trace has started | |
796 | * | |
797 | * struct { | |
798 | * struct perf_event_header header; | |
799 | * u32 pid; | |
800 | * u32 tid; | |
801 | * }; | |
802 | */ | |
803 | PERF_RECORD_ITRACE_START = 12, | |
804 | ||
607ca46e DH |
805 | PERF_RECORD_MAX, /* non-ABI */ |
806 | }; | |
807 | ||
808 | #define PERF_MAX_STACK_DEPTH 127 | |
809 | ||
810 | enum perf_callchain_context { | |
811 | PERF_CONTEXT_HV = (__u64)-32, | |
812 | PERF_CONTEXT_KERNEL = (__u64)-128, | |
813 | PERF_CONTEXT_USER = (__u64)-512, | |
814 | ||
815 | PERF_CONTEXT_GUEST = (__u64)-2048, | |
816 | PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, | |
817 | PERF_CONTEXT_GUEST_USER = (__u64)-2560, | |
818 | ||
819 | PERF_CONTEXT_MAX = (__u64)-4095, | |
820 | }; | |
821 | ||
68db7e98 AS |
822 | /** |
823 | * PERF_RECORD_AUX::flags bits | |
824 | */ | |
825 | #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ | |
2023a0d2 | 826 | #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ |
68db7e98 | 827 | |
643fd0b9 PZ |
828 | #define PERF_FLAG_FD_NO_GROUP (1UL << 0) |
829 | #define PERF_FLAG_FD_OUTPUT (1UL << 1) | |
830 | #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ | |
831 | #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ | |
607ca46e | 832 | |
d6be9ad6 SE |
833 | union perf_mem_data_src { |
834 | __u64 val; | |
835 | struct { | |
836 | __u64 mem_op:5, /* type of opcode */ | |
837 | mem_lvl:14, /* memory hierarchy level */ | |
838 | mem_snoop:5, /* snoop mode */ | |
839 | mem_lock:2, /* lock instr */ | |
840 | mem_dtlb:7, /* tlb access */ | |
841 | mem_rsvd:31; | |
842 | }; | |
843 | }; | |
844 | ||
845 | /* type of opcode (load/store/prefetch,code) */ | |
846 | #define PERF_MEM_OP_NA 0x01 /* not available */ | |
847 | #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ | |
848 | #define PERF_MEM_OP_STORE 0x04 /* store instruction */ | |
849 | #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ | |
850 | #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ | |
851 | #define PERF_MEM_OP_SHIFT 0 | |
852 | ||
853 | /* memory hierarchy (memory level, hit or miss) */ | |
854 | #define PERF_MEM_LVL_NA 0x01 /* not available */ | |
855 | #define PERF_MEM_LVL_HIT 0x02 /* hit level */ | |
856 | #define PERF_MEM_LVL_MISS 0x04 /* miss level */ | |
857 | #define PERF_MEM_LVL_L1 0x08 /* L1 */ | |
858 | #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ | |
cc2f5a8a SE |
859 | #define PERF_MEM_LVL_L2 0x20 /* L2 */ |
860 | #define PERF_MEM_LVL_L3 0x40 /* L3 */ | |
d6be9ad6 SE |
861 | #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ |
862 | #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ | |
863 | #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ | |
864 | #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ | |
865 | #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ | |
866 | #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ | |
867 | #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ | |
868 | #define PERF_MEM_LVL_SHIFT 5 | |
869 | ||
870 | /* snoop mode */ | |
871 | #define PERF_MEM_SNOOP_NA 0x01 /* not available */ | |
872 | #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ | |
873 | #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ | |
874 | #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ | |
875 | #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ | |
876 | #define PERF_MEM_SNOOP_SHIFT 19 | |
877 | ||
878 | /* locked instruction */ | |
879 | #define PERF_MEM_LOCK_NA 0x01 /* not available */ | |
880 | #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ | |
881 | #define PERF_MEM_LOCK_SHIFT 24 | |
882 | ||
883 | /* TLB access */ | |
884 | #define PERF_MEM_TLB_NA 0x01 /* not available */ | |
885 | #define PERF_MEM_TLB_HIT 0x02 /* hit level */ | |
886 | #define PERF_MEM_TLB_MISS 0x04 /* miss level */ | |
887 | #define PERF_MEM_TLB_L1 0x08 /* L1 */ | |
888 | #define PERF_MEM_TLB_L2 0x10 /* L2 */ | |
889 | #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ | |
890 | #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ | |
891 | #define PERF_MEM_TLB_SHIFT 26 | |
892 | ||
893 | #define PERF_MEM_S(a, s) \ | |
0d9dfc23 | 894 | (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) |
d6be9ad6 | 895 | |
274481de VW |
896 | /* |
897 | * single taken branch record layout: | |
898 | * | |
899 | * from: source instruction (may not always be a branch insn) | |
900 | * to: branch target | |
901 | * mispred: branch target was mispredicted | |
902 | * predicted: branch target was predicted | |
903 | * | |
904 | * support for mispred, predicted is optional. In case it | |
905 | * is not supported mispred = predicted = 0. | |
906 | * | |
907 | * in_tx: running in a hardware transaction | |
908 | * abort: aborting a hardware transaction | |
909 | */ | |
910 | struct perf_branch_entry { | |
911 | __u64 from; | |
912 | __u64 to; | |
913 | __u64 mispred:1, /* target mispredicted */ | |
914 | predicted:1,/* target predicted */ | |
915 | in_tx:1, /* in transaction */ | |
916 | abort:1, /* transaction abort */ | |
917 | reserved:60; | |
918 | }; | |
919 | ||
607ca46e | 920 | #endif /* _UAPI_LINUX_PERF_EVENT_H */ |