Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mtd/nand.h | |
3 | * | |
44d1b980 | 4 | * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org> |
1da177e4 LT |
5 | * Steven J. Hill <sjhill@realitydiluted.com> |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
7 | * | |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
2c0a2bed TG |
12 | * Info: |
13 | * Contains standard defines and IDs for NAND flash devices | |
1da177e4 | 14 | * |
2c0a2bed TG |
15 | * Changelog: |
16 | * See git changelog. | |
1da177e4 LT |
17 | */ |
18 | #ifndef __LINUX_MTD_NAND_H | |
19 | #define __LINUX_MTD_NAND_H | |
20 | ||
1da177e4 LT |
21 | #include <linux/wait.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/mtd/mtd.h> | |
30631cb8 | 24 | #include <linux/mtd/flashchip.h> |
c62d81bc | 25 | #include <linux/mtd/bbm.h> |
1da177e4 LT |
26 | |
27 | struct mtd_info; | |
28 | /* Scan and identify a NAND device */ | |
29 | extern int nand_scan (struct mtd_info *mtd, int max_chips); | |
3b85c321 DW |
30 | /* Separate phases of nand_scan(), allowing board driver to intervene |
31 | * and override command or ECC setup according to flash type */ | |
32 | extern int nand_scan_ident(struct mtd_info *mtd, int max_chips); | |
33 | extern int nand_scan_tail(struct mtd_info *mtd); | |
34 | ||
1da177e4 LT |
35 | /* Free resources held by the NAND device */ |
36 | extern void nand_release (struct mtd_info *mtd); | |
37 | ||
b77d95c7 DW |
38 | /* Internal helper for board drivers which need to override command function */ |
39 | extern void nand_wait_ready(struct mtd_info *mtd); | |
40 | ||
1da177e4 LT |
41 | /* The maximum number of NAND chips in an array */ |
42 | #define NAND_MAX_CHIPS 8 | |
43 | ||
44 | /* This constant declares the max. oobsize / page, which | |
45 | * is supported now. If you add a chip with bigger oobsize/page | |
46 | * adjust this accordingly. | |
47 | */ | |
81ec5364 TG |
48 | #define NAND_MAX_OOBSIZE 128 |
49 | #define NAND_MAX_PAGESIZE 4096 | |
1da177e4 LT |
50 | |
51 | /* | |
52 | * Constants for hardware specific CLE/ALE/NCE function | |
7abd3ef9 TG |
53 | * |
54 | * These are bits which can be or'ed to set/clear multiple | |
55 | * bits in one go. | |
56 | */ | |
1da177e4 | 57 | /* Select the chip by setting nCE to low */ |
7abd3ef9 | 58 | #define NAND_NCE 0x01 |
1da177e4 | 59 | /* Select the command latch by setting CLE to high */ |
7abd3ef9 | 60 | #define NAND_CLE 0x02 |
1da177e4 | 61 | /* Select the address latch by setting ALE to high */ |
7abd3ef9 TG |
62 | #define NAND_ALE 0x04 |
63 | ||
64 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) | |
65 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) | |
66 | #define NAND_CTRL_CHANGE 0x80 | |
1da177e4 LT |
67 | |
68 | /* | |
69 | * Standard NAND flash commands | |
70 | */ | |
71 | #define NAND_CMD_READ0 0 | |
72 | #define NAND_CMD_READ1 1 | |
7bc3312b | 73 | #define NAND_CMD_RNDOUT 5 |
1da177e4 LT |
74 | #define NAND_CMD_PAGEPROG 0x10 |
75 | #define NAND_CMD_READOOB 0x50 | |
76 | #define NAND_CMD_ERASE1 0x60 | |
77 | #define NAND_CMD_STATUS 0x70 | |
78 | #define NAND_CMD_STATUS_MULTI 0x71 | |
79 | #define NAND_CMD_SEQIN 0x80 | |
7bc3312b | 80 | #define NAND_CMD_RNDIN 0x85 |
1da177e4 LT |
81 | #define NAND_CMD_READID 0x90 |
82 | #define NAND_CMD_ERASE2 0xd0 | |
83 | #define NAND_CMD_RESET 0xff | |
84 | ||
85 | /* Extended commands for large page devices */ | |
86 | #define NAND_CMD_READSTART 0x30 | |
7bc3312b | 87 | #define NAND_CMD_RNDOUTSTART 0xE0 |
1da177e4 LT |
88 | #define NAND_CMD_CACHEDPROG 0x15 |
89 | ||
28a48de7 | 90 | /* Extended commands for AG-AND device */ |
61ecfa87 TG |
91 | /* |
92 | * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but | |
28a48de7 DM |
93 | * there is no way to distinguish that from NAND_CMD_READ0 |
94 | * until the remaining sequence of commands has been completed | |
95 | * so add a high order bit and mask it off in the command. | |
96 | */ | |
97 | #define NAND_CMD_DEPLETE1 0x100 | |
98 | #define NAND_CMD_DEPLETE2 0x38 | |
99 | #define NAND_CMD_STATUS_MULTI 0x71 | |
100 | #define NAND_CMD_STATUS_ERROR 0x72 | |
101 | /* multi-bank error status (banks 0-3) */ | |
102 | #define NAND_CMD_STATUS_ERROR0 0x73 | |
103 | #define NAND_CMD_STATUS_ERROR1 0x74 | |
104 | #define NAND_CMD_STATUS_ERROR2 0x75 | |
105 | #define NAND_CMD_STATUS_ERROR3 0x76 | |
106 | #define NAND_CMD_STATUS_RESET 0x7f | |
107 | #define NAND_CMD_STATUS_CLEAR 0xff | |
108 | ||
7abd3ef9 TG |
109 | #define NAND_CMD_NONE -1 |
110 | ||
1da177e4 LT |
111 | /* Status bits */ |
112 | #define NAND_STATUS_FAIL 0x01 | |
113 | #define NAND_STATUS_FAIL_N1 0x02 | |
114 | #define NAND_STATUS_TRUE_READY 0x20 | |
115 | #define NAND_STATUS_READY 0x40 | |
116 | #define NAND_STATUS_WP 0x80 | |
117 | ||
61ecfa87 | 118 | /* |
1da177e4 LT |
119 | * Constants for ECC_MODES |
120 | */ | |
6dfc6d25 TG |
121 | typedef enum { |
122 | NAND_ECC_NONE, | |
123 | NAND_ECC_SOFT, | |
124 | NAND_ECC_HW, | |
125 | NAND_ECC_HW_SYNDROME, | |
6e0cb135 | 126 | NAND_ECC_HW_OOB_FIRST, |
6dfc6d25 | 127 | } nand_ecc_modes_t; |
1da177e4 LT |
128 | |
129 | /* | |
130 | * Constants for Hardware ECC | |
068e3c0a | 131 | */ |
1da177e4 LT |
132 | /* Reset Hardware ECC for read */ |
133 | #define NAND_ECC_READ 0 | |
134 | /* Reset Hardware ECC for write */ | |
135 | #define NAND_ECC_WRITE 1 | |
136 | /* Enable Hardware ECC before syndrom is read back from flash */ | |
137 | #define NAND_ECC_READSYN 2 | |
138 | ||
068e3c0a DM |
139 | /* Bit mask for flags passed to do_nand_read_ecc */ |
140 | #define NAND_GET_DEVICE 0x80 | |
141 | ||
142 | ||
1da177e4 LT |
143 | /* Option constants for bizarre disfunctionality and real |
144 | * features | |
145 | */ | |
146 | /* Chip can not auto increment pages */ | |
147 | #define NAND_NO_AUTOINCR 0x00000001 | |
148 | /* Buswitdh is 16 bit */ | |
149 | #define NAND_BUSWIDTH_16 0x00000002 | |
150 | /* Device supports partial programming without padding */ | |
151 | #define NAND_NO_PADDING 0x00000004 | |
152 | /* Chip has cache program function */ | |
153 | #define NAND_CACHEPRG 0x00000008 | |
154 | /* Chip has copy back function */ | |
155 | #define NAND_COPYBACK 0x00000010 | |
61ecfa87 | 156 | /* AND Chip which has 4 banks and a confusing page / block |
1da177e4 LT |
157 | * assignment. See Renesas datasheet for further information */ |
158 | #define NAND_IS_AND 0x00000020 | |
159 | /* Chip has a array of 4 pages which can be read without | |
160 | * additional ready /busy waits */ | |
61ecfa87 | 161 | #define NAND_4PAGE_ARRAY 0x00000040 |
28a48de7 DM |
162 | /* Chip requires that BBT is periodically rewritten to prevent |
163 | * bits from adjacent blocks from 'leaking' in altering data. | |
164 | * This happens with the Renesas AG-AND chips, possibly others. */ | |
165 | #define BBT_AUTO_REFRESH 0x00000080 | |
7a30601b TG |
166 | /* Chip does not require ready check on read. True |
167 | * for all large page devices, as they do not support | |
168 | * autoincrement.*/ | |
169 | #define NAND_NO_READRDY 0x00000100 | |
29072b96 TG |
170 | /* Chip does not allow subpage writes */ |
171 | #define NAND_NO_SUBPAGE_WRITE 0x00000200 | |
172 | ||
1da177e4 LT |
173 | /* Options valid for Samsung large page devices */ |
174 | #define NAND_SAMSUNG_LP_OPTIONS \ | |
175 | (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) | |
176 | ||
177 | /* Macros to identify the above */ | |
178 | #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) | |
179 | #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) | |
180 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) | |
181 | #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) | |
96d8b647 AK |
182 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
183 | #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ | |
184 | && (chip->page_shift > 9)) | |
1da177e4 LT |
185 | |
186 | /* Mask to zero out the chip options, which come from the id table */ | |
187 | #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) | |
188 | ||
189 | /* Non chip related options */ | |
190 | /* Use a flash based bad block table. This option is passed to the | |
191 | * default bad block table function. */ | |
192 | #define NAND_USE_FLASH_BBT 0x00010000 | |
0040bf38 | 193 | /* This option skips the bbt scan during initialization. */ |
f75e5097 | 194 | #define NAND_SKIP_BBTSCAN 0x00020000 |
4bf63fcb DW |
195 | /* This option is defined if the board driver allocates its own buffers |
196 | (e.g. because it needs them DMA-coherent */ | |
197 | #define NAND_OWN_BUFFERS 0x00040000 | |
b1c6e6db BD |
198 | /* Chip may not exist, so silence any errors in scan */ |
199 | #define NAND_SCAN_SILENT_NODEV 0x00080000 | |
200 | ||
1da177e4 | 201 | /* Options set by nand scan */ |
a36ed299 | 202 | /* Nand scan has allocated controller struct */ |
f75e5097 | 203 | #define NAND_CONTROLLER_ALLOC 0x80000000 |
1da177e4 | 204 | |
29072b96 TG |
205 | /* Cell info constants */ |
206 | #define NAND_CI_CHIPNR_MSK 0x03 | |
207 | #define NAND_CI_CELLTYPE_MSK 0x0C | |
1da177e4 | 208 | |
1da177e4 LT |
209 | /* Keep gcc happy */ |
210 | struct nand_chip; | |
211 | ||
212 | /** | |
844d3b42 | 213 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
61ecfa87 | 214 | * @lock: protection lock |
1da177e4 | 215 | * @active: the mtd device which holds the controller currently |
0dfc6246 TG |
216 | * @wq: wait queue to sleep on if a NAND operation is in progress |
217 | * used instead of the per chip wait queue when a hw controller is available | |
1da177e4 LT |
218 | */ |
219 | struct nand_hw_control { | |
220 | spinlock_t lock; | |
221 | struct nand_chip *active; | |
0dfc6246 | 222 | wait_queue_head_t wq; |
1da177e4 LT |
223 | }; |
224 | ||
6dfc6d25 TG |
225 | /** |
226 | * struct nand_ecc_ctrl - Control structure for ecc | |
227 | * @mode: ecc mode | |
228 | * @steps: number of ecc steps per page | |
229 | * @size: data bytes per ecc step | |
230 | * @bytes: ecc bytes per step | |
9577f44a TG |
231 | * @total: total number of ecc bytes per page |
232 | * @prepad: padding information for syndrome based ecc generators | |
233 | * @postpad: padding information for syndrome based ecc generators | |
844d3b42 | 234 | * @layout: ECC layout control struct pointer |
6dfc6d25 TG |
235 | * @hwctl: function to control hardware ecc generator. Must only |
236 | * be provided if an hardware ECC is available | |
237 | * @calculate: function for ecc calculation or readback from ecc hardware | |
238 | * @correct: function for ecc correction, matching to ecc generator (sw/hw) | |
956e944c DW |
239 | * @read_page_raw: function to read a raw page without ECC |
240 | * @write_page_raw: function to write a raw page without ECC | |
f75e5097 | 241 | * @read_page: function to read a page according to the ecc generator requirements |
17c1d2be | 242 | * @read_subpage: function to read parts of the page covered by ECC. |
9577f44a | 243 | * @write_page: function to write a page according to the ecc generator requirements |
844d3b42 RD |
244 | * @read_oob: function to read chip OOB data |
245 | * @write_oob: function to write chip OOB data | |
6dfc6d25 TG |
246 | */ |
247 | struct nand_ecc_ctrl { | |
248 | nand_ecc_modes_t mode; | |
249 | int steps; | |
250 | int size; | |
251 | int bytes; | |
9577f44a TG |
252 | int total; |
253 | int prepad; | |
254 | int postpad; | |
5bd34c09 | 255 | struct nand_ecclayout *layout; |
9a57d470 | 256 | void (*hwctl)(struct mtd_info *mtd, int mode); |
6dfc6d25 TG |
257 | int (*calculate)(struct mtd_info *mtd, |
258 | const uint8_t *dat, | |
259 | uint8_t *ecc_code); | |
260 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, | |
261 | uint8_t *read_ecc, | |
262 | uint8_t *calc_ecc); | |
956e944c DW |
263 | int (*read_page_raw)(struct mtd_info *mtd, |
264 | struct nand_chip *chip, | |
46a8cf2d | 265 | uint8_t *buf, int page); |
956e944c DW |
266 | void (*write_page_raw)(struct mtd_info *mtd, |
267 | struct nand_chip *chip, | |
268 | const uint8_t *buf); | |
9577f44a TG |
269 | int (*read_page)(struct mtd_info *mtd, |
270 | struct nand_chip *chip, | |
46a8cf2d | 271 | uint8_t *buf, int page); |
3d459559 AK |
272 | int (*read_subpage)(struct mtd_info *mtd, |
273 | struct nand_chip *chip, | |
274 | uint32_t offs, uint32_t len, | |
275 | uint8_t *buf); | |
f75e5097 | 276 | void (*write_page)(struct mtd_info *mtd, |
9577f44a | 277 | struct nand_chip *chip, |
f75e5097 | 278 | const uint8_t *buf); |
7bc3312b TG |
279 | int (*read_oob)(struct mtd_info *mtd, |
280 | struct nand_chip *chip, | |
281 | int page, | |
282 | int sndcmd); | |
283 | int (*write_oob)(struct mtd_info *mtd, | |
284 | struct nand_chip *chip, | |
285 | int page); | |
f75e5097 TG |
286 | }; |
287 | ||
288 | /** | |
289 | * struct nand_buffers - buffer structure for read/write | |
290 | * @ecccalc: buffer for calculated ecc | |
291 | * @ecccode: buffer for ecc read from flash | |
f75e5097 | 292 | * @databuf: buffer for data - dynamically sized |
f75e5097 TG |
293 | * |
294 | * Do not change the order of buffers. databuf and oobrbuf must be in | |
295 | * consecutive order. | |
296 | */ | |
297 | struct nand_buffers { | |
298 | uint8_t ecccalc[NAND_MAX_OOBSIZE]; | |
299 | uint8_t ecccode[NAND_MAX_OOBSIZE]; | |
7dcdcbef | 300 | uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; |
6dfc6d25 TG |
301 | }; |
302 | ||
1da177e4 LT |
303 | /** |
304 | * struct nand_chip - NAND Private Flash Chip Data | |
61ecfa87 TG |
305 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device |
306 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device | |
1da177e4 | 307 | * @read_byte: [REPLACEABLE] read one byte from the chip |
1da177e4 | 308 | * @read_word: [REPLACEABLE] read one word from the chip |
1da177e4 LT |
309 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
310 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
311 | * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data | |
312 | * @select_chip: [REPLACEABLE] select chip nr | |
313 | * @block_bad: [REPLACEABLE] check, if the block is bad | |
314 | * @block_markbad: [REPLACEABLE] mark the block bad | |
7abd3ef9 TG |
315 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling |
316 | * ALE/CLE/nCE. Also used to write command and address | |
1da177e4 LT |
317 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line |
318 | * If set to NULL no access to ready/busy is available and the ready/busy information | |
319 | * is read from the chip status register | |
320 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip | |
321 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready | |
6dfc6d25 | 322 | * @ecc: [BOARDSPECIFIC] ecc control ctructure |
844d3b42 RD |
323 | * @buffers: buffer structure for read/write |
324 | * @hwcontrol: platform-specific hardware control structure | |
325 | * @ops: oob operation operands | |
1da177e4 LT |
326 | * @erase_cmd: [INTERN] erase command write function, selectable due to AND support |
327 | * @scan_bbt: [REPLACEABLE] function to scan bad block table | |
1da177e4 | 328 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) |
2c0a2bed | 329 | * @state: [INTERN] the current state of the NAND device |
844d3b42 | 330 | * @oob_poi: poison value buffer |
1da177e4 LT |
331 | * @page_shift: [INTERN] number of address bits in a page (column address bits) |
332 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock | |
333 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
334 | * @chip_shift: [INTERN] number of address bits in one chip | |
1da177e4 LT |
335 | * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about |
336 | * special functionality. See the defines for further explanation | |
337 | * @badblockpos: [INTERN] position of the bad block marker in the oob area | |
552a8278 | 338 | * @cellinfo: [INTERN] MLC/multichip data from chip ident |
1da177e4 LT |
339 | * @numchips: [INTERN] number of physical chips |
340 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
341 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
342 | * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf | |
29072b96 | 343 | * @subpagesize: [INTERN] holds the subpagesize |
5bd34c09 | 344 | * @ecclayout: [REPLACEABLE] the default ecc placement scheme |
1da177e4 LT |
345 | * @bbt: [INTERN] bad block table pointer |
346 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup | |
347 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor | |
61ecfa87 | 348 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan |
a36ed299 TG |
349 | * @controller: [REPLACEABLE] a pointer to a hardware controller structure |
350 | * which is shared among multiple independend devices | |
1da177e4 | 351 | * @priv: [OPTIONAL] pointer to private chip date |
61ecfa87 | 352 | * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks |
068e3c0a | 353 | * (determine if errors are correctable) |
351edd24 | 354 | * @write_page: [REPLACEABLE] High-level page write function |
1da177e4 | 355 | */ |
61ecfa87 | 356 | |
1da177e4 LT |
357 | struct nand_chip { |
358 | void __iomem *IO_ADDR_R; | |
2c0a2bed | 359 | void __iomem *IO_ADDR_W; |
61ecfa87 | 360 | |
58dd8f2b | 361 | uint8_t (*read_byte)(struct mtd_info *mtd); |
1da177e4 | 362 | u16 (*read_word)(struct mtd_info *mtd); |
58dd8f2b TG |
363 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
364 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
365 | int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
1da177e4 LT |
366 | void (*select_chip)(struct mtd_info *mtd, int chip); |
367 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); | |
368 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); | |
7abd3ef9 TG |
369 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, |
370 | unsigned int ctrl); | |
2c0a2bed TG |
371 | int (*dev_ready)(struct mtd_info *mtd); |
372 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); | |
7bc3312b | 373 | int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); |
1da177e4 LT |
374 | void (*erase_cmd)(struct mtd_info *mtd, int page); |
375 | int (*scan_bbt)(struct mtd_info *mtd); | |
f75e5097 | 376 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); |
956e944c DW |
377 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
378 | const uint8_t *buf, int page, int cached, int raw); | |
f75e5097 | 379 | |
2c0a2bed | 380 | int chip_delay; |
f75e5097 TG |
381 | unsigned int options; |
382 | ||
2c0a2bed | 383 | int page_shift; |
1da177e4 LT |
384 | int phys_erase_shift; |
385 | int bbt_erase_shift; | |
386 | int chip_shift; | |
1da177e4 | 387 | int numchips; |
69423d99 | 388 | uint64_t chipsize; |
1da177e4 LT |
389 | int pagemask; |
390 | int pagebuf; | |
29072b96 TG |
391 | int subpagesize; |
392 | uint8_t cellinfo; | |
f75e5097 TG |
393 | int badblockpos; |
394 | ||
30631cb8 | 395 | flstate_t state; |
f75e5097 TG |
396 | |
397 | uint8_t *oob_poi; | |
398 | struct nand_hw_control *controller; | |
5bd34c09 | 399 | struct nand_ecclayout *ecclayout; |
f75e5097 TG |
400 | |
401 | struct nand_ecc_ctrl ecc; | |
4bf63fcb | 402 | struct nand_buffers *buffers; |
f75e5097 TG |
403 | struct nand_hw_control hwcontrol; |
404 | ||
8593fbc6 TG |
405 | struct mtd_oob_ops ops; |
406 | ||
1da177e4 LT |
407 | uint8_t *bbt; |
408 | struct nand_bbt_descr *bbt_td; | |
409 | struct nand_bbt_descr *bbt_md; | |
f75e5097 | 410 | |
1da177e4 | 411 | struct nand_bbt_descr *badblock_pattern; |
f75e5097 | 412 | |
1da177e4 LT |
413 | void *priv; |
414 | }; | |
415 | ||
416 | /* | |
417 | * NAND Flash Manufacturer ID Codes | |
418 | */ | |
419 | #define NAND_MFR_TOSHIBA 0x98 | |
420 | #define NAND_MFR_SAMSUNG 0xec | |
421 | #define NAND_MFR_FUJITSU 0x04 | |
422 | #define NAND_MFR_NATIONAL 0x8f | |
423 | #define NAND_MFR_RENESAS 0x07 | |
424 | #define NAND_MFR_STMICRO 0x20 | |
2c0a2bed | 425 | #define NAND_MFR_HYNIX 0xad |
8c60e547 | 426 | #define NAND_MFR_MICRON 0x2c |
30eb0db0 | 427 | #define NAND_MFR_AMD 0x01 |
1da177e4 LT |
428 | |
429 | /** | |
430 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
2c0a2bed TG |
431 | * @name: Identify the device type |
432 | * @id: device ID code | |
433 | * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 | |
61ecfa87 | 434 | * If the pagesize is 0, then the real pagesize |
1da177e4 LT |
435 | * and the eraseize are determined from the |
436 | * extended id bytes in the chip | |
2c0a2bed TG |
437 | * @erasesize: Size of an erase block in the flash device. |
438 | * @chipsize: Total chipsize in Mega Bytes | |
1da177e4 LT |
439 | * @options: Bitfield to store chip relevant options |
440 | */ | |
441 | struct nand_flash_dev { | |
442 | char *name; | |
443 | int id; | |
444 | unsigned long pagesize; | |
445 | unsigned long chipsize; | |
446 | unsigned long erasesize; | |
447 | unsigned long options; | |
448 | }; | |
449 | ||
450 | /** | |
451 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure | |
452 | * @name: Manufacturer name | |
2c0a2bed | 453 | * @id: manufacturer ID code of device. |
1da177e4 LT |
454 | */ |
455 | struct nand_manufacturers { | |
456 | int id; | |
457 | char * name; | |
458 | }; | |
459 | ||
460 | extern struct nand_flash_dev nand_flash_ids[]; | |
461 | extern struct nand_manufacturers nand_manuf_ids[]; | |
462 | ||
f5bbdacc TG |
463 | extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); |
464 | extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); | |
465 | extern int nand_default_bbt(struct mtd_info *mtd); | |
466 | extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); | |
467 | extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, | |
468 | int allowbbt); | |
469 | extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, | |
470 | size_t * retlen, uint8_t * buf); | |
1da177e4 | 471 | |
41796c2e TG |
472 | /** |
473 | * struct platform_nand_chip - chip level device structure | |
41796c2e | 474 | * @nr_chips: max. number of chips to scan for |
844d3b42 | 475 | * @chip_offset: chip number offset |
8be834f7 | 476 | * @nr_partitions: number of partitions pointed to by partitions (or zero) |
41796c2e TG |
477 | * @partitions: mtd partition list |
478 | * @chip_delay: R/B delay value in us | |
479 | * @options: Option flags, e.g. 16bit buswidth | |
5bd34c09 | 480 | * @ecclayout: ecc layout info structure |
972edcb7 | 481 | * @part_probe_types: NULL-terminated array of probe types |
f36e20c0 | 482 | * @set_parts: platform specific function to set partitions |
41796c2e TG |
483 | * @priv: hardware controller specific settings |
484 | */ | |
485 | struct platform_nand_chip { | |
486 | int nr_chips; | |
487 | int chip_offset; | |
488 | int nr_partitions; | |
489 | struct mtd_partition *partitions; | |
5bd34c09 | 490 | struct nand_ecclayout *ecclayout; |
2c0a2bed | 491 | int chip_delay; |
41796c2e | 492 | unsigned int options; |
972edcb7 | 493 | const char **part_probe_types; |
f36e20c0 HS |
494 | void (*set_parts)(uint64_t size, |
495 | struct platform_nand_chip *chip); | |
41796c2e TG |
496 | void *priv; |
497 | }; | |
498 | ||
bf95efd4 HS |
499 | /* Keep gcc happy */ |
500 | struct platform_device; | |
501 | ||
41796c2e TG |
502 | /** |
503 | * struct platform_nand_ctrl - controller level device structure | |
bf95efd4 HS |
504 | * @probe: platform specific function to probe/setup hardware |
505 | * @remove: platform specific function to remove/teardown hardware | |
41796c2e TG |
506 | * @hwcontrol: platform specific hardware control structure |
507 | * @dev_ready: platform specific function to read ready/busy pin | |
508 | * @select_chip: platform specific chip select function | |
972edcb7 VW |
509 | * @cmd_ctrl: platform specific function for controlling |
510 | * ALE/CLE/nCE. Also used to write command and address | |
d6fed9e9 AC |
511 | * @write_buf: platform specific function for write buffer |
512 | * @read_buf: platform specific function for read buffer | |
844d3b42 | 513 | * @priv: private data to transport driver specific settings |
41796c2e TG |
514 | * |
515 | * All fields are optional and depend on the hardware driver requirements | |
516 | */ | |
517 | struct platform_nand_ctrl { | |
bf95efd4 HS |
518 | int (*probe)(struct platform_device *pdev); |
519 | void (*remove)(struct platform_device *pdev); | |
2c0a2bed TG |
520 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); |
521 | int (*dev_ready)(struct mtd_info *mtd); | |
41796c2e | 522 | void (*select_chip)(struct mtd_info *mtd, int chip); |
972edcb7 VW |
523 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, |
524 | unsigned int ctrl); | |
d6fed9e9 AC |
525 | void (*write_buf)(struct mtd_info *mtd, |
526 | const uint8_t *buf, int len); | |
527 | void (*read_buf)(struct mtd_info *mtd, | |
528 | uint8_t *buf, int len); | |
41796c2e TG |
529 | void *priv; |
530 | }; | |
531 | ||
972edcb7 VW |
532 | /** |
533 | * struct platform_nand_data - container structure for platform-specific data | |
534 | * @chip: chip level chip structure | |
535 | * @ctrl: controller level device structure | |
536 | */ | |
537 | struct platform_nand_data { | |
538 | struct platform_nand_chip chip; | |
539 | struct platform_nand_ctrl ctrl; | |
540 | }; | |
541 | ||
41796c2e TG |
542 | /* Some helpers to access the data structures */ |
543 | static inline | |
544 | struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) | |
545 | { | |
546 | struct nand_chip *chip = mtd->priv; | |
547 | ||
548 | return chip->priv; | |
549 | } | |
550 | ||
1da177e4 | 551 | #endif /* __LINUX_MTD_NAND_H */ |