[linux-2.6-block.git] / drivers / video / fbdev / sa1100fb.h

/*
 * linux/drivers/video/sa1100fb.h
 *    -- StrongARM 1100 LCD Controller Frame Buffer Device
 *
 *  Copyright (C) 1999 Eric A. Thomas
 *   Based on acornfb.c Copyright (C) Russell King.
 *  
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

#define LCCR0           0x0000          /* LCD Control Reg. 0 */
#define LCSR            0x0004          /* LCD Status Reg. */
#define DBAR1           0x0010          /* LCD DMA Base Address Reg. channel 1 */
#define DCAR1           0x0014          /* LCD DMA Current Address Reg. channel 1 */
#define DBAR2           0x0018          /* LCD DMA Base Address Reg.  channel 2 */
#define DCAR2           0x001C          /* LCD DMA Current Address Reg. channel 2 */
#define LCCR1           0x0020          /* LCD Control Reg. 1 */
#define LCCR2           0x0024          /* LCD Control Reg. 2 */
#define LCCR3           0x0028          /* LCD Control Reg. 3 */

/* Shadows for LCD controller registers */
struct sa1100fb_lcd_reg {
	unsigned long lccr0;
	unsigned long lccr1;
	unsigned long lccr2;
	unsigned long lccr3;
};

struct sa1100fb_info {
	struct fb_info		fb;
	struct device		*dev;
	const struct sa1100fb_rgb *rgb[NR_RGB];
	void __iomem		*base;

	/*
	 * These are the addresses we mapped
	 * the framebuffer memory region to.
	 */
	dma_addr_t		map_dma;
	u_char *		map_cpu;
	u_int			map_size;

	u_char *		screen_cpu;
	dma_addr_t		screen_dma;
	u16 *			palette_cpu;
	dma_addr_t		palette_dma;
	u_int			palette_size;

	dma_addr_t		dbar1;
	dma_addr_t		dbar2;

	u_int			reg_lccr0;
	u_int			reg_lccr1;
	u_int			reg_lccr2;
	u_int			reg_lccr3;

	volatile u_char		state;
	volatile u_char		task_state;
	struct mutex		ctrlr_lock;
	wait_queue_head_t	ctrlr_wait;
	struct work_struct	task;

#ifdef CONFIG_CPU_FREQ
	struct notifier_block	freq_transition;
#endif

	const struct sa1100fb_mach_info *inf;
	struct clk *clk;

	u32 pseudo_palette[16];
};

#define TO_INF(ptr,member)	container_of(ptr,struct sa1100fb_info,member)

#define SA1100_PALETTE_MODE_VAL(bpp)    (((bpp) & 0x018) << 9)

/*
 * These are the actions for set_ctrlr_state
 */
#define C_DISABLE		(0)
#define C_ENABLE		(1)
#define C_DISABLE_CLKCHANGE	(2)
#define C_ENABLE_CLKCHANGE	(3)
#define C_REENABLE		(4)
#define C_DISABLE_PM		(5)
#define C_ENABLE_PM		(6)
#define C_STARTUP		(7)

#define SA1100_NAME	"SA1100"

/*
 * Minimum X and Y resolutions
 */
#define MIN_XRES	64
#define MIN_YRES	64
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/video/sa1100fb.h
	3	* -- StrongARM 1100 LCD Controller Frame Buffer Device
	4	*
	5	* Copyright (C) 1999 Eric A. Thomas
	6	* Based on acornfb.c Copyright (C) Russell King.
	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file COPYING in the main directory of this archive
	10	* for more details.
	11	*/
	12
7cb66dcc RK	13	#define LCCR0 0x0000 /* LCD Control Reg. 0 */
	14	#define LCSR 0x0004 /* LCD Status Reg. */
	15	#define DBAR1 0x0010 /* LCD DMA Base Address Reg. channel 1 */
	16	#define DCAR1 0x0014 /* LCD DMA Current Address Reg. channel 1 */
	17	#define DBAR2 0x0018 /* LCD DMA Base Address Reg. channel 2 */
	18	#define DCAR2 0x001C /* LCD DMA Current Address Reg. channel 2 */
	19	#define LCCR1 0x0020 /* LCD Control Reg. 1 */
	20	#define LCCR2 0x0024 /* LCD Control Reg. 2 */
	21	#define LCCR3 0x0028 /* LCD Control Reg. 3 */
	22
1da177e4 LT	23	/* Shadows for LCD controller registers */
	24	struct sa1100fb_lcd_reg {
	25	unsigned long lccr0;
	26	unsigned long lccr1;
	27	unsigned long lccr2;
	28	unsigned long lccr3;
	29	};
	30
1da177e4 LT	31	struct sa1100fb_info {
	32	struct fb_info fb;
	33	struct device *dev;
58f5cbf2	34	const struct sa1100fb_rgb *rgb[NR_RGB];
7cb66dcc	35	void __iomem *base;
1da177e4	36
1da177e4 LT	37	/*
	38	* These are the addresses we mapped
	39	* the framebuffer memory region to.
	40	*/
	41	dma_addr_t map_dma;
	42	u_char * map_cpu;
	43	u_int map_size;
	44
	45	u_char * screen_cpu;
	46	dma_addr_t screen_dma;
	47	u16 * palette_cpu;
	48	dma_addr_t palette_dma;
	49	u_int palette_size;
	50
	51	dma_addr_t dbar1;
	52	dma_addr_t dbar2;
	53
1da177e4 LT	54	u_int reg_lccr0;
	55	u_int reg_lccr1;
	56	u_int reg_lccr2;
	57	u_int reg_lccr3;
	58
	59	volatile u_char state;
	60	volatile u_char task_state;
7951ac91	61	struct mutex ctrlr_lock;
1da177e4 LT	62	wait_queue_head_t ctrlr_wait;
	63	struct work_struct task;
	64
	65	#ifdef CONFIG_CPU_FREQ
	66	struct notifier_block freq_transition;
1da177e4	67	#endif
086ada54 RK	68
086ada54 RK	69	const struct sa1100fb_mach_info *inf;
23834a41	70	struct clk *clk;
cb6bc3ff RK	71
cb6bc3ff RK	72	u32 pseudo_palette[16];
1da177e4 LT	73	};
1da177e4 LT	74
b385a144	75	#define TO_INF(ptr,member) container_of(ptr,struct sa1100fb_info,member)
1da177e4 LT	76
	77	#define SA1100_PALETTE_MODE_VAL(bpp) (((bpp) & 0x018) << 9)
	78
	79	/*
	80	* These are the actions for set_ctrlr_state
	81	*/
	82	#define C_DISABLE (0)
	83	#define C_ENABLE (1)
	84	#define C_DISABLE_CLKCHANGE (2)
	85	#define C_ENABLE_CLKCHANGE (3)
	86	#define C_REENABLE (4)
	87	#define C_DISABLE_PM (5)
	88	#define C_ENABLE_PM (6)
	89	#define C_STARTUP (7)
	90
	91	#define SA1100_NAME "SA1100"
	92
1da177e4 LT	93	/*
	94	* Minimum X and Y resolutions
	95	*/
	96	#define MIN_XRES 64
	97	#define MIN_YRES 64
	98