[linux-2.6-block.git] / drivers / usb / dwc3 / dwc3-omap.c

// SPDX-License-Identifier: GPL-2.0
/**
 * dwc3-omap.c - OMAP Specific Glue layer
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dwc3-omap.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/extcon.h>
#include <linux/regulator/consumer.h>

#include <linux/usb/otg.h>

/*
 * All these registers belong to OMAP's Wrapper around the
 * DesignWare USB3 Core.
 */

#define USBOTGSS_REVISION			0x0000
#define USBOTGSS_SYSCONFIG			0x0010
#define USBOTGSS_IRQ_EOI			0x0020
#define USBOTGSS_EOI_OFFSET			0x0008
#define USBOTGSS_IRQSTATUS_RAW_0		0x0024
#define USBOTGSS_IRQSTATUS_0			0x0028
#define USBOTGSS_IRQENABLE_SET_0		0x002c
#define USBOTGSS_IRQENABLE_CLR_0		0x0030
#define USBOTGSS_IRQ0_OFFSET			0x0004
#define USBOTGSS_IRQSTATUS_RAW_1		0x0030
#define USBOTGSS_IRQSTATUS_1			0x0034
#define USBOTGSS_IRQENABLE_SET_1		0x0038
#define USBOTGSS_IRQENABLE_CLR_1		0x003c
#define USBOTGSS_IRQSTATUS_RAW_2		0x0040
#define USBOTGSS_IRQSTATUS_2			0x0044
#define USBOTGSS_IRQENABLE_SET_2		0x0048
#define USBOTGSS_IRQENABLE_CLR_2		0x004c
#define USBOTGSS_IRQSTATUS_RAW_3		0x0050
#define USBOTGSS_IRQSTATUS_3			0x0054
#define USBOTGSS_IRQENABLE_SET_3		0x0058
#define USBOTGSS_IRQENABLE_CLR_3		0x005c
#define USBOTGSS_IRQSTATUS_EOI_MISC		0x0030
#define USBOTGSS_IRQSTATUS_RAW_MISC		0x0034
#define USBOTGSS_IRQSTATUS_MISC			0x0038
#define USBOTGSS_IRQENABLE_SET_MISC		0x003c
#define USBOTGSS_IRQENABLE_CLR_MISC		0x0040
#define USBOTGSS_IRQMISC_OFFSET			0x03fc
#define USBOTGSS_UTMI_OTG_STATUS		0x0080
#define USBOTGSS_UTMI_OTG_CTRL			0x0084
#define USBOTGSS_UTMI_OTG_OFFSET		0x0480
#define USBOTGSS_TXFIFO_DEPTH			0x0508
#define USBOTGSS_RXFIFO_DEPTH			0x050c
#define USBOTGSS_MMRAM_OFFSET			0x0100
#define USBOTGSS_FLADJ				0x0104
#define USBOTGSS_DEBUG_CFG			0x0108
#define USBOTGSS_DEBUG_DATA			0x010c
#define USBOTGSS_DEV_EBC_EN			0x0110
#define USBOTGSS_DEBUG_OFFSET			0x0600

/* SYSCONFIG REGISTER */
#define USBOTGSS_SYSCONFIG_DMADISABLE		BIT(16)

/* IRQ_EOI REGISTER */
#define USBOTGSS_IRQ_EOI_LINE_NUMBER		BIT(0)

/* IRQS0 BITS */
#define USBOTGSS_IRQO_COREIRQ_ST		BIT(0)

/* IRQMISC BITS */
#define USBOTGSS_IRQMISC_DMADISABLECLR		BIT(17)
#define USBOTGSS_IRQMISC_OEVT			BIT(16)
#define USBOTGSS_IRQMISC_DRVVBUS_RISE		BIT(13)
#define USBOTGSS_IRQMISC_CHRGVBUS_RISE		BIT(12)
#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE	BIT(11)
#define USBOTGSS_IRQMISC_IDPULLUP_RISE		BIT(8)
#define USBOTGSS_IRQMISC_DRVVBUS_FALL		BIT(5)
#define USBOTGSS_IRQMISC_CHRGVBUS_FALL		BIT(4)
#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL		BIT(3)
#define USBOTGSS_IRQMISC_IDPULLUP_FALL		BIT(0)

/* UTMI_OTG_STATUS REGISTER */
#define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS	BIT(5)
#define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS	BIT(4)
#define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS	BIT(3)
#define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP	BIT(0)

/* UTMI_OTG_CTRL REGISTER */
#define USBOTGSS_UTMI_OTG_CTRL_SW_MODE		BIT(31)
#define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT	BIT(9)
#define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE BIT(8)
#define USBOTGSS_UTMI_OTG_CTRL_IDDIG		BIT(4)
#define USBOTGSS_UTMI_OTG_CTRL_SESSEND		BIT(3)
#define USBOTGSS_UTMI_OTG_CTRL_SESSVALID	BIT(2)
#define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID	BIT(1)

struct dwc3_omap {
	struct device		*dev;

	int			irq;
	void __iomem		*base;

	u32			utmi_otg_ctrl;
	u32			utmi_otg_offset;
	u32			irqmisc_offset;
	u32			irq_eoi_offset;
	u32			debug_offset;
	u32			irq0_offset;

	struct extcon_dev	*edev;
	struct notifier_block	vbus_nb;
	struct notifier_block	id_nb;

	struct regulator	*vbus_reg;
};

enum omap_dwc3_vbus_id_status {
	OMAP_DWC3_ID_FLOAT,
	OMAP_DWC3_ID_GROUND,
	OMAP_DWC3_VBUS_OFF,
	OMAP_DWC3_VBUS_VALID,
};

static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
{
	return readl(base + offset);
}

static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
{
	writel(value, base + offset);
}

static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
							omap->utmi_otg_offset);
}

static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
					omap->utmi_otg_offset, value);

}

static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 -
						omap->irq0_offset);
}

static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
						omap->irq0_offset, value);

}

static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC +
						omap->irqmisc_offset);
}

static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
					omap->irqmisc_offset, value);

}

static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
						omap->irqmisc_offset, value);

}

static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
						omap->irq0_offset, value);
}

static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
						omap->irqmisc_offset, value);
}

static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
						omap->irq0_offset, value);
}

static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
	enum omap_dwc3_vbus_id_status status)
{
	int	ret;
	u32	val;

	switch (status) {
	case OMAP_DWC3_ID_GROUND:
		if (omap->vbus_reg) {
			ret = regulator_enable(omap->vbus_reg);
			if (ret) {
				dev_err(omap->dev, "regulator enable failed\n");
				return;
			}
		}

		val = dwc3_omap_read_utmi_ctrl(omap);
		val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	case OMAP_DWC3_VBUS_VALID:
		val = dwc3_omap_read_utmi_ctrl(omap);
		val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
		val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
				| USBOTGSS_UTMI_OTG_CTRL_SESSVALID;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	case OMAP_DWC3_ID_FLOAT:
		if (omap->vbus_reg)
			regulator_disable(omap->vbus_reg);
		val = dwc3_omap_read_utmi_ctrl(omap);
		val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	case OMAP_DWC3_VBUS_OFF:
		val = dwc3_omap_read_utmi_ctrl(omap);
		val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
				| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID);
		val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	default:
		dev_WARN(omap->dev, "invalid state\n");
	}
}

static void dwc3_omap_enable_irqs(struct dwc3_omap *omap);
static void dwc3_omap_disable_irqs(struct dwc3_omap *omap);

static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
{
	struct dwc3_omap	*omap = _omap;

	if (dwc3_omap_read_irqmisc_status(omap) ||
	    dwc3_omap_read_irq0_status(omap)) {
		/* mask irqs */
		dwc3_omap_disable_irqs(omap);
		return IRQ_WAKE_THREAD;
	}

	return IRQ_NONE;
}

static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap)
{
	struct dwc3_omap	*omap = _omap;
	u32			reg;

	/* clear irq status flags */
	reg = dwc3_omap_read_irqmisc_status(omap);
	dwc3_omap_write_irqmisc_status(omap, reg);

	reg = dwc3_omap_read_irq0_status(omap);
	dwc3_omap_write_irq0_status(omap, reg);

	/* unmask irqs */
	dwc3_omap_enable_irqs(omap);

	return IRQ_HANDLED;
}

static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
{
	u32			reg;

	/* enable all IRQs */
	reg = USBOTGSS_IRQO_COREIRQ_ST;
	dwc3_omap_write_irq0_set(omap, reg);

	reg = (USBOTGSS_IRQMISC_OEVT |
			USBOTGSS_IRQMISC_DRVVBUS_RISE |
			USBOTGSS_IRQMISC_CHRGVBUS_RISE |
			USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
			USBOTGSS_IRQMISC_IDPULLUP_RISE |
			USBOTGSS_IRQMISC_DRVVBUS_FALL |
			USBOTGSS_IRQMISC_CHRGVBUS_FALL |
			USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
			USBOTGSS_IRQMISC_IDPULLUP_FALL);

	dwc3_omap_write_irqmisc_set(omap, reg);
}

static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
{
	u32			reg;

	/* disable all IRQs */
	reg = USBOTGSS_IRQO_COREIRQ_ST;
	dwc3_omap_write_irq0_clr(omap, reg);

	reg = (USBOTGSS_IRQMISC_OEVT |
			USBOTGSS_IRQMISC_DRVVBUS_RISE |
			USBOTGSS_IRQMISC_CHRGVBUS_RISE |
			USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
			USBOTGSS_IRQMISC_IDPULLUP_RISE |
			USBOTGSS_IRQMISC_DRVVBUS_FALL |
			USBOTGSS_IRQMISC_CHRGVBUS_FALL |
			USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
			USBOTGSS_IRQMISC_IDPULLUP_FALL);

	dwc3_omap_write_irqmisc_clr(omap, reg);
}

static int dwc3_omap_id_notifier(struct notifier_block *nb,
	unsigned long event, void *ptr)
{
	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);

	if (event)
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	else
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);

	return NOTIFY_DONE;
}

static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
	unsigned long event, void *ptr)
{
	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);

	if (event)
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	else
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);

	return NOTIFY_DONE;
}

static void dwc3_omap_map_offset(struct dwc3_omap *omap)
{
	struct device_node	*node = omap->dev->of_node;

	/*
	 * Differentiate between OMAP5 and AM437x.
	 *
	 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
	 * though there are changes in wrapper register offsets.
	 *
	 * Using dt compatible to differentiate AM437x.
	 */
	if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
		omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
		omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
		omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
		omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
		omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
	}
}

static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
{
	u32			reg;
	struct device_node	*node = omap->dev->of_node;
	u32			utmi_mode = 0;

	reg = dwc3_omap_read_utmi_ctrl(omap);

	of_property_read_u32(node, "utmi-mode", &utmi_mode);

	switch (utmi_mode) {
	case DWC3_OMAP_UTMI_MODE_SW:
		reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
		break;
	case DWC3_OMAP_UTMI_MODE_HW:
		reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
		break;
	default:
		dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
	}

	dwc3_omap_write_utmi_ctrl(omap, reg);
}

static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
{
	int			ret;
	struct device_node	*node = omap->dev->of_node;
	struct extcon_dev	*edev;

	if (of_property_read_bool(node, "extcon")) {
		edev = extcon_get_edev_by_phandle(omap->dev, 0);
		if (IS_ERR(edev)) {
			dev_vdbg(omap->dev, "couldn't get extcon device\n");
			return -EPROBE_DEFER;
		}

		omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
		ret = devm_extcon_register_notifier(omap->dev, edev,
						EXTCON_USB, &omap->vbus_nb);
		if (ret < 0)
			dev_vdbg(omap->dev, "failed to register notifier for USB\n");

		omap->id_nb.notifier_call = dwc3_omap_id_notifier;
		ret = devm_extcon_register_notifier(omap->dev, edev,
						EXTCON_USB_HOST, &omap->id_nb);
		if (ret < 0)
			dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");

		if (extcon_get_state(edev, EXTCON_USB) == true)
			dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
		if (extcon_get_state(edev, EXTCON_USB_HOST) == true)
			dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);

		omap->edev = edev;
	}

	return 0;
}

static int dwc3_omap_probe(struct platform_device *pdev)
{
	struct device_node	*node = pdev->dev.of_node;

	struct dwc3_omap	*omap;
	struct resource		*res;
	struct device		*dev = &pdev->dev;
	struct regulator	*vbus_reg = NULL;

	int			ret;
	int			irq;

	u32			reg;

	void __iomem		*base;

	if (!node) {
		dev_err(dev, "device node not found\n");
		return -EINVAL;
	}

	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
	if (!omap)
		return -ENOMEM;

	platform_set_drvdata(pdev, omap);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "missing IRQ resource: %d\n", irq);
		return irq;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	if (of_property_read_bool(node, "vbus-supply")) {
		vbus_reg = devm_regulator_get(dev, "vbus");
		if (IS_ERR(vbus_reg)) {
			dev_err(dev, "vbus init failed\n");
			return PTR_ERR(vbus_reg);
		}
	}

	omap->dev	= dev;
	omap->irq	= irq;
	omap->base	= base;
	omap->vbus_reg	= vbus_reg;

	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "get_sync failed with err %d\n", ret);
		goto err1;
	}

	dwc3_omap_map_offset(omap);
	dwc3_omap_set_utmi_mode(omap);

	/* check the DMA Status */
	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);

	ret = dwc3_omap_extcon_register(omap);
	if (ret < 0)
		goto err1;

	ret = of_platform_populate(node, NULL, NULL, dev);
	if (ret) {
		dev_err(&pdev->dev, "failed to create dwc3 core\n");
		goto err1;
	}

	ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt,
					dwc3_omap_interrupt_thread, IRQF_SHARED,
					"dwc3-omap", omap);
	if (ret) {
		dev_err(dev, "failed to request IRQ #%d --> %d\n",
			omap->irq, ret);
		goto err1;
	}
	dwc3_omap_enable_irqs(omap);
	return 0;

err1:
	pm_runtime_put_sync(dev);
	pm_runtime_disable(dev);

	return ret;
}

static int dwc3_omap_remove(struct platform_device *pdev)
{
	struct dwc3_omap	*omap = platform_get_drvdata(pdev);

	dwc3_omap_disable_irqs(omap);
	disable_irq(omap->irq);
	of_platform_depopulate(omap->dev);
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static const struct of_device_id of_dwc3_match[] = {
	{
		.compatible =	"ti,dwc3"
	},
	{
		.compatible =	"ti,am437x-dwc3"
	},
	{ },
};
MODULE_DEVICE_TABLE(of, of_dwc3_match);

#ifdef CONFIG_PM_SLEEP
static int dwc3_omap_suspend(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
	dwc3_omap_disable_irqs(omap);

	return 0;
}

static int dwc3_omap_resume(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
	dwc3_omap_enable_irqs(omap);

	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;
}

static void dwc3_omap_complete(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	if (extcon_get_state(omap->edev, EXTCON_USB))
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	else
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);

	if (extcon_get_state(omap->edev, EXTCON_USB_HOST))
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	else
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
}

static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {

	SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
	.complete = dwc3_omap_complete,
};

#define DEV_PM_OPS	(&dwc3_omap_dev_pm_ops)
#else
#define DEV_PM_OPS	NULL
#endif /* CONFIG_PM_SLEEP */

static struct platform_driver dwc3_omap_driver = {
	.probe		= dwc3_omap_probe,
	.remove		= dwc3_omap_remove,
	.driver		= {
		.name	= "omap-dwc3",
		.of_match_table	= of_dwc3_match,
		.pm	= DEV_PM_OPS,
	},
};

module_platform_driver(dwc3_omap_driver);

MODULE_ALIAS("platform:omap-dwc3");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
72246da4 FB	2	/**
	3	* dwc3-omap.c - OMAP Specific Glue layer
	4	*
	5	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	6	*
	7	* Authors: Felipe Balbi <balbi@ti.com>,
	8	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
72246da4 FB	9	*/
72246da4 FB	10
a72e658b	11	#include <linux/module.h>
72246da4 FB	12	#include <linux/kernel.h>
72246da4 FB	13	#include <linux/slab.h>
12a7f17f	14	#include <linux/irq.h>
72246da4	15	#include <linux/interrupt.h>
72246da4	16	#include <linux/platform_device.h>
9962444f	17	#include <linux/platform_data/dwc3-omap.h>
af310e96	18	#include <linux/pm_runtime.h>
72246da4 FB	19	#include <linux/dma-mapping.h>
	20	#include <linux/ioport.h>
	21	#include <linux/io.h>
45b3cd4a	22	#include <linux/of.h>
b4bfe6aa	23	#include <linux/of_platform.h>
8061ad72	24	#include <linux/extcon.h>
8061ad72	25	#include <linux/regulator/consumer.h>
72246da4	26
a418cc4e	27	#include <linux/usb/otg.h>
a418cc4e	28
72246da4 FB	29	/*
	30	* All these registers belong to OMAP's Wrapper around the
	31	* DesignWare USB3 Core.
	32	*/
	33
	34	#define USBOTGSS_REVISION 0x0000
	35	#define USBOTGSS_SYSCONFIG 0x0010
	36	#define USBOTGSS_IRQ_EOI 0x0020
ff7307b5	37	#define USBOTGSS_EOI_OFFSET 0x0008
72246da4 FB	38	#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
	39	#define USBOTGSS_IRQSTATUS_0 0x0028
	40	#define USBOTGSS_IRQENABLE_SET_0 0x002c
	41	#define USBOTGSS_IRQENABLE_CLR_0 0x0030
ff7307b5	42	#define USBOTGSS_IRQ0_OFFSET 0x0004
b1fd6cb5 GC	43	#define USBOTGSS_IRQSTATUS_RAW_1 0x0030
	44	#define USBOTGSS_IRQSTATUS_1 0x0034
	45	#define USBOTGSS_IRQENABLE_SET_1 0x0038
	46	#define USBOTGSS_IRQENABLE_CLR_1 0x003c
	47	#define USBOTGSS_IRQSTATUS_RAW_2 0x0040
	48	#define USBOTGSS_IRQSTATUS_2 0x0044
	49	#define USBOTGSS_IRQENABLE_SET_2 0x0048
	50	#define USBOTGSS_IRQENABLE_CLR_2 0x004c
	51	#define USBOTGSS_IRQSTATUS_RAW_3 0x0050
	52	#define USBOTGSS_IRQSTATUS_3 0x0054
	53	#define USBOTGSS_IRQENABLE_SET_3 0x0058
	54	#define USBOTGSS_IRQENABLE_CLR_3 0x005c
ff7307b5 GC	55	#define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
	56	#define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
	57	#define USBOTGSS_IRQSTATUS_MISC 0x0038
	58	#define USBOTGSS_IRQENABLE_SET_MISC 0x003c
	59	#define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
	60	#define USBOTGSS_IRQMISC_OFFSET 0x03fc
22832190 BL	61	#define USBOTGSS_UTMI_OTG_STATUS 0x0080
22832190 BL	62	#define USBOTGSS_UTMI_OTG_CTRL 0x0084
ff7307b5 GC	63	#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
	64	#define USBOTGSS_TXFIFO_DEPTH 0x0508
	65	#define USBOTGSS_RXFIFO_DEPTH 0x050c
72246da4 FB	66	#define USBOTGSS_MMRAM_OFFSET 0x0100
	67	#define USBOTGSS_FLADJ 0x0104
	68	#define USBOTGSS_DEBUG_CFG 0x0108
	69	#define USBOTGSS_DEBUG_DATA 0x010c
ff7307b5 GC	70	#define USBOTGSS_DEV_EBC_EN 0x0110
ff7307b5 GC	71	#define USBOTGSS_DEBUG_OFFSET 0x0600
72246da4 FB	72
72246da4 FB	73	/* SYSCONFIG REGISTER */
ff3f0789	74	#define USBOTGSS_SYSCONFIG_DMADISABLE BIT(16)
4b5faa7a	75
72246da4	76	/* IRQ_EOI REGISTER */
ff3f0789	77	#define USBOTGSS_IRQ_EOI_LINE_NUMBER BIT(0)
72246da4 FB	78
72246da4 FB	79	/* IRQS0 BITS */
ff3f0789	80	#define USBOTGSS_IRQO_COREIRQ_ST BIT(0)
72246da4	81
b1fd6cb5	82	/* IRQMISC BITS */
ff3f0789 RQ	83	#define USBOTGSS_IRQMISC_DMADISABLECLR BIT(17)
	84	#define USBOTGSS_IRQMISC_OEVT BIT(16)
	85	#define USBOTGSS_IRQMISC_DRVVBUS_RISE BIT(13)
	86	#define USBOTGSS_IRQMISC_CHRGVBUS_RISE BIT(12)
	87	#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE BIT(11)
	88	#define USBOTGSS_IRQMISC_IDPULLUP_RISE BIT(8)
	89	#define USBOTGSS_IRQMISC_DRVVBUS_FALL BIT(5)
	90	#define USBOTGSS_IRQMISC_CHRGVBUS_FALL BIT(4)
	91	#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL BIT(3)
	92	#define USBOTGSS_IRQMISC_IDPULLUP_FALL BIT(0)
72246da4	93
72246da4	94	/* UTMI_OTG_STATUS REGISTER */
ff3f0789 RQ	95	#define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS BIT(5)
	96	#define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS BIT(4)
	97	#define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS BIT(3)
	98	#define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP BIT(0)
22832190 BL	99
22832190 BL	100	/* UTMI_OTG_CTRL REGISTER */
ff3f0789 RQ	101	#define USBOTGSS_UTMI_OTG_CTRL_SW_MODE BIT(31)
	102	#define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT BIT(9)
	103	#define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE BIT(8)
	104	#define USBOTGSS_UTMI_OTG_CTRL_IDDIG BIT(4)
	105	#define USBOTGSS_UTMI_OTG_CTRL_SESSEND BIT(3)
	106	#define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2)
	107	#define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1)
72246da4 FB	108
72246da4 FB	109	struct dwc3_omap {
72246da4 FB	110	struct device *dev;
	111
	112	int irq;
	113	void __iomem *base;
	114
22832190	115	u32 utmi_otg_ctrl;
1e2a064c GC	116	u32 utmi_otg_offset;
	117	u32 irqmisc_offset;
	118	u32 irq_eoi_offset;
	119	u32 debug_offset;
	120	u32 irq0_offset;
f3e117f4	121
5960387a	122	struct extcon_dev *edev;
8061ad72 KVA	123	struct notifier_block vbus_nb;
	124	struct notifier_block id_nb;
	125
	126	struct regulator *vbus_reg;
72246da4 FB	127	};
72246da4 FB	128
8061ad72 KVA	129	enum omap_dwc3_vbus_id_status {
	130	OMAP_DWC3_ID_FLOAT,
	131	OMAP_DWC3_ID_GROUND,
	132	OMAP_DWC3_VBUS_OFF,
	133	OMAP_DWC3_VBUS_VALID,
	134	};
7e41bba9	135
ab5e59db IS	136	static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
	137	{
	138	return readl(base + offset);
	139	}
	140
	141	static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
	142	{
	143	writel(value, base + offset);
	144	}
	145
22832190	146	static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
b1fd6cb5	147	{
22832190	148	return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
b1fd6cb5 GC	149	omap->utmi_otg_offset);
	150	}
	151
22832190	152	static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
b1fd6cb5	153	{
22832190	154	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
b1fd6cb5 GC	155	omap->utmi_otg_offset, value);
	156
	157	}
	158
	159	static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
	160	{
3f586c92	161	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 -
b1fd6cb5 GC	162	omap->irq0_offset);
	163	}
	164
	165	static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
	166	{
	167	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
	168	omap->irq0_offset, value);
	169
	170	}
	171
	172	static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
	173	{
3f586c92	174	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC +
b1fd6cb5 GC	175	omap->irqmisc_offset);
	176	}
	177
	178	static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
	179	{
	180	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
	181	omap->irqmisc_offset, value);
	182
	183	}
	184
	185	static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
	186	{
	187	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
	188	omap->irqmisc_offset, value);
	189
	190	}
	191
	192	static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
	193	{
	194	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
	195	omap->irq0_offset, value);
	196	}
	197
96e5d312 GC	198	static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
	199	{
	200	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
	201	omap->irqmisc_offset, value);
	202	}
	203
	204	static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
	205	{
	206	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
	207	omap->irq0_offset, value);
	208	}
	209
8061ad72 KVA	210	static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
8061ad72 KVA	211	enum omap_dwc3_vbus_id_status status)
7e41bba9	212	{
8061ad72 KVA	213	int ret;
8061ad72 KVA	214	u32 val;
2ba7943a	215
7e41bba9 KVA	216	switch (status) {
7e41bba9 KVA	217	case OMAP_DWC3_ID_GROUND:
8061ad72 KVA	218	if (omap->vbus_reg) {
	219	ret = regulator_enable(omap->vbus_reg);
	220	if (ret) {
e4f75667	221	dev_err(omap->dev, "regulator enable failed\n");
8061ad72 KVA	222	return;
	223	}
	224	}
	225
22832190	226	val = dwc3_omap_read_utmi_ctrl(omap);
d2728fb3	227	val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG;
22832190	228	dwc3_omap_write_utmi_ctrl(omap, val);
7e41bba9 KVA	229	break;
	230
	231	case OMAP_DWC3_VBUS_VALID:
22832190 BL	232	val = dwc3_omap_read_utmi_ctrl(omap);
22832190 BL	233	val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
d2728fb3	234	val \|= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
9ab330bf	235	\| USBOTGSS_UTMI_OTG_CTRL_SESSVALID;
22832190	236	dwc3_omap_write_utmi_ctrl(omap, val);
7e41bba9 KVA	237	break;
	238
	239	case OMAP_DWC3_ID_FLOAT:
8061ad72 KVA	240	if (omap->vbus_reg)
8061ad72 KVA	241	regulator_disable(omap->vbus_reg);
d2728fb3 RQ	242	val = dwc3_omap_read_utmi_ctrl(omap);
	243	val \|= USBOTGSS_UTMI_OTG_CTRL_IDDIG;
	244	dwc3_omap_write_utmi_ctrl(omap, val);
0913750f	245	break;
8061ad72	246
7e41bba9	247	case OMAP_DWC3_VBUS_OFF:
22832190 BL	248	val = dwc3_omap_read_utmi_ctrl(omap);
22832190 BL	249	val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
9ab330bf	250	\| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID);
d2728fb3	251	val \|= USBOTGSS_UTMI_OTG_CTRL_SESSEND;
22832190	252	dwc3_omap_write_utmi_ctrl(omap, val);
7e41bba9 KVA	253	break;
	254
	255	default:
e4f75667	256	dev_WARN(omap->dev, "invalid state\n");
7e41bba9	257	}
7e41bba9	258	}
7e41bba9	259
3f586c92 RQ	260	static void dwc3_omap_enable_irqs(struct dwc3_omap *omap);
	261	static void dwc3_omap_disable_irqs(struct dwc3_omap *omap);
	262
72246da4	263	static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
3f586c92 RQ	264	{
	265	struct dwc3_omap *omap = _omap;
	266
	267	if (dwc3_omap_read_irqmisc_status(omap) \|\|
	268	dwc3_omap_read_irq0_status(omap)) {
	269	/* mask irqs */
	270	dwc3_omap_disable_irqs(omap);
	271	return IRQ_WAKE_THREAD;
	272	}
	273
	274	return IRQ_NONE;
	275	}
	276
	277	static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap)
72246da4 FB	278	{
	279	struct dwc3_omap *omap = _omap;
	280	u32 reg;
72246da4	281
3f586c92	282	/* clear irq status flags */
b1fd6cb5	283	reg = dwc3_omap_read_irqmisc_status(omap);
b1fd6cb5 GC	284	dwc3_omap_write_irqmisc_status(omap, reg);
	285
	286	reg = dwc3_omap_read_irq0_status(omap);
b1fd6cb5	287	dwc3_omap_write_irq0_status(omap, reg);
72246da4	288
3f586c92 RQ	289	/* unmask irqs */
	290	dwc3_omap_enable_irqs(omap);
	291
72246da4 FB	292	return IRQ_HANDLED;
	293	}
	294
9a4b5dab FB	295	static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
	296	{
	297	u32 reg;
	298
	299	/* enable all IRQs */
	300	reg = USBOTGSS_IRQO_COREIRQ_ST;
b1fd6cb5 GC	301	dwc3_omap_write_irq0_set(omap, reg);
	302
	303	reg = (USBOTGSS_IRQMISC_OEVT \|
	304	USBOTGSS_IRQMISC_DRVVBUS_RISE \|
	305	USBOTGSS_IRQMISC_CHRGVBUS_RISE \|
	306	USBOTGSS_IRQMISC_DISCHRGVBUS_RISE \|
	307	USBOTGSS_IRQMISC_IDPULLUP_RISE \|
	308	USBOTGSS_IRQMISC_DRVVBUS_FALL \|
	309	USBOTGSS_IRQMISC_CHRGVBUS_FALL \|
	310	USBOTGSS_IRQMISC_DISCHRGVBUS_FALL \|
	311	USBOTGSS_IRQMISC_IDPULLUP_FALL);
	312
	313	dwc3_omap_write_irqmisc_set(omap, reg);
9a4b5dab FB	314	}
	315
	316	static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
	317	{
96e5d312 GC	318	u32 reg;
96e5d312 GC	319
9a4b5dab	320	/* disable all IRQs */
96e5d312 GC	321	reg = USBOTGSS_IRQO_COREIRQ_ST;
	322	dwc3_omap_write_irq0_clr(omap, reg);
	323
	324	reg = (USBOTGSS_IRQMISC_OEVT \|
	325	USBOTGSS_IRQMISC_DRVVBUS_RISE \|
	326	USBOTGSS_IRQMISC_CHRGVBUS_RISE \|
	327	USBOTGSS_IRQMISC_DISCHRGVBUS_RISE \|
	328	USBOTGSS_IRQMISC_IDPULLUP_RISE \|
	329	USBOTGSS_IRQMISC_DRVVBUS_FALL \|
	330	USBOTGSS_IRQMISC_CHRGVBUS_FALL \|
	331	USBOTGSS_IRQMISC_DISCHRGVBUS_FALL \|
	332	USBOTGSS_IRQMISC_IDPULLUP_FALL);
	333
	334	dwc3_omap_write_irqmisc_clr(omap, reg);
9a4b5dab FB	335	}
9a4b5dab FB	336
8061ad72 KVA	337	static int dwc3_omap_id_notifier(struct notifier_block *nb,
	338	unsigned long event, void *ptr)
	339	{
	340	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
	341
	342	if (event)
	343	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	344	else
	345	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
	346
	347	return NOTIFY_DONE;
	348	}
	349
	350	static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
	351	unsigned long event, void *ptr)
	352	{
	353	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
	354
	355	if (event)
	356	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	357	else
	358	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
	359
	360	return NOTIFY_DONE;
	361	}
	362
30fef1a9 GC	363	static void dwc3_omap_map_offset(struct dwc3_omap *omap)
	364	{
	365	struct device_node *node = omap->dev->of_node;
	366
	367	/*
	368	* Differentiate between OMAP5 and AM437x.
	369	*
	370	* For OMAP5(ES2.0) and AM437x wrapper revision is same, even
	371	* though there are changes in wrapper register offsets.
	372	*
	373	* Using dt compatible to differentiate AM437x.
	374	*/
	375	if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
	376	omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
	377	omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
	378	omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
	379	omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
	380	omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
	381	}
	382	}
	383
d2f0cf89 GC	384	static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
	385	{
	386	u32 reg;
	387	struct device_node *node = omap->dev->of_node;
73561128	388	u32 utmi_mode = 0;
d2f0cf89	389
22832190	390	reg = dwc3_omap_read_utmi_ctrl(omap);
d2f0cf89 GC	391
	392	of_property_read_u32(node, "utmi-mode", &utmi_mode);
	393
	394	switch (utmi_mode) {
	395	case DWC3_OMAP_UTMI_MODE_SW:
22832190	396	reg \|= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
d2f0cf89 GC	397	break;
d2f0cf89 GC	398	case DWC3_OMAP_UTMI_MODE_HW:
22832190	399	reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
d2f0cf89 GC	400	break;
d2f0cf89 GC	401	default:
e4f75667	402	dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
d2f0cf89 GC	403	}
d2f0cf89 GC	404
22832190	405	dwc3_omap_write_utmi_ctrl(omap, reg);
d2f0cf89 GC	406	}
d2f0cf89 GC	407
025b431b GC	408	static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
025b431b GC	409	{
788b0bc4	410	int ret;
025b431b GC	411	struct device_node *node = omap->dev->of_node;
	412	struct extcon_dev *edev;
	413
	414	if (of_property_read_bool(node, "extcon")) {
	415	edev = extcon_get_edev_by_phandle(omap->dev, 0);
	416	if (IS_ERR(edev)) {
	417	dev_vdbg(omap->dev, "couldn't get extcon device\n");
	418	return -EPROBE_DEFER;
	419	}
	420
	421	omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
c773bb0b CC	422	ret = devm_extcon_register_notifier(omap->dev, edev,
c773bb0b CC	423	EXTCON_USB, &omap->vbus_nb);
025b431b GC	424	if (ret < 0)
	425	dev_vdbg(omap->dev, "failed to register notifier for USB\n");
	426
	427	omap->id_nb.notifier_call = dwc3_omap_id_notifier;
c773bb0b CC	428	ret = devm_extcon_register_notifier(omap->dev, edev,
c773bb0b CC	429	EXTCON_USB_HOST, &omap->id_nb);
025b431b GC	430	if (ret < 0)
	431	dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
	432
c773bb0b	433	if (extcon_get_state(edev, EXTCON_USB) == true)
025b431b	434	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
c773bb0b	435	if (extcon_get_state(edev, EXTCON_USB_HOST) == true)
025b431b	436	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
5960387a CC	437
5960387a CC	438	omap->edev = edev;
025b431b GC	439	}
	440
	441	return 0;
	442	}
	443
41ac7b3a	444	static int dwc3_omap_probe(struct platform_device *pdev)
72246da4	445	{
45b3cd4a FB	446	struct device_node *node = pdev->dev.of_node;
45b3cd4a FB	447
72246da4 FB	448	struct dwc3_omap *omap;
72246da4 FB	449	struct resource *res;
802ca850	450	struct device *dev = &pdev->dev;
8061ad72	451	struct regulator *vbus_reg = NULL;
72246da4	452
b09e99ee	453	int ret;
72246da4 FB	454	int irq;
	455
	456	u32 reg;
	457
	458	void __iomem *base;
72246da4	459
4495afcf KVA	460	if (!node) {
	461	dev_err(dev, "device node not found\n");
	462	return -EINVAL;
	463	}
	464
802ca850	465	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
734d5a53	466	if (!omap)
802ca850	467	return -ENOMEM;
72246da4 FB	468
	469	platform_set_drvdata(pdev, omap);
	470
e36a0c87	471	irq = platform_get_irq(pdev, 0);
72246da4	472	if (irq < 0) {
0ae99ecb GS	473	dev_err(dev, "missing IRQ resource: %d\n", irq);
0ae99ecb GS	474	return irq;
72246da4 FB	475	}
72246da4 FB	476
e36a0c87	477	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8bbcd17d FB	478	base = devm_ioremap_resource(dev, res);
	479	if (IS_ERR(base))
	480	return PTR_ERR(base);
72246da4	481
8061ad72 KVA	482	if (of_property_read_bool(node, "vbus-supply")) {
	483	vbus_reg = devm_regulator_get(dev, "vbus");
	484	if (IS_ERR(vbus_reg)) {
	485	dev_err(dev, "vbus init failed\n");
	486	return PTR_ERR(vbus_reg);
	487	}
	488	}
	489
802ca850	490	omap->dev = dev;
72246da4 FB	491	omap->irq = irq;
72246da4 FB	492	omap->base = base;
8061ad72	493	omap->vbus_reg = vbus_reg;
72246da4	494
af310e96 KVA	495	pm_runtime_enable(dev);
	496	ret = pm_runtime_get_sync(dev);
	497	if (ret < 0) {
	498	dev_err(dev, "get_sync failed with err %d\n", ret);
45d49cb7	499	goto err1;
af310e96 KVA	500	}
af310e96 KVA	501
30fef1a9	502	dwc3_omap_map_offset(omap);
d2f0cf89	503	dwc3_omap_set_utmi_mode(omap);
9962444f	504
72246da4	505	/* check the DMA Status */
ab5e59db	506	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
72246da4	507
025b431b GC	508	ret = dwc3_omap_extcon_register(omap);
025b431b GC	509	if (ret < 0)
45d49cb7	510	goto err1;
8061ad72	511
4495afcf KVA	512	ret = of_platform_populate(node, NULL, NULL, dev);
	513	if (ret) {
	514	dev_err(&pdev->dev, "failed to create dwc3 core\n");
c773bb0b	515	goto err1;
72246da4 FB	516	}
72246da4 FB	517
ee249b45 V	518	ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt,
	519	dwc3_omap_interrupt_thread, IRQF_SHARED,
	520	"dwc3-omap", omap);
	521	if (ret) {
	522	dev_err(dev, "failed to request IRQ #%d --> %d\n",
	523	omap->irq, ret);
	524	goto err1;
	525	}
e2ae0692	526	dwc3_omap_enable_irqs(omap);
72246da4	527	return 0;
594daba1	528
594daba1 KVA	529	err1:
594daba1 KVA	530	pm_runtime_put_sync(dev);
594daba1 KVA	531	pm_runtime_disable(dev);
	532
	533	return ret;
72246da4 FB	534	}
72246da4 FB	535
fb4e98ab	536	static int dwc3_omap_remove(struct platform_device *pdev)
72246da4	537	{
9a4b5dab FB	538	struct dwc3_omap *omap = platform_get_drvdata(pdev);
	539
	540	dwc3_omap_disable_irqs(omap);
12a7f17f	541	disable_irq(omap->irq);
3d0184d0	542	of_platform_depopulate(omap->dev);
af310e96 KVA	543	pm_runtime_put_sync(&pdev->dev);
af310e96 KVA	544	pm_runtime_disable(&pdev->dev);
94c6a436	545
72246da4 FB	546	return 0;
	547	}
	548
2c2dc89c	549	static const struct of_device_id of_dwc3_match[] = {
72246da4	550	{
e36a0c87	551	.compatible = "ti,dwc3"
72246da4	552	},
ff7307b5 GC	553	{
	554	.compatible = "ti,am437x-dwc3"
	555	},
72246da4 FB	556	{ },
72246da4 FB	557	};
2c2dc89c	558	MODULE_DEVICE_TABLE(of, of_dwc3_match);
72246da4	559
19fda7cd	560	#ifdef CONFIG_PM_SLEEP
f3e117f4 FB	561	static int dwc3_omap_suspend(struct device *dev)
	562	{
	563	struct dwc3_omap *omap = dev_get_drvdata(dev);
	564
22832190	565	omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
7ee2566f	566	dwc3_omap_disable_irqs(omap);
f3e117f4 FB	567
	568	return 0;
	569	}
	570
	571	static int dwc3_omap_resume(struct device *dev)
	572	{
	573	struct dwc3_omap *omap = dev_get_drvdata(dev);
	574
22832190	575	dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
7ee2566f	576	dwc3_omap_enable_irqs(omap);
f3e117f4 FB	577
	578	pm_runtime_disable(dev);
	579	pm_runtime_set_active(dev);
	580	pm_runtime_enable(dev);
	581
	582	return 0;
	583	}
	584
c49f6305 RQ	585	static void dwc3_omap_complete(struct device *dev)
	586	{
	587	struct dwc3_omap *omap = dev_get_drvdata(dev);
	588
	589	if (extcon_get_state(omap->edev, EXTCON_USB))
	590	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	591	else
	592	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
	593
	594	if (extcon_get_state(omap->edev, EXTCON_USB_HOST))
	595	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	596	else
	597	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
	598	}
	599
f3e117f4	600	static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
f3e117f4 FB	601
f3e117f4 FB	602	SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
c49f6305	603	.complete = dwc3_omap_complete,
f3e117f4 FB	604	};
	605
	606	#define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
	607	#else
	608	#define DEV_PM_OPS NULL
19fda7cd	609	#endif /* CONFIG_PM_SLEEP */
f3e117f4	610
72246da4 FB	611	static struct platform_driver dwc3_omap_driver = {
72246da4 FB	612	.probe = dwc3_omap_probe,
7690417d	613	.remove = dwc3_omap_remove,
72246da4 FB	614	.driver = {
72246da4 FB	615	.name = "omap-dwc3",
2c2dc89c	616	.of_match_table = of_dwc3_match,
f3e117f4	617	.pm = DEV_PM_OPS,
72246da4 FB	618	},
	619	};
	620
cc27c96c AL	621	module_platform_driver(dwc3_omap_driver);
cc27c96c AL	622
7ae4fc4d	623	MODULE_ALIAS("platform:omap-dwc3");
72246da4	624	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789	625	MODULE_LICENSE("GPL v2");
72246da4	626	MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");