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usb: dwc3: core: Call dwc3_core_get_phy() before initializing phys
[linux-2.6-block.git] / drivers / usb / dwc3 / core.c
CommitLineData
72246da4
FB		 1/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4 17 *
5945f789
FB		 18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
72246da4
FB		 20 */
21
fa0ea13e 22#include <linux/version.h>
a72e658b 23#include <linux/module.h>
72246da4
FB		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/interrupt.h>
30#include <linux/ioport.h>
31#include <linux/io.h>
32#include <linux/list.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
457e84b6 35#include <linux/of.h>
404905a6 36#include <linux/acpi.h>
6344475f 37#include <linux/pinctrl/consumer.h>
72246da4
FB		 38
39#include <linux/usb/ch9.h>
40#include <linux/usb/gadget.h>
f7e846f0 41#include <linux/usb/of.h>
a45c82b8 42#include <linux/usb/otg.h>
72246da4
FB		 43
44#include "core.h"
45#include "gadget.h"
46#include "io.h"
47
48#include "debug.h"
49
fc8bb91b 50#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 51
9d6173e1
TN		 52/**
53 * dwc3_get_dr_mode - Validates and sets dr_mode
54 * @dwc: pointer to our context structure
55 */
56static int dwc3_get_dr_mode(struct dwc3 *dwc)
57{
58 enum usb_dr_mode mode;
59 struct device *dev = dwc->dev;
60 unsigned int hw_mode;
61
62 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
63 dwc->dr_mode = USB_DR_MODE_OTG;
64
65 mode = dwc->dr_mode;
66 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
67
68 switch (hw_mode) {
69 case DWC3_GHWPARAMS0_MODE_GADGET:
70 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
71 dev_err(dev,
72 "Controller does not support host mode.\n");
73 return -EINVAL;
74 }
75 mode = USB_DR_MODE_PERIPHERAL;
76 break;
77 case DWC3_GHWPARAMS0_MODE_HOST:
78 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
79 dev_err(dev,
80 "Controller does not support device mode.\n");
81 return -EINVAL;
82 }
83 mode = USB_DR_MODE_HOST;
84 break;
85 default:
86 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
87 mode = USB_DR_MODE_HOST;
88 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
89 mode = USB_DR_MODE_PERIPHERAL;
90 }
91
92 if (mode != dwc->dr_mode) {
93 dev_warn(dev,
94 "Configuration mismatch. dr_mode forced to %s\n",
95 mode == USB_DR_MODE_HOST ? "host" : "gadget");
96
97 dwc->dr_mode = mode;
98 }
99
100 return 0;
101}
102
41ce1456
RQ		 103static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
104static int dwc3_event_buffers_setup(struct dwc3 *dwc);
105
106static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
3140e8cb
SAS		 107{
108 u32 reg;
109
110 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
111 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
112 reg |= DWC3_GCTL_PRTCAPDIR(mode);
113 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
41ce1456
RQ		 114}
115
116static void __dwc3_set_mode(struct work_struct *work)
117{
118 struct dwc3 *dwc = work_to_dwc(work);
119 unsigned long flags;
120 int ret;
121
122 if (!dwc->desired_dr_role)
123 return;
124
125 if (dwc->desired_dr_role == dwc->current_dr_role)
126 return;
127
128 if (dwc->dr_mode != USB_DR_MODE_OTG)
129 return;
130
131 switch (dwc->current_dr_role) {
132 case DWC3_GCTL_PRTCAP_HOST:
133 dwc3_host_exit(dwc);
134 break;
135 case DWC3_GCTL_PRTCAP_DEVICE:
136 dwc3_gadget_exit(dwc);
137 dwc3_event_buffers_cleanup(dwc);
138 break;
139 default:
140 break;
141 }
142
143 spin_lock_irqsave(&dwc->lock, flags);
144
145 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
6b3261a2 146
41ce1456
RQ		 147 dwc->current_dr_role = dwc->desired_dr_role;
148
149 spin_unlock_irqrestore(&dwc->lock, flags);
150
151 switch (dwc->desired_dr_role) {
152 case DWC3_GCTL_PRTCAP_HOST:
153 ret = dwc3_host_init(dwc);
958d1a4c 154 if (ret) {
41ce1456 155 dev_err(dwc->dev, "failed to initialize host\n");
958d1a4c
FB		 156 } else {
157 if (dwc->usb2_phy)
158 otg_set_vbus(dwc->usb2_phy->otg, true);
159 if (dwc->usb2_generic_phy)
160 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
161
162 }
41ce1456
RQ		 163 break;
164 case DWC3_GCTL_PRTCAP_DEVICE:
165 dwc3_event_buffers_setup(dwc);
958d1a4c
FB		 166
167 if (dwc->usb2_phy)
168 otg_set_vbus(dwc->usb2_phy->otg, false);
169 if (dwc->usb2_generic_phy)
170 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
171
41ce1456
RQ		 172 ret = dwc3_gadget_init(dwc);
173 if (ret)
174 dev_err(dwc->dev, "failed to initialize peripheral\n");
175 break;
176 default:
177 break;
178 }
179}
180
181void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
182{
183 unsigned long flags;
184
185 spin_lock_irqsave(&dwc->lock, flags);
186 dwc->desired_dr_role = mode;
187 spin_unlock_irqrestore(&dwc->lock, flags);
188
189 queue_work(system_power_efficient_wq, &dwc->drd_work);
3140e8cb 190}
8300dd23 191
cf6d867d
FB		 192u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
193{
194 struct dwc3 *dwc = dep->dwc;
195 u32 reg;
196
197 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
198 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
199 DWC3_GDBGFIFOSPACE_TYPE(type));
200
201 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
202
203 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
204}
205
72246da4
FB		 206/**
207 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
208 * @dwc: pointer to our context structure
209 */
57303488 210static int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 211{
212 u32 reg;
f59dcab1 213 int retries = 1000;
57303488 214 int ret;
72246da4 215
51e1e7bc
FB		 216 usb_phy_init(dwc->usb2_phy);
217 usb_phy_init(dwc->usb3_phy);
57303488
KVA		 218 ret = phy_init(dwc->usb2_generic_phy);
219 if (ret < 0)
220 return ret;
221
222 ret = phy_init(dwc->usb3_generic_phy);
223 if (ret < 0) {
224 phy_exit(dwc->usb2_generic_phy);
225 return ret;
226 }
72246da4 227
f59dcab1
FB		 228 /*
229 * We're resetting only the device side because, if we're in host mode,
230 * XHCI driver will reset the host block. If dwc3 was configured for
231 * host-only mode, then we can return early.
232 */
233 if (dwc->dr_mode == USB_DR_MODE_HOST)
234 return 0;
72246da4 235
f59dcab1
FB		 236 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
237 reg |= DWC3_DCTL_CSFTRST;
238 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 239
f59dcab1
FB		 240 do {
241 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
242 if (!(reg & DWC3_DCTL_CSFTRST))
243 return 0;
45627ac6 244
f59dcab1
FB		 245 udelay(1);
246 } while (--retries);
57303488 247
f59dcab1 248 return -ETIMEDOUT;
72246da4
FB		 249}
250
db2be4e9
NB		 251/*
252 * dwc3_frame_length_adjustment - Adjusts frame length if required
253 * @dwc3: Pointer to our controller context structure
db2be4e9 254 */
bcdb3272 255static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 256{
257 u32 reg;
258 u32 dft;
259
260 if (dwc->revision < DWC3_REVISION_250A)
261 return;
262
bcdb3272 263 if (dwc->fladj == 0)
db2be4e9
NB		 264 return;
265
266 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
267 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 268 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
db2be4e9
NB		 269 "request value same as default, ignoring\n")) {
270 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 271 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 272 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
273 }
274}
275
72246da4
FB		 276/**
277 * dwc3_free_one_event_buffer - Frees one event buffer
278 * @dwc: Pointer to our controller context structure
279 * @evt: Pointer to event buffer to be freed
280 */
281static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
282 struct dwc3_event_buffer *evt)
283{
d64ff406 284 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
72246da4
FB		 285}
286
287/**
1d046793 288 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 289 * @dwc: Pointer to our controller context structure
290 * @length: size of the event buffer
291 *
1d046793 292 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 293 * otherwise ERR_PTR(errno).
294 */
67d0b500
FB		 295static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
296 unsigned length)
72246da4
FB		 297{
298 struct dwc3_event_buffer *evt;
299
380f0d28 300 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 301 if (!evt)
302 return ERR_PTR(-ENOMEM);
303
304 evt->dwc = dwc;
305 evt->length = length;
d9fa4c63
JY		 306 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
307 if (!evt->cache)
308 return ERR_PTR(-ENOMEM);
309
d64ff406 310 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
72246da4 311 &evt->dma, GFP_KERNEL);
e32672f0 312 if (!evt->buf)
72246da4 313 return ERR_PTR(-ENOMEM);
72246da4
FB		 314
315 return evt;
316}
317
318/**
319 * dwc3_free_event_buffers - frees all allocated event buffers
320 * @dwc: Pointer to our controller context structure
321 */
322static void dwc3_free_event_buffers(struct dwc3 *dwc)
323{
324 struct dwc3_event_buffer *evt;
72246da4 325
696c8b12 326 evt = dwc->ev_buf;
660e9bde
FB		 327 if (evt)
328 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 329}
330
331/**
332 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 333 * @dwc: pointer to our controller context structure
72246da4
FB		 334 * @length: size of event buffer
335 *
1d046793 336 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 337 * may contain some buffers allocated but not all which were requested.
338 */
41ac7b3a 339static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4 340{
660e9bde 341 struct dwc3_event_buffer *evt;
72246da4 342
660e9bde
FB		 343 evt = dwc3_alloc_one_event_buffer(dwc, length);
344 if (IS_ERR(evt)) {
345 dev_err(dwc->dev, "can't allocate event buffer\n");
346 return PTR_ERR(evt);
72246da4 347 }
696c8b12 348 dwc->ev_buf = evt;
72246da4
FB		 349
350 return 0;
351}
352
353/**
354 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 355 * @dwc: pointer to our controller context structure
72246da4
FB		 356 *
357 * Returns 0 on success otherwise negative errno.
358 */
7acd85e0 359static int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 360{
361 struct dwc3_event_buffer *evt;
72246da4 362
696c8b12 363 evt = dwc->ev_buf;
660e9bde 364 evt->lpos = 0;
660e9bde
FB		 365 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
366 lower_32_bits(evt->dma));
367 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
368 upper_32_bits(evt->dma));
369 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
370 DWC3_GEVNTSIZ_SIZE(evt->length));
371 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 372
373 return 0;
374}
375
376static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
377{
378 struct dwc3_event_buffer *evt;
72246da4 379
696c8b12 380 evt = dwc->ev_buf;
7acd85e0 381
660e9bde 382 evt->lpos = 0;
7acd85e0 383
660e9bde
FB		 384 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
385 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
386 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
387 | DWC3_GEVNTSIZ_SIZE(0));
388 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 389}
390
0ffcaf37
FB		 391static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
392{
393 if (!dwc->has_hibernation)
394 return 0;
395
396 if (!dwc->nr_scratch)
397 return 0;
398
399 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
400 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
401 if (!dwc->scratchbuf)
402 return -ENOMEM;
403
404 return 0;
405}
406
407static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
408{
409 dma_addr_t scratch_addr;
410 u32 param;
411 int ret;
412
413 if (!dwc->has_hibernation)
414 return 0;
415
416 if (!dwc->nr_scratch)
417 return 0;
418
419 /* should never fall here */
420 if (!WARN_ON(dwc->scratchbuf))
421 return 0;
422
d64ff406 423 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
0ffcaf37
FB		 424 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
425 DMA_BIDIRECTIONAL);
d64ff406
AB		 426 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
427 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
0ffcaf37
FB		 428 ret = -EFAULT;
429 goto err0;
430 }
431
432 dwc->scratch_addr = scratch_addr;
433
434 param = lower_32_bits(scratch_addr);
435
436 ret = dwc3_send_gadget_generic_command(dwc,
437 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
438 if (ret < 0)
439 goto err1;
440
441 param = upper_32_bits(scratch_addr);
442
443 ret = dwc3_send_gadget_generic_command(dwc,
444 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
445 if (ret < 0)
446 goto err1;
447
448 return 0;
449
450err1:
d64ff406 451 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 452 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
453
454err0:
455 return ret;
456}
457
458static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
459{
460 if (!dwc->has_hibernation)
461 return;
462
463 if (!dwc->nr_scratch)
464 return;
465
466 /* should never fall here */
467 if (!WARN_ON(dwc->scratchbuf))
468 return;
469
d64ff406 470 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 471 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
472 kfree(dwc->scratchbuf);
473}
474
789451f6
FB		 475static void dwc3_core_num_eps(struct dwc3 *dwc)
476{
477 struct dwc3_hwparams *parms = &dwc->hwparams;
478
47d3946e 479 dwc->num_eps = DWC3_NUM_EPS(parms);
789451f6
FB		 480}
481
41ac7b3a 482static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 483{
484 struct dwc3_hwparams *parms = &dwc->hwparams;
485
486 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
487 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
488 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
489 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
490 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
491 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
492 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
493 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
494 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
495}
496
b5a65c40
HR		 497/**
498 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
499 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 500 *
501 * Returns 0 on success. The USB PHY interfaces are configured but not
502 * initialized. The PHY interfaces and the PHYs get initialized together with
503 * the core in dwc3_core_init.
b5a65c40 504 */
88bc9d19 505static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40
HR		 506{
507 u32 reg;
88bc9d19 508 int ret;
b5a65c40
HR		 509
510 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
511
1966b865
FB		 512 /*
513 * Make sure UX_EXIT_PX is cleared as that causes issues with some
514 * PHYs. Also, this bit is not supposed to be used in normal operation.
515 */
516 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
517
2164a476
HR		 518 /*
519 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
520 * to '0' during coreConsultant configuration. So default value
521 * will be '0' when the core is reset. Application needs to set it
522 * to '1' after the core initialization is completed.
523 */
524 if (dwc->revision > DWC3_REVISION_194A)
525 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
526
b5a65c40
HR		 527 if (dwc->u2ss_inp3_quirk)
528 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
529
e58dd357
RB		 530 if (dwc->dis_rxdet_inp3_quirk)
531 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
532
df31f5b3
HR		 533 if (dwc->req_p1p2p3_quirk)
534 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
535
a2a1d0f5
HR		 536 if (dwc->del_p1p2p3_quirk)
537 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
538
41c06ffd
HR		 539 if (dwc->del_phy_power_chg_quirk)
540 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
541
fb67afca
HR		 542 if (dwc->lfps_filter_quirk)
543 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
544
14f4ac53
HR		 545 if (dwc->rx_detect_poll_quirk)
546 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
547
6b6a0c9a
HR		 548 if (dwc->tx_de_emphasis_quirk)
549 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
550
cd72f890 551 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 552 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
553
00fe081d
WW		 554 if (dwc->dis_del_phy_power_chg_quirk)
555 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
556
b5a65c40
HR		 557 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
558
2164a476
HR		 559 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
560
3e10a2ce
HK		 561 /* Select the HS PHY interface */
562 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
563 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 564 if (dwc->hsphy_interface &&
565 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 566 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 567 break;
43cacb03
FB		 568 } else if (dwc->hsphy_interface &&
569 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 570 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 571 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 572 } else {
88bc9d19
HK		 573 /* Relying on default value. */
574 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
575 break;
3e10a2ce
HK		 576 }
577 /* FALLTHROUGH */
88bc9d19 578 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
88bc9d19
HK		 579 ret = dwc3_ulpi_init(dwc);
580 if (ret)
581 return ret;
582 /* FALLTHROUGH */
3e10a2ce
HK		 583 default:
584 break;
585 }
586
32f2ed86
WW		 587 switch (dwc->hsphy_mode) {
588 case USBPHY_INTERFACE_MODE_UTMI:
589 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
590 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
591 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
592 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
593 break;
594 case USBPHY_INTERFACE_MODE_UTMIW:
595 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
596 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
597 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
598 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
599 break;
600 default:
601 break;
602 }
603
2164a476
HR		 604 /*
605 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
606 * '0' during coreConsultant configuration. So default value will
607 * be '0' when the core is reset. Application needs to set it to
608 * '1' after the core initialization is completed.
609 */
610 if (dwc->revision > DWC3_REVISION_194A)
611 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
612
cd72f890 613 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 614 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
615
ec791d14
JY		 616 if (dwc->dis_enblslpm_quirk)
617 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
618
16199f33
WW		 619 if (dwc->dis_u2_freeclk_exists_quirk)
620 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
621
2164a476 622 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 623
624 return 0;
b5a65c40
HR		 625}
626
c499ff71
FB		 627static void dwc3_core_exit(struct dwc3 *dwc)
628{
629 dwc3_event_buffers_cleanup(dwc);
630
631 usb_phy_shutdown(dwc->usb2_phy);
632 usb_phy_shutdown(dwc->usb3_phy);
633 phy_exit(dwc->usb2_generic_phy);
634 phy_exit(dwc->usb3_generic_phy);
635
636 usb_phy_set_suspend(dwc->usb2_phy, 1);
637 usb_phy_set_suspend(dwc->usb3_phy, 1);
638 phy_power_off(dwc->usb2_generic_phy);
639 phy_power_off(dwc->usb3_generic_phy);
640}
641
0759956f 642static bool dwc3_core_is_valid(struct dwc3 *dwc)
72246da4 643{
0759956f 644 u32 reg;
72246da4 645
7650bd74 646 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
0759956f 647
7650bd74 648 /* This should read as U3 followed by revision number */
690fb371
JY		 649 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
650 /* Detected DWC_usb3 IP */
651 dwc->revision = reg;
652 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
653 /* Detected DWC_usb31 IP */
654 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
655 dwc->revision |= DWC3_REVISION_IS_DWC31;
656 } else {
0759956f 657 return false;
7650bd74 658 }
7650bd74 659
0759956f
FB		 660 return true;
661}
58a0f23f 662
941f918e 663static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0759956f 664{
941f918e
FB		 665 u32 hwparams4 = dwc->hwparams.hwparams4;
666 u32 reg;
c499ff71 667
4878a028 668 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 669 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 670
164d7731 671 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 672 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 673 /**
674 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
675 * issue which would cause xHCI compliance tests to fail.
676 *
677 * Because of that we cannot enable clock gating on such
678 * configurations.
679 *
680 * Refers to:
681 *
682 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
683 * SOF/ITP Mode Used
684 */
685 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
686 dwc->dr_mode == USB_DR_MODE_OTG) &&
687 (dwc->revision >= DWC3_REVISION_210A &&
688 dwc->revision <= DWC3_REVISION_250A))
689 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
690 else
691 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 692 break;
0ffcaf37
FB		 693 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
694 /* enable hibernation here */
695 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
2eac3992
HR		 696
697 /*
698 * REVISIT Enabling this bit so that host-mode hibernation
699 * will work. Device-mode hibernation is not yet implemented.
700 */
701 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 702 break;
4878a028 703 default:
5eb30ced
FB		 704 /* nothing */
705 break;
4878a028
SAS		 706 }
707
946bd579
HR		 708 /* check if current dwc3 is on simulation board */
709 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
5eb30ced 710 dev_info(dwc->dev, "Running with FPGA optmizations\n");
946bd579
HR		 711 dwc->is_fpga = true;
712 }
713
3b81221a
HR		 714 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
715 "disable_scramble cannot be used on non-FPGA builds\n");
716
717 if (dwc->disable_scramble_quirk && dwc->is_fpga)
718 reg |= DWC3_GCTL_DISSCRAMBLE;
719 else
720 reg &= ~DWC3_GCTL_DISSCRAMBLE;
721
9a5b2f31
HR		 722 if (dwc->u2exit_lfps_quirk)
723 reg |= DWC3_GCTL_U2EXIT_LFPS;
724
4878a028
SAS		 725 /*
726 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 727 * where the device can fail to connect at SuperSpeed
4878a028 728 * and falls back to high-speed mode which causes
1d046793 729 * the device to enter a Connect/Disconnect loop
4878a028
SAS		 730 */
731 if (dwc->revision < DWC3_REVISION_190A)
732 reg |= DWC3_GCTL_U2RSTECN;
733
734 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941f918e
FB		 735}
736
f54edb53
FB		 737static int dwc3_core_get_phy(struct dwc3 *dwc);
738
941f918e
FB		 739/**
740 * dwc3_core_init - Low-level initialization of DWC3 Core
741 * @dwc: Pointer to our controller context structure
742 *
743 * Returns 0 on success otherwise negative errno.
744 */
745static int dwc3_core_init(struct dwc3 *dwc)
746{
747 u32 reg;
748 int ret;
749
750 if (!dwc3_core_is_valid(dwc)) {
751 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
752 ret = -ENODEV;
753 goto err0;
754 }
755
756 /*
757 * Write Linux Version Code to our GUID register so it's easy to figure
758 * out which kernel version a bug was found.
759 */
760 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
761
762 /* Handle USB2.0-only core configuration */
763 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
764 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
765 if (dwc->maximum_speed == USB_SPEED_SUPER)
766 dwc->maximum_speed = USB_SPEED_HIGH;
767 }
768
541768b0 769 ret = dwc3_core_get_phy(dwc);
941f918e
FB		 770 if (ret)
771 goto err0;
4878a028 772
541768b0 773 ret = dwc3_core_soft_reset(dwc);
941f918e
FB		 774 if (ret)
775 goto err0;
4878a028 776
541768b0 777 ret = dwc3_phy_setup(dwc);
f54edb53
FB		 778 if (ret)
779 goto err0;
780
941f918e 781 dwc3_core_setup_global_control(dwc);
c499ff71 782 dwc3_core_num_eps(dwc);
0ffcaf37
FB		 783
784 ret = dwc3_setup_scratch_buffers(dwc);
785 if (ret)
c499ff71
FB		 786 goto err1;
787
788 /* Adjust Frame Length */
789 dwc3_frame_length_adjustment(dwc);
790
791 usb_phy_set_suspend(dwc->usb2_phy, 0);
792 usb_phy_set_suspend(dwc->usb3_phy, 0);
793 ret = phy_power_on(dwc->usb2_generic_phy);
794 if (ret < 0)
0ffcaf37
FB		 795 goto err2;
796
c499ff71
FB		 797 ret = phy_power_on(dwc->usb3_generic_phy);
798 if (ret < 0)
799 goto err3;
800
801 ret = dwc3_event_buffers_setup(dwc);
802 if (ret) {
803 dev_err(dwc->dev, "failed to setup event buffers\n");
804 goto err4;
805 }
806
06281d46
JY		 807 /*
808 * ENDXFER polling is available on version 3.10a and later of
809 * the DWC_usb3 controller. It is NOT available in the
810 * DWC_usb31 controller.
811 */
812 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
813 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
814 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
815 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
816 }
817
65db7a0c 818 if (dwc->revision >= DWC3_REVISION_250A) {
0bb39ca1 819 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
65db7a0c
WW		 820
821 /*
822 * Enable hardware control of sending remote wakeup
823 * in HS when the device is in the L1 state.
824 */
825 if (dwc->revision >= DWC3_REVISION_290A)
826 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
827
828 if (dwc->dis_tx_ipgap_linecheck_quirk)
829 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
830
0bb39ca1
JY		 831 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
832 }
833
72246da4
FB		 834 return 0;
835
c499ff71 836err4:
9b9d7cdd 837 phy_power_off(dwc->usb3_generic_phy);
c499ff71
FB		 838
839err3:
9b9d7cdd 840 phy_power_off(dwc->usb2_generic_phy);
c499ff71 841
0ffcaf37 842err2:
c499ff71
FB		 843 usb_phy_set_suspend(dwc->usb2_phy, 1);
844 usb_phy_set_suspend(dwc->usb3_phy, 1);
0ffcaf37
FB		 845
846err1:
847 usb_phy_shutdown(dwc->usb2_phy);
848 usb_phy_shutdown(dwc->usb3_phy);
57303488
KVA		 849 phy_exit(dwc->usb2_generic_phy);
850 phy_exit(dwc->usb3_generic_phy);
0ffcaf37 851
72246da4
FB		 852err0:
853 return ret;
854}
855
3c9f94ac 856static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 857{
3c9f94ac 858 struct device *dev = dwc->dev;
941ea361 859 struct device_node *node = dev->of_node;
3c9f94ac 860 int ret;
72246da4 861
5088b6f5
KVA		 862 if (node) {
863 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
864 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 865 } else {
866 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
867 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 868 }
869
d105e7f8
FB		 870 if (IS_ERR(dwc->usb2_phy)) {
871 ret = PTR_ERR(dwc->usb2_phy);
122f06e6
KVA		 872 if (ret == -ENXIO || ret == -ENODEV) {
873 dwc->usb2_phy = NULL;
874 } else if (ret == -EPROBE_DEFER) {
d105e7f8 875 return ret;
122f06e6
KVA		 876 } else {
877 dev_err(dev, "no usb2 phy configured\n");
878 return ret;
879 }
51e1e7bc
FB		 880 }
881
d105e7f8 882 if (IS_ERR(dwc->usb3_phy)) {
315955d7 883 ret = PTR_ERR(dwc->usb3_phy);
122f06e6
KVA		 884 if (ret == -ENXIO || ret == -ENODEV) {
885 dwc->usb3_phy = NULL;
886 } else if (ret == -EPROBE_DEFER) {
d105e7f8 887 return ret;
122f06e6
KVA		 888 } else {
889 dev_err(dev, "no usb3 phy configured\n");
890 return ret;
891 }
51e1e7bc
FB		 892 }
893
57303488
KVA		 894 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
895 if (IS_ERR(dwc->usb2_generic_phy)) {
896 ret = PTR_ERR(dwc->usb2_generic_phy);
897 if (ret == -ENOSYS || ret == -ENODEV) {
898 dwc->usb2_generic_phy = NULL;
899 } else if (ret == -EPROBE_DEFER) {
900 return ret;
901 } else {
902 dev_err(dev, "no usb2 phy configured\n");
903 return ret;
904 }
905 }
906
907 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
908 if (IS_ERR(dwc->usb3_generic_phy)) {
909 ret = PTR_ERR(dwc->usb3_generic_phy);
910 if (ret == -ENOSYS || ret == -ENODEV) {
911 dwc->usb3_generic_phy = NULL;
912 } else if (ret == -EPROBE_DEFER) {
913 return ret;
914 } else {
915 dev_err(dev, "no usb3 phy configured\n");
916 return ret;
917 }
918 }
919
3c9f94ac
FB		 920 return 0;
921}
922
5f94adfe
FB		 923static int dwc3_core_init_mode(struct dwc3 *dwc)
924{
925 struct device *dev = dwc->dev;
926 int ret;
927
928 switch (dwc->dr_mode) {
929 case USB_DR_MODE_PERIPHERAL:
41ce1456 930 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
958d1a4c
FB		 931
932 if (dwc->usb2_phy)
933 otg_set_vbus(dwc->usb2_phy->otg, false);
934 if (dwc->usb2_generic_phy)
935 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
936
5f94adfe
FB		 937 ret = dwc3_gadget_init(dwc);
938 if (ret) {
9522def4
RQ		 939 if (ret != -EPROBE_DEFER)
940 dev_err(dev, "failed to initialize gadget\n");
5f94adfe
FB		 941 return ret;
942 }
943 break;
944 case USB_DR_MODE_HOST:
41ce1456 945 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
958d1a4c
FB		 946
947 if (dwc->usb2_phy)
948 otg_set_vbus(dwc->usb2_phy->otg, true);
949 if (dwc->usb2_generic_phy)
950 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
951
5f94adfe
FB		 952 ret = dwc3_host_init(dwc);
953 if (ret) {
9522def4
RQ		 954 if (ret != -EPROBE_DEFER)
955 dev_err(dev, "failed to initialize host\n");
5f94adfe
FB		 956 return ret;
957 }
958 break;
959 case USB_DR_MODE_OTG:
41ce1456 960 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
9840354f
RQ		 961 ret = dwc3_drd_init(dwc);
962 if (ret) {
963 if (ret != -EPROBE_DEFER)
964 dev_err(dev, "failed to initialize dual-role\n");
965 return ret;
966 }
5f94adfe
FB		 967 break;
968 default:
969 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
970 return -EINVAL;
971 }
972
973 return 0;
974}
975
976static void dwc3_core_exit_mode(struct dwc3 *dwc)
977{
978 switch (dwc->dr_mode) {
979 case USB_DR_MODE_PERIPHERAL:
980 dwc3_gadget_exit(dwc);
981 break;
982 case USB_DR_MODE_HOST:
983 dwc3_host_exit(dwc);
984 break;
985 case USB_DR_MODE_OTG:
9840354f 986 dwc3_drd_exit(dwc);
5f94adfe
FB		 987 break;
988 default:
989 /* do nothing */
990 break;
991 }
992}
993
c5ac6116 994static void dwc3_get_properties(struct dwc3 *dwc)
3c9f94ac 995{
c5ac6116 996 struct device *dev = dwc->dev;
80caf7d2 997 u8 lpm_nyet_threshold;
6b6a0c9a 998 u8 tx_de_emphasis;
460d098c 999 u8 hird_threshold;
3c9f94ac 1000
80caf7d2
HR		 1001 /* default to highest possible threshold */
1002 lpm_nyet_threshold = 0xff;
1003
6b6a0c9a
HR		 1004 /* default to -3.5dB de-emphasis */
1005 tx_de_emphasis = 1;
1006
460d098c
HR		 1007 /*
1008 * default to assert utmi_sleep_n and use maximum allowed HIRD
1009 * threshold value of 0b1100
1010 */
1011 hird_threshold = 12;
1012
63863b98 1013 dwc->maximum_speed = usb_get_maximum_speed(dev);
06e7114f 1014 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 1015 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 1016
d64ff406
AB		 1017 dwc->sysdev_is_parent = device_property_read_bool(dev,
1018 "linux,sysdev_is_parent");
1019 if (dwc->sysdev_is_parent)
1020 dwc->sysdev = dwc->dev->parent;
1021 else
1022 dwc->sysdev = dwc->dev;
1023
3d128919 1024 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 1025 "snps,has-lpm-erratum");
3d128919 1026 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 1027 &lpm_nyet_threshold);
3d128919 1028 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 1029 "snps,is-utmi-l1-suspend");
3d128919 1030 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 1031 &hird_threshold);
3d128919 1032 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 1033 "snps,usb3_lpm_capable");
3c9f94ac 1034
3d128919 1035 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 1036 "snps,disable_scramble_quirk");
3d128919 1037 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 1038 "snps,u2exit_lfps_quirk");
3d128919 1039 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 1040 "snps,u2ss_inp3_quirk");
3d128919 1041 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 1042 "snps,req_p1p2p3_quirk");
3d128919 1043 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 1044 "snps,del_p1p2p3_quirk");
3d128919 1045 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 1046 "snps,del_phy_power_chg_quirk");
3d128919 1047 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 1048 "snps,lfps_filter_quirk");
3d128919 1049 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 1050 "snps,rx_detect_poll_quirk");
3d128919 1051 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 1052 "snps,dis_u3_susphy_quirk");
3d128919 1053 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 1054 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 1055 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1056 "snps,dis_enblslpm_quirk");
e58dd357
RB		 1057 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1058 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 1059 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1060 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 1061 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1062 "snps,dis-del-phy-power-chg-quirk");
65db7a0c
WW		 1063 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1064 "snps,dis-tx-ipgap-linecheck-quirk");
6b6a0c9a 1065
3d128919 1066 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 1067 "snps,tx_de_emphasis_quirk");
3d128919 1068 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 1069 &tx_de_emphasis);
3d128919
HK		 1070 device_property_read_string(dev, "snps,hsphy_interface",
1071 &dwc->hsphy_interface);
1072 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 1073 &dwc->fladj);
3d128919 1074
80caf7d2 1075 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 1076 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 1077
460d098c
HR		 1078 dwc->hird_threshold = hird_threshold
1079 | (dwc->is_utmi_l1_suspend << 4);
1080
cf40b86b
JY		 1081 dwc->imod_interval = 0;
1082}
1083
1084/* check whether the core supports IMOD */
1085bool dwc3_has_imod(struct dwc3 *dwc)
1086{
1087 return ((dwc3_is_usb3(dwc) &&
1088 dwc->revision >= DWC3_REVISION_300A) ||
1089 (dwc3_is_usb31(dwc) &&
1090 dwc->revision >= DWC3_USB31_REVISION_120A));
c5ac6116
FB		 1091}
1092
7ac51a12
JY		 1093static void dwc3_check_params(struct dwc3 *dwc)
1094{
1095 struct device *dev = dwc->dev;
1096
cf40b86b
JY		 1097 /* Check for proper value of imod_interval */
1098 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1099 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1100 dwc->imod_interval = 0;
1101 }
1102
28632b44
JY		 1103 /*
1104 * Workaround for STAR 9000961433 which affects only version
1105 * 3.00a of the DWC_usb3 core. This prevents the controller
1106 * interrupt from being masked while handling events. IMOD
1107 * allows us to work around this issue. Enable it for the
1108 * affected version.
1109 */
1110 if (!dwc->imod_interval &&
1111 (dwc->revision == DWC3_REVISION_300A))
1112 dwc->imod_interval = 1;
1113
7ac51a12
JY		 1114 /* Check the maximum_speed parameter */
1115 switch (dwc->maximum_speed) {
1116 case USB_SPEED_LOW:
1117 case USB_SPEED_FULL:
1118 case USB_SPEED_HIGH:
1119 case USB_SPEED_SUPER:
1120 case USB_SPEED_SUPER_PLUS:
1121 break;
1122 default:
1123 dev_err(dev, "invalid maximum_speed parameter %d\n",
1124 dwc->maximum_speed);
1125 /* fall through */
1126 case USB_SPEED_UNKNOWN:
1127 /* default to superspeed */
1128 dwc->maximum_speed = USB_SPEED_SUPER;
1129
1130 /*
1131 * default to superspeed plus if we are capable.
1132 */
1133 if (dwc3_is_usb31(dwc) &&
1134 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1135 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1136 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1137
1138 break;
1139 }
1140}
1141
c5ac6116
FB		 1142static int dwc3_probe(struct platform_device *pdev)
1143{
1144 struct device *dev = &pdev->dev;
1145 struct resource *res;
1146 struct dwc3 *dwc;
1147
1148 int ret;
1149
1150 void __iomem *regs;
1151
1152 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1153 if (!dwc)
1154 return -ENOMEM;
1155
1156 dwc->dev = dev;
1157
1158 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1159 if (!res) {
1160 dev_err(dev, "missing memory resource\n");
1161 return -ENODEV;
1162 }
1163
1164 dwc->xhci_resources[0].start = res->start;
1165 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1166 DWC3_XHCI_REGS_END;
1167 dwc->xhci_resources[0].flags = res->flags;
1168 dwc->xhci_resources[0].name = res->name;
1169
1170 res->start += DWC3_GLOBALS_REGS_START;
1171
1172 /*
1173 * Request memory region but exclude xHCI regs,
1174 * since it will be requested by the xhci-plat driver.
1175 */
1176 regs = devm_ioremap_resource(dev, res);
1177 if (IS_ERR(regs)) {
1178 ret = PTR_ERR(regs);
1179 goto err0;
1180 }
1181
1182 dwc->regs = regs;
1183 dwc->regs_size = resource_size(res);
1184
1185 dwc3_get_properties(dwc);
1186
6c89cce0 1187 platform_set_drvdata(pdev, dwc);
2917e718 1188 dwc3_cache_hwparams(dwc);
6c89cce0 1189
72246da4 1190 spin_lock_init(&dwc->lock);
72246da4 1191
fc8bb91b
FB		 1192 pm_runtime_set_active(dev);
1193 pm_runtime_use_autosuspend(dev);
1194 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 1195 pm_runtime_enable(dev);
32808237
RQ		 1196 ret = pm_runtime_get_sync(dev);
1197 if (ret < 0)
1198 goto err1;
1199
802ca850 1200 pm_runtime_forbid(dev);
72246da4 1201
3921426b
FB		 1202 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1203 if (ret) {
1204 dev_err(dwc->dev, "failed to allocate event buffers\n");
1205 ret = -ENOMEM;
32808237 1206 goto err2;
3921426b
FB		 1207 }
1208
9d6173e1
TN		 1209 ret = dwc3_get_dr_mode(dwc);
1210 if (ret)
1211 goto err3;
32a4a135 1212
c499ff71
FB		 1213 ret = dwc3_alloc_scratch_buffers(dwc);
1214 if (ret)
32808237 1215 goto err3;
c499ff71 1216
72246da4
FB		 1217 ret = dwc3_core_init(dwc);
1218 if (ret) {
802ca850 1219 dev_err(dev, "failed to initialize core\n");
32808237 1220 goto err4;
72246da4
FB		 1221 }
1222
7ac51a12 1223 dwc3_check_params(dwc);
2c7f1bd9 1224
5f94adfe
FB		 1225 ret = dwc3_core_init_mode(dwc);
1226 if (ret)
32808237 1227 goto err5;
72246da4 1228
4e9f3118 1229 dwc3_debugfs_init(dwc);
fc8bb91b 1230 pm_runtime_put(dev);
72246da4
FB		 1231
1232 return 0;
1233
32808237 1234err5:
c499ff71 1235 dwc3_event_buffers_cleanup(dwc);
57303488 1236
32808237 1237err4:
c499ff71 1238 dwc3_free_scratch_buffers(dwc);
72246da4 1239
32808237 1240err3:
3921426b 1241 dwc3_free_event_buffers(dwc);
88bc9d19 1242 dwc3_ulpi_exit(dwc);
3921426b 1243
32808237
RQ		 1244err2:
1245 pm_runtime_allow(&pdev->dev);
1246
1247err1:
1248 pm_runtime_put_sync(&pdev->dev);
1249 pm_runtime_disable(&pdev->dev);
1250
3da1f6ee
FB		 1251err0:
1252 /*
1253 * restore res->start back to its original value so that, in case the
1254 * probe is deferred, we don't end up getting error in request the
1255 * memory region the next time probe is called.
1256 */
1257 res->start -= DWC3_GLOBALS_REGS_START;
1258
72246da4
FB		 1259 return ret;
1260}
1261
fb4e98ab 1262static int dwc3_remove(struct platform_device *pdev)
72246da4 1263{
72246da4 1264 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee
FB		 1265 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1266
fc8bb91b 1267 pm_runtime_get_sync(&pdev->dev);
3da1f6ee
FB		 1268 /*
1269 * restore res->start back to its original value so that, in case the
1270 * probe is deferred, we don't end up getting error in request the
1271 * memory region the next time probe is called.
1272 */
1273 res->start -= DWC3_GLOBALS_REGS_START;
72246da4 1274
dc99f16f
FB		 1275 dwc3_debugfs_exit(dwc);
1276 dwc3_core_exit_mode(dwc);
8ba007a9 1277
72246da4 1278 dwc3_core_exit(dwc);
88bc9d19 1279 dwc3_ulpi_exit(dwc);
72246da4 1280
16b972a5 1281 pm_runtime_put_sync(&pdev->dev);
fc8bb91b 1282 pm_runtime_allow(&pdev->dev);
72246da4
FB		 1283 pm_runtime_disable(&pdev->dev);
1284
fc8bb91b
FB		 1285 dwc3_free_event_buffers(dwc);
1286 dwc3_free_scratch_buffers(dwc);
1287
72246da4
FB		 1288 return 0;
1289}
1290
fc8bb91b
FB		 1291#ifdef CONFIG_PM
1292static int dwc3_suspend_common(struct dwc3 *dwc)
7415f17c 1293{
fc8bb91b 1294 unsigned long flags;
7415f17c 1295
a45c82b8
RK		 1296 switch (dwc->dr_mode) {
1297 case USB_DR_MODE_PERIPHERAL:
1298 case USB_DR_MODE_OTG:
fc8bb91b 1299 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1300 dwc3_gadget_suspend(dwc);
fc8bb91b 1301 spin_unlock_irqrestore(&dwc->lock, flags);
51f5d49a 1302 break;
a45c82b8 1303 case USB_DR_MODE_HOST:
7415f17c 1304 default:
51f5d49a 1305 /* do nothing */
7415f17c
FB		 1306 break;
1307 }
1308
51f5d49a 1309 dwc3_core_exit(dwc);
5c4ad318 1310
7415f17c
FB		 1311 return 0;
1312}
1313
fc8bb91b 1314static int dwc3_resume_common(struct dwc3 *dwc)
7415f17c 1315{
fc8bb91b 1316 unsigned long flags;
57303488 1317 int ret;
7415f17c 1318
51f5d49a
FB		 1319 ret = dwc3_core_init(dwc);
1320 if (ret)
5c4ad318
FB		 1321 return ret;
1322
a45c82b8
RK		 1323 switch (dwc->dr_mode) {
1324 case USB_DR_MODE_PERIPHERAL:
1325 case USB_DR_MODE_OTG:
fc8bb91b 1326 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1327 dwc3_gadget_resume(dwc);
fc8bb91b 1328 spin_unlock_irqrestore(&dwc->lock, flags);
7415f17c 1329 /* FALLTHROUGH */
a45c82b8 1330 case USB_DR_MODE_HOST:
7415f17c
FB		 1331 default:
1332 /* do nothing */
1333 break;
1334 }
1335
fc8bb91b
FB		 1336 return 0;
1337}
1338
1339static int dwc3_runtime_checks(struct dwc3 *dwc)
1340{
1341 switch (dwc->dr_mode) {
1342 case USB_DR_MODE_PERIPHERAL:
1343 case USB_DR_MODE_OTG:
1344 if (dwc->connected)
1345 return -EBUSY;
1346 break;
1347 case USB_DR_MODE_HOST:
1348 default:
1349 /* do nothing */
1350 break;
1351 }
1352
1353 return 0;
1354}
1355
1356static int dwc3_runtime_suspend(struct device *dev)
1357{
1358 struct dwc3 *dwc = dev_get_drvdata(dev);
1359 int ret;
1360
1361 if (dwc3_runtime_checks(dwc))
1362 return -EBUSY;
1363
1364 ret = dwc3_suspend_common(dwc);
1365 if (ret)
1366 return ret;
1367
1368 device_init_wakeup(dev, true);
1369
1370 return 0;
1371}
1372
1373static int dwc3_runtime_resume(struct device *dev)
1374{
1375 struct dwc3 *dwc = dev_get_drvdata(dev);
1376 int ret;
1377
1378 device_init_wakeup(dev, false);
1379
1380 ret = dwc3_resume_common(dwc);
1381 if (ret)
1382 return ret;
1383
1384 switch (dwc->dr_mode) {
1385 case USB_DR_MODE_PERIPHERAL:
1386 case USB_DR_MODE_OTG:
1387 dwc3_gadget_process_pending_events(dwc);
1388 break;
1389 case USB_DR_MODE_HOST:
1390 default:
1391 /* do nothing */
1392 break;
1393 }
1394
1395 pm_runtime_mark_last_busy(dev);
b74c2d87 1396 pm_runtime_put(dev);
fc8bb91b
FB		 1397
1398 return 0;
1399}
1400
1401static int dwc3_runtime_idle(struct device *dev)
1402{
1403 struct dwc3 *dwc = dev_get_drvdata(dev);
1404
1405 switch (dwc->dr_mode) {
1406 case USB_DR_MODE_PERIPHERAL:
1407 case USB_DR_MODE_OTG:
1408 if (dwc3_runtime_checks(dwc))
1409 return -EBUSY;
1410 break;
1411 case USB_DR_MODE_HOST:
1412 default:
1413 /* do nothing */
1414 break;
1415 }
1416
1417 pm_runtime_mark_last_busy(dev);
1418 pm_runtime_autosuspend(dev);
1419
1420 return 0;
1421}
1422#endif /* CONFIG_PM */
1423
1424#ifdef CONFIG_PM_SLEEP
1425static int dwc3_suspend(struct device *dev)
1426{
1427 struct dwc3 *dwc = dev_get_drvdata(dev);
1428 int ret;
1429
1430 ret = dwc3_suspend_common(dwc);
1431 if (ret)
1432 return ret;
1433
1434 pinctrl_pm_select_sleep_state(dev);
1435
1436 return 0;
1437}
1438
1439static int dwc3_resume(struct device *dev)
1440{
1441 struct dwc3 *dwc = dev_get_drvdata(dev);
1442 int ret;
1443
1444 pinctrl_pm_select_default_state(dev);
1445
1446 ret = dwc3_resume_common(dwc);
1447 if (ret)
1448 return ret;
1449
7415f17c
FB		 1450 pm_runtime_disable(dev);
1451 pm_runtime_set_active(dev);
1452 pm_runtime_enable(dev);
1453
1454 return 0;
1455}
7f370ed0 1456#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 1457
1458static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 1459 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
fc8bb91b
FB		 1460 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1461 dwc3_runtime_idle)
7415f17c
FB		 1462};
1463
5088b6f5
KVA		 1464#ifdef CONFIG_OF
1465static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 1466 {
1467 .compatible = "snps,dwc3"
1468 },
5088b6f5
KVA		 1469 {
1470 .compatible = "synopsys,dwc3"
1471 },
1472 { },
1473};
1474MODULE_DEVICE_TABLE(of, of_dwc3_match);
1475#endif
1476
404905a6
HK		 1477#ifdef CONFIG_ACPI
1478
1479#define ACPI_ID_INTEL_BSW "808622B7"
1480
1481static const struct acpi_device_id dwc3_acpi_match[] = {
1482 { ACPI_ID_INTEL_BSW, 0 },
1483 { },
1484};
1485MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1486#endif
1487
72246da4
FB		 1488static struct platform_driver dwc3_driver = {
1489 .probe = dwc3_probe,
7690417d 1490 .remove = dwc3_remove,
72246da4
FB		 1491 .driver = {
1492 .name = "dwc3",
5088b6f5 1493 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 1494 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 1495 .pm = &dwc3_dev_pm_ops,
72246da4 1496 },
72246da4
FB		 1497};
1498
b1116dcc
TK		 1499module_platform_driver(dwc3_driver);
1500
7ae4fc4d 1501MODULE_ALIAS("platform:dwc3");
72246da4 1502MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 1503MODULE_LICENSE("GPL v2");
72246da4 1504MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)