Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 8 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 | 31 | |
cb06ff10 | 32 | |
1da177e4 LT |
33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
34 | #define SUPPORT_SYSRQ | |
35 | #endif | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/console.h> | |
41 | #include <linux/sysrq.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/tty.h> | |
44 | #include <linux/tty_flip.h> | |
45 | #include <linux/serial_core.h> | |
46 | #include <linux/serial.h> | |
a62c80e5 RK |
47 | #include <linux/amba/bus.h> |
48 | #include <linux/amba/serial.h> | |
f8ce2547 | 49 | #include <linux/clk.h> |
5a0e3ad6 | 50 | #include <linux/slab.h> |
68b65f73 RK |
51 | #include <linux/dmaengine.h> |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/scatterlist.h> | |
c16d51a3 | 54 | #include <linux/delay.h> |
258aea76 | 55 | #include <linux/types.h> |
32614aad ML |
56 | #include <linux/of.h> |
57 | #include <linux/of_device.h> | |
258e0551 | 58 | #include <linux/pinctrl/consumer.h> |
cb70706c | 59 | #include <linux/sizes.h> |
de609582 | 60 | #include <linux/io.h> |
3db9ab0b | 61 | #include <linux/acpi.h> |
1da177e4 LT |
62 | |
63 | #define UART_NR 14 | |
64 | ||
65 | #define SERIAL_AMBA_MAJOR 204 | |
66 | #define SERIAL_AMBA_MINOR 64 | |
67 | #define SERIAL_AMBA_NR UART_NR | |
68 | ||
69 | #define AMBA_ISR_PASS_LIMIT 256 | |
70 | ||
b63d4f0f RK |
71 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
72 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 73 | |
5926a295 AR |
74 | /* There is by now at least one vendor with differing details, so handle it */ |
75 | struct vendor_data { | |
76 | unsigned int ifls; | |
ec489aa8 LW |
77 | unsigned int lcrh_tx; |
78 | unsigned int lcrh_rx; | |
ac3e3fb4 | 79 | bool oversampling; |
38d62436 | 80 | bool dma_threshold; |
4fd0690b | 81 | bool cts_event_workaround; |
71eec483 | 82 | bool always_enabled; |
cefc2d1d | 83 | bool fixed_options; |
78506f22 | 84 | |
ea33640a | 85 | unsigned int (*get_fifosize)(struct amba_device *dev); |
5926a295 AR |
86 | }; |
87 | ||
ea33640a | 88 | static unsigned int get_fifosize_arm(struct amba_device *dev) |
78506f22 | 89 | { |
ea33640a | 90 | return amba_rev(dev) < 3 ? 16 : 32; |
78506f22 JK |
91 | } |
92 | ||
5926a295 AR |
93 | static struct vendor_data vendor_arm = { |
94 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
ec489aa8 LW |
95 | .lcrh_tx = UART011_LCRH, |
96 | .lcrh_rx = UART011_LCRH, | |
ac3e3fb4 | 97 | .oversampling = false, |
38d62436 | 98 | .dma_threshold = false, |
4fd0690b | 99 | .cts_event_workaround = false, |
71eec483 | 100 | .always_enabled = false, |
cefc2d1d | 101 | .fixed_options = false, |
78506f22 | 102 | .get_fifosize = get_fifosize_arm, |
5926a295 AR |
103 | }; |
104 | ||
0dd1e247 AP |
105 | static struct vendor_data vendor_sbsa = { |
106 | .oversampling = false, | |
107 | .dma_threshold = false, | |
108 | .cts_event_workaround = false, | |
109 | .always_enabled = true, | |
110 | .fixed_options = true, | |
111 | }; | |
112 | ||
ea33640a | 113 | static unsigned int get_fifosize_st(struct amba_device *dev) |
78506f22 JK |
114 | { |
115 | return 64; | |
116 | } | |
117 | ||
5926a295 AR |
118 | static struct vendor_data vendor_st = { |
119 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
ec489aa8 LW |
120 | .lcrh_tx = ST_UART011_LCRH_TX, |
121 | .lcrh_rx = ST_UART011_LCRH_RX, | |
ac3e3fb4 | 122 | .oversampling = true, |
38d62436 | 123 | .dma_threshold = true, |
4fd0690b | 124 | .cts_event_workaround = true, |
71eec483 | 125 | .always_enabled = false, |
cefc2d1d | 126 | .fixed_options = false, |
78506f22 | 127 | .get_fifosize = get_fifosize_st, |
1da177e4 LT |
128 | }; |
129 | ||
68b65f73 | 130 | /* Deals with DMA transactions */ |
ead76f32 LW |
131 | |
132 | struct pl011_sgbuf { | |
133 | struct scatterlist sg; | |
134 | char *buf; | |
135 | }; | |
136 | ||
137 | struct pl011_dmarx_data { | |
138 | struct dma_chan *chan; | |
139 | struct completion complete; | |
140 | bool use_buf_b; | |
141 | struct pl011_sgbuf sgbuf_a; | |
142 | struct pl011_sgbuf sgbuf_b; | |
143 | dma_cookie_t cookie; | |
144 | bool running; | |
cb06ff10 CM |
145 | struct timer_list timer; |
146 | unsigned int last_residue; | |
147 | unsigned long last_jiffies; | |
148 | bool auto_poll_rate; | |
149 | unsigned int poll_rate; | |
150 | unsigned int poll_timeout; | |
ead76f32 LW |
151 | }; |
152 | ||
68b65f73 RK |
153 | struct pl011_dmatx_data { |
154 | struct dma_chan *chan; | |
155 | struct scatterlist sg; | |
156 | char *buf; | |
157 | bool queued; | |
158 | }; | |
159 | ||
c19f12b5 RK |
160 | /* |
161 | * We wrap our port structure around the generic uart_port. | |
162 | */ | |
163 | struct uart_amba_port { | |
164 | struct uart_port port; | |
165 | struct clk *clk; | |
166 | const struct vendor_data *vendor; | |
68b65f73 | 167 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
168 | unsigned int im; /* interrupt mask */ |
169 | unsigned int old_status; | |
ffca2b11 | 170 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
171 | unsigned int lcrh_tx; /* vendor-specific */ |
172 | unsigned int lcrh_rx; /* vendor-specific */ | |
d8d8ffa4 | 173 | unsigned int old_cr; /* state during shutdown */ |
c19f12b5 | 174 | bool autorts; |
cefc2d1d | 175 | unsigned int fixed_baud; /* vendor-set fixed baud rate */ |
c19f12b5 | 176 | char type[12]; |
68b65f73 RK |
177 | #ifdef CONFIG_DMA_ENGINE |
178 | /* DMA stuff */ | |
ead76f32 LW |
179 | bool using_tx_dma; |
180 | bool using_rx_dma; | |
181 | struct pl011_dmarx_data dmarx; | |
68b65f73 | 182 | struct pl011_dmatx_data dmatx; |
1c9be310 | 183 | bool dma_probed; |
68b65f73 RK |
184 | #endif |
185 | }; | |
186 | ||
29772c4e LW |
187 | /* |
188 | * Reads up to 256 characters from the FIFO or until it's empty and | |
189 | * inserts them into the TTY layer. Returns the number of characters | |
190 | * read from the FIFO. | |
191 | */ | |
192 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
193 | { | |
194 | u16 status, ch; | |
195 | unsigned int flag, max_count = 256; | |
196 | int fifotaken = 0; | |
197 | ||
198 | while (max_count--) { | |
199 | status = readw(uap->port.membase + UART01x_FR); | |
200 | if (status & UART01x_FR_RXFE) | |
201 | break; | |
202 | ||
203 | /* Take chars from the FIFO and update status */ | |
204 | ch = readw(uap->port.membase + UART01x_DR) | | |
205 | UART_DUMMY_DR_RX; | |
206 | flag = TTY_NORMAL; | |
207 | uap->port.icount.rx++; | |
208 | fifotaken++; | |
209 | ||
210 | if (unlikely(ch & UART_DR_ERROR)) { | |
211 | if (ch & UART011_DR_BE) { | |
212 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
213 | uap->port.icount.brk++; | |
214 | if (uart_handle_break(&uap->port)) | |
215 | continue; | |
216 | } else if (ch & UART011_DR_PE) | |
217 | uap->port.icount.parity++; | |
218 | else if (ch & UART011_DR_FE) | |
219 | uap->port.icount.frame++; | |
220 | if (ch & UART011_DR_OE) | |
221 | uap->port.icount.overrun++; | |
222 | ||
223 | ch &= uap->port.read_status_mask; | |
224 | ||
225 | if (ch & UART011_DR_BE) | |
226 | flag = TTY_BREAK; | |
227 | else if (ch & UART011_DR_PE) | |
228 | flag = TTY_PARITY; | |
229 | else if (ch & UART011_DR_FE) | |
230 | flag = TTY_FRAME; | |
231 | } | |
232 | ||
233 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
234 | continue; | |
235 | ||
236 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
237 | } | |
238 | ||
239 | return fifotaken; | |
240 | } | |
241 | ||
242 | ||
68b65f73 RK |
243 | /* |
244 | * All the DMA operation mode stuff goes inside this ifdef. | |
245 | * This assumes that you have a generic DMA device interface, | |
246 | * no custom DMA interfaces are supported. | |
247 | */ | |
248 | #ifdef CONFIG_DMA_ENGINE | |
249 | ||
250 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
251 | ||
ead76f32 LW |
252 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
253 | enum dma_data_direction dir) | |
254 | { | |
cb06ff10 CM |
255 | dma_addr_t dma_addr; |
256 | ||
257 | sg->buf = dma_alloc_coherent(chan->device->dev, | |
258 | PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); | |
ead76f32 LW |
259 | if (!sg->buf) |
260 | return -ENOMEM; | |
261 | ||
cb06ff10 CM |
262 | sg_init_table(&sg->sg, 1); |
263 | sg_set_page(&sg->sg, phys_to_page(dma_addr), | |
264 | PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); | |
265 | sg_dma_address(&sg->sg) = dma_addr; | |
c64be923 | 266 | sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; |
ead76f32 | 267 | |
ead76f32 LW |
268 | return 0; |
269 | } | |
270 | ||
271 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
272 | enum dma_data_direction dir) | |
273 | { | |
274 | if (sg->buf) { | |
cb06ff10 CM |
275 | dma_free_coherent(chan->device->dev, |
276 | PL011_DMA_BUFFER_SIZE, sg->buf, | |
277 | sg_dma_address(&sg->sg)); | |
ead76f32 LW |
278 | } |
279 | } | |
280 | ||
1c9be310 | 281 | static void pl011_dma_probe(struct uart_amba_port *uap) |
68b65f73 RK |
282 | { |
283 | /* DMA is the sole user of the platform data right now */ | |
574de559 | 284 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
1c9be310 | 285 | struct device *dev = uap->port.dev; |
68b65f73 RK |
286 | struct dma_slave_config tx_conf = { |
287 | .dst_addr = uap->port.mapbase + UART01x_DR, | |
288 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 289 | .direction = DMA_MEM_TO_DEV, |
68b65f73 | 290 | .dst_maxburst = uap->fifosize >> 1, |
258aea76 | 291 | .device_fc = false, |
68b65f73 RK |
292 | }; |
293 | struct dma_chan *chan; | |
294 | dma_cap_mask_t mask; | |
295 | ||
1c9be310 JRO |
296 | uap->dma_probed = true; |
297 | chan = dma_request_slave_channel_reason(dev, "tx"); | |
298 | if (IS_ERR(chan)) { | |
299 | if (PTR_ERR(chan) == -EPROBE_DEFER) { | |
1c9be310 JRO |
300 | uap->dma_probed = false; |
301 | return; | |
302 | } | |
68b65f73 | 303 | |
787b0c1f AB |
304 | /* We need platform data */ |
305 | if (!plat || !plat->dma_filter) { | |
306 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
307 | return; | |
308 | } | |
309 | ||
310 | /* Try to acquire a generic DMA engine slave TX channel */ | |
311 | dma_cap_zero(mask); | |
312 | dma_cap_set(DMA_SLAVE, mask); | |
313 | ||
314 | chan = dma_request_channel(mask, plat->dma_filter, | |
315 | plat->dma_tx_param); | |
316 | if (!chan) { | |
317 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
318 | return; | |
319 | } | |
68b65f73 RK |
320 | } |
321 | ||
322 | dmaengine_slave_config(chan, &tx_conf); | |
323 | uap->dmatx.chan = chan; | |
324 | ||
325 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
326 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
327 | |
328 | /* Optionally make use of an RX channel as well */ | |
787b0c1f | 329 | chan = dma_request_slave_channel(dev, "rx"); |
0d3c673e | 330 | |
787b0c1f AB |
331 | if (!chan && plat->dma_rx_param) { |
332 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
333 | ||
334 | if (!chan) { | |
335 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
336 | return; | |
337 | } | |
338 | } | |
339 | ||
340 | if (chan) { | |
ead76f32 LW |
341 | struct dma_slave_config rx_conf = { |
342 | .src_addr = uap->port.mapbase + UART01x_DR, | |
343 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 344 | .direction = DMA_DEV_TO_MEM, |
b2aeb775 | 345 | .src_maxburst = uap->fifosize >> 2, |
258aea76 | 346 | .device_fc = false, |
ead76f32 | 347 | }; |
2d3b7d6e AJ |
348 | struct dma_slave_caps caps; |
349 | ||
350 | /* | |
351 | * Some DMA controllers provide information on their capabilities. | |
352 | * If the controller does, check for suitable residue processing | |
353 | * otherwise assime all is well. | |
354 | */ | |
355 | if (0 == dma_get_slave_caps(chan, &caps)) { | |
356 | if (caps.residue_granularity == | |
357 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { | |
358 | dma_release_channel(chan); | |
359 | dev_info(uap->port.dev, | |
360 | "RX DMA disabled - no residue processing\n"); | |
361 | return; | |
362 | } | |
363 | } | |
ead76f32 LW |
364 | dmaengine_slave_config(chan, &rx_conf); |
365 | uap->dmarx.chan = chan; | |
366 | ||
98267d33 | 367 | uap->dmarx.auto_poll_rate = false; |
8f898bfd | 368 | if (plat && plat->dma_rx_poll_enable) { |
cb06ff10 CM |
369 | /* Set poll rate if specified. */ |
370 | if (plat->dma_rx_poll_rate) { | |
371 | uap->dmarx.auto_poll_rate = false; | |
372 | uap->dmarx.poll_rate = plat->dma_rx_poll_rate; | |
373 | } else { | |
374 | /* | |
375 | * 100 ms defaults to poll rate if not | |
376 | * specified. This will be adjusted with | |
377 | * the baud rate at set_termios. | |
378 | */ | |
379 | uap->dmarx.auto_poll_rate = true; | |
380 | uap->dmarx.poll_rate = 100; | |
381 | } | |
382 | /* 3 secs defaults poll_timeout if not specified. */ | |
383 | if (plat->dma_rx_poll_timeout) | |
384 | uap->dmarx.poll_timeout = | |
385 | plat->dma_rx_poll_timeout; | |
386 | else | |
387 | uap->dmarx.poll_timeout = 3000; | |
98267d33 AJ |
388 | } else if (!plat && dev->of_node) { |
389 | uap->dmarx.auto_poll_rate = of_property_read_bool( | |
390 | dev->of_node, "auto-poll"); | |
391 | if (uap->dmarx.auto_poll_rate) { | |
392 | u32 x; | |
393 | ||
394 | if (0 == of_property_read_u32(dev->of_node, | |
395 | "poll-rate-ms", &x)) | |
396 | uap->dmarx.poll_rate = x; | |
397 | else | |
398 | uap->dmarx.poll_rate = 100; | |
399 | if (0 == of_property_read_u32(dev->of_node, | |
400 | "poll-timeout-ms", &x)) | |
401 | uap->dmarx.poll_timeout = x; | |
402 | else | |
403 | uap->dmarx.poll_timeout = 3000; | |
404 | } | |
405 | } | |
ead76f32 LW |
406 | dev_info(uap->port.dev, "DMA channel RX %s\n", |
407 | dma_chan_name(uap->dmarx.chan)); | |
408 | } | |
68b65f73 RK |
409 | } |
410 | ||
68b65f73 RK |
411 | static void pl011_dma_remove(struct uart_amba_port *uap) |
412 | { | |
68b65f73 RK |
413 | if (uap->dmatx.chan) |
414 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
415 | if (uap->dmarx.chan) |
416 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
417 | } |
418 | ||
734745ca | 419 | /* Forward declare these for the refill routine */ |
68b65f73 | 420 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); |
734745ca | 421 | static void pl011_start_tx_pio(struct uart_amba_port *uap); |
68b65f73 RK |
422 | |
423 | /* | |
424 | * The current DMA TX buffer has been sent. | |
425 | * Try to queue up another DMA buffer. | |
426 | */ | |
427 | static void pl011_dma_tx_callback(void *data) | |
428 | { | |
429 | struct uart_amba_port *uap = data; | |
430 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
431 | unsigned long flags; | |
432 | u16 dmacr; | |
433 | ||
434 | spin_lock_irqsave(&uap->port.lock, flags); | |
435 | if (uap->dmatx.queued) | |
436 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
437 | DMA_TO_DEVICE); | |
438 | ||
439 | dmacr = uap->dmacr; | |
440 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
441 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
442 | ||
443 | /* | |
444 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
445 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
446 | * | |
447 | * Note: we need to be careful here of a potential race between DMA | |
448 | * and the rest of the driver - if the driver disables TX DMA while | |
449 | * a TX buffer completing, we must update the tx queued status to | |
450 | * get further refills (hence we check dmacr). | |
451 | */ | |
452 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
453 | uart_circ_empty(&uap->port.state->xmit)) { | |
454 | uap->dmatx.queued = false; | |
455 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
456 | return; | |
457 | } | |
458 | ||
734745ca | 459 | if (pl011_dma_tx_refill(uap) <= 0) |
68b65f73 RK |
460 | /* |
461 | * We didn't queue a DMA buffer for some reason, but we | |
462 | * have data pending to be sent. Re-enable the TX IRQ. | |
463 | */ | |
734745ca DM |
464 | pl011_start_tx_pio(uap); |
465 | ||
68b65f73 RK |
466 | spin_unlock_irqrestore(&uap->port.lock, flags); |
467 | } | |
468 | ||
469 | /* | |
470 | * Try to refill the TX DMA buffer. | |
471 | * Locking: called with port lock held and IRQs disabled. | |
472 | * Returns: | |
473 | * 1 if we queued up a TX DMA buffer. | |
474 | * 0 if we didn't want to handle this by DMA | |
475 | * <0 on error | |
476 | */ | |
477 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
478 | { | |
479 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
480 | struct dma_chan *chan = dmatx->chan; | |
481 | struct dma_device *dma_dev = chan->device; | |
482 | struct dma_async_tx_descriptor *desc; | |
483 | struct circ_buf *xmit = &uap->port.state->xmit; | |
484 | unsigned int count; | |
485 | ||
486 | /* | |
487 | * Try to avoid the overhead involved in using DMA if the | |
488 | * transaction fits in the first half of the FIFO, by using | |
489 | * the standard interrupt handling. This ensures that we | |
490 | * issue a uart_write_wakeup() at the appropriate time. | |
491 | */ | |
492 | count = uart_circ_chars_pending(xmit); | |
493 | if (count < (uap->fifosize >> 1)) { | |
494 | uap->dmatx.queued = false; | |
495 | return 0; | |
496 | } | |
497 | ||
498 | /* | |
499 | * Bodge: don't send the last character by DMA, as this | |
500 | * will prevent XON from notifying us to restart DMA. | |
501 | */ | |
502 | count -= 1; | |
503 | ||
504 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
505 | if (count > PL011_DMA_BUFFER_SIZE) | |
506 | count = PL011_DMA_BUFFER_SIZE; | |
507 | ||
508 | if (xmit->tail < xmit->head) | |
509 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
510 | else { | |
511 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
e2a545a6 AJ |
512 | size_t second; |
513 | ||
514 | if (first > count) | |
515 | first = count; | |
516 | second = count - first; | |
68b65f73 RK |
517 | |
518 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
519 | if (second) | |
520 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
521 | } | |
522 | ||
523 | dmatx->sg.length = count; | |
524 | ||
525 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
526 | uap->dmatx.queued = false; | |
527 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
528 | return -EBUSY; | |
529 | } | |
530 | ||
16052827 | 531 | desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
68b65f73 RK |
532 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
533 | if (!desc) { | |
534 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
535 | uap->dmatx.queued = false; | |
536 | /* | |
537 | * If DMA cannot be used right now, we complete this | |
538 | * transaction via IRQ and let the TTY layer retry. | |
539 | */ | |
540 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
541 | return -EBUSY; | |
542 | } | |
543 | ||
544 | /* Some data to go along to the callback */ | |
545 | desc->callback = pl011_dma_tx_callback; | |
546 | desc->callback_param = uap; | |
547 | ||
548 | /* All errors should happen at prepare time */ | |
549 | dmaengine_submit(desc); | |
550 | ||
551 | /* Fire the DMA transaction */ | |
552 | dma_dev->device_issue_pending(chan); | |
553 | ||
554 | uap->dmacr |= UART011_TXDMAE; | |
555 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
556 | uap->dmatx.queued = true; | |
557 | ||
558 | /* | |
559 | * Now we know that DMA will fire, so advance the ring buffer | |
560 | * with the stuff we just dispatched. | |
561 | */ | |
562 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
563 | uap->port.icount.tx += count; | |
564 | ||
565 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
566 | uart_write_wakeup(&uap->port); | |
567 | ||
568 | return 1; | |
569 | } | |
570 | ||
571 | /* | |
572 | * We received a transmit interrupt without a pending X-char but with | |
573 | * pending characters. | |
574 | * Locking: called with port lock held and IRQs disabled. | |
575 | * Returns: | |
576 | * false if we want to use PIO to transmit | |
577 | * true if we queued a DMA buffer | |
578 | */ | |
579 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
580 | { | |
ead76f32 | 581 | if (!uap->using_tx_dma) |
68b65f73 RK |
582 | return false; |
583 | ||
584 | /* | |
585 | * If we already have a TX buffer queued, but received a | |
586 | * TX interrupt, it will be because we've just sent an X-char. | |
587 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
588 | */ | |
589 | if (uap->dmatx.queued) { | |
590 | uap->dmacr |= UART011_TXDMAE; | |
591 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
592 | uap->im &= ~UART011_TXIM; | |
593 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
594 | return true; | |
595 | } | |
596 | ||
597 | /* | |
598 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 599 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
600 | */ |
601 | if (pl011_dma_tx_refill(uap) > 0) { | |
602 | uap->im &= ~UART011_TXIM; | |
603 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
604 | return true; | |
605 | } | |
606 | return false; | |
607 | } | |
608 | ||
609 | /* | |
610 | * Stop the DMA transmit (eg, due to received XOFF). | |
611 | * Locking: called with port lock held and IRQs disabled. | |
612 | */ | |
613 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
614 | { | |
615 | if (uap->dmatx.queued) { | |
616 | uap->dmacr &= ~UART011_TXDMAE; | |
617 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
618 | } | |
619 | } | |
620 | ||
621 | /* | |
622 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
623 | * character queued for send, try to get that character out ASAP. | |
624 | * Locking: called with port lock held and IRQs disabled. | |
625 | * Returns: | |
626 | * false if we want the TX IRQ to be enabled | |
627 | * true if we have a buffer queued | |
628 | */ | |
629 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
630 | { | |
631 | u16 dmacr; | |
632 | ||
ead76f32 | 633 | if (!uap->using_tx_dma) |
68b65f73 RK |
634 | return false; |
635 | ||
636 | if (!uap->port.x_char) { | |
637 | /* no X-char, try to push chars out in DMA mode */ | |
638 | bool ret = true; | |
639 | ||
640 | if (!uap->dmatx.queued) { | |
641 | if (pl011_dma_tx_refill(uap) > 0) { | |
642 | uap->im &= ~UART011_TXIM; | |
734745ca DM |
643 | writew(uap->im, uap->port.membase + |
644 | UART011_IMSC); | |
645 | } else | |
68b65f73 | 646 | ret = false; |
68b65f73 RK |
647 | } else if (!(uap->dmacr & UART011_TXDMAE)) { |
648 | uap->dmacr |= UART011_TXDMAE; | |
649 | writew(uap->dmacr, | |
650 | uap->port.membase + UART011_DMACR); | |
651 | } | |
652 | return ret; | |
653 | } | |
654 | ||
655 | /* | |
656 | * We have an X-char to send. Disable DMA to prevent it loading | |
657 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
658 | */ | |
659 | dmacr = uap->dmacr; | |
660 | uap->dmacr &= ~UART011_TXDMAE; | |
661 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
662 | ||
663 | if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { | |
664 | /* | |
665 | * No space in the FIFO, so enable the transmit interrupt | |
666 | * so we know when there is space. Note that once we've | |
667 | * loaded the character, we should just re-enable DMA. | |
668 | */ | |
669 | return false; | |
670 | } | |
671 | ||
672 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
673 | uap->port.icount.tx++; | |
674 | uap->port.x_char = 0; | |
675 | ||
676 | /* Success - restore the DMA state */ | |
677 | uap->dmacr = dmacr; | |
678 | writew(dmacr, uap->port.membase + UART011_DMACR); | |
679 | ||
680 | return true; | |
681 | } | |
682 | ||
683 | /* | |
684 | * Flush the transmit buffer. | |
685 | * Locking: called with port lock held and IRQs disabled. | |
686 | */ | |
687 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
b83286bf FE |
688 | __releases(&uap->port.lock) |
689 | __acquires(&uap->port.lock) | |
68b65f73 | 690 | { |
a5820c24 DT |
691 | struct uart_amba_port *uap = |
692 | container_of(port, struct uart_amba_port, port); | |
68b65f73 | 693 | |
ead76f32 | 694 | if (!uap->using_tx_dma) |
68b65f73 RK |
695 | return; |
696 | ||
697 | /* Avoid deadlock with the DMA engine callback */ | |
698 | spin_unlock(&uap->port.lock); | |
699 | dmaengine_terminate_all(uap->dmatx.chan); | |
700 | spin_lock(&uap->port.lock); | |
701 | if (uap->dmatx.queued) { | |
702 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
703 | DMA_TO_DEVICE); | |
704 | uap->dmatx.queued = false; | |
705 | uap->dmacr &= ~UART011_TXDMAE; | |
706 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
707 | } | |
708 | } | |
709 | ||
ead76f32 LW |
710 | static void pl011_dma_rx_callback(void *data); |
711 | ||
712 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
713 | { | |
714 | struct dma_chan *rxchan = uap->dmarx.chan; | |
ead76f32 LW |
715 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
716 | struct dma_async_tx_descriptor *desc; | |
717 | struct pl011_sgbuf *sgbuf; | |
718 | ||
719 | if (!rxchan) | |
720 | return -EIO; | |
721 | ||
722 | /* Start the RX DMA job */ | |
723 | sgbuf = uap->dmarx.use_buf_b ? | |
724 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
16052827 | 725 | desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, |
a485df4b | 726 | DMA_DEV_TO_MEM, |
ead76f32 LW |
727 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
728 | /* | |
729 | * If the DMA engine is busy and cannot prepare a | |
730 | * channel, no big deal, the driver will fall back | |
731 | * to interrupt mode as a result of this error code. | |
732 | */ | |
733 | if (!desc) { | |
734 | uap->dmarx.running = false; | |
735 | dmaengine_terminate_all(rxchan); | |
736 | return -EBUSY; | |
737 | } | |
738 | ||
739 | /* Some data to go along to the callback */ | |
740 | desc->callback = pl011_dma_rx_callback; | |
741 | desc->callback_param = uap; | |
742 | dmarx->cookie = dmaengine_submit(desc); | |
743 | dma_async_issue_pending(rxchan); | |
744 | ||
745 | uap->dmacr |= UART011_RXDMAE; | |
746 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
747 | uap->dmarx.running = true; | |
748 | ||
749 | uap->im &= ~UART011_RXIM; | |
750 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
755 | /* | |
756 | * This is called when either the DMA job is complete, or | |
757 | * the FIFO timeout interrupt occurred. This must be called | |
758 | * with the port spinlock uap->port.lock held. | |
759 | */ | |
760 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
761 | u32 pending, bool use_buf_b, | |
762 | bool readfifo) | |
763 | { | |
05c7cd39 | 764 | struct tty_port *port = &uap->port.state->port; |
ead76f32 LW |
765 | struct pl011_sgbuf *sgbuf = use_buf_b ? |
766 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
ead76f32 LW |
767 | int dma_count = 0; |
768 | u32 fifotaken = 0; /* only used for vdbg() */ | |
769 | ||
cb06ff10 CM |
770 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
771 | int dmataken = 0; | |
772 | ||
773 | if (uap->dmarx.poll_rate) { | |
774 | /* The data can be taken by polling */ | |
775 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
776 | /* Recalculate the pending size */ | |
777 | if (pending >= dmataken) | |
778 | pending -= dmataken; | |
779 | } | |
780 | ||
781 | /* Pick the remain data from the DMA */ | |
ead76f32 | 782 | if (pending) { |
ead76f32 LW |
783 | |
784 | /* | |
785 | * First take all chars in the DMA pipe, then look in the FIFO. | |
786 | * Note that tty_insert_flip_buf() tries to take as many chars | |
787 | * as it can. | |
788 | */ | |
cb06ff10 CM |
789 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, |
790 | pending); | |
ead76f32 LW |
791 | |
792 | uap->port.icount.rx += dma_count; | |
793 | if (dma_count < pending) | |
794 | dev_warn(uap->port.dev, | |
795 | "couldn't insert all characters (TTY is full?)\n"); | |
796 | } | |
797 | ||
cb06ff10 CM |
798 | /* Reset the last_residue for Rx DMA poll */ |
799 | if (uap->dmarx.poll_rate) | |
800 | dmarx->last_residue = sgbuf->sg.length; | |
801 | ||
ead76f32 LW |
802 | /* |
803 | * Only continue with trying to read the FIFO if all DMA chars have | |
804 | * been taken first. | |
805 | */ | |
806 | if (dma_count == pending && readfifo) { | |
807 | /* Clear any error flags */ | |
808 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
809 | uap->port.membase + UART011_ICR); | |
810 | ||
811 | /* | |
812 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
813 | * incomplete buffer, that could be due to an rx error, or |
814 | * maybe we just timed out. Read any pending chars and check | |
815 | * the error status. | |
816 | * | |
817 | * Error conditions will only occur in the FIFO, these will | |
818 | * trigger an immediate interrupt and stop the DMA job, so we | |
819 | * will always find the error in the FIFO, never in the DMA | |
820 | * buffer. | |
ead76f32 | 821 | */ |
29772c4e | 822 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
823 | } |
824 | ||
825 | spin_unlock(&uap->port.lock); | |
826 | dev_vdbg(uap->port.dev, | |
827 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
828 | dma_count, fifotaken); | |
2e124b4a | 829 | tty_flip_buffer_push(port); |
ead76f32 LW |
830 | spin_lock(&uap->port.lock); |
831 | } | |
832 | ||
833 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
834 | { | |
835 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
836 | struct dma_chan *rxchan = dmarx->chan; | |
837 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
838 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
839 | size_t pending; | |
840 | struct dma_tx_state state; | |
841 | enum dma_status dmastat; | |
842 | ||
843 | /* | |
844 | * Pause the transfer so we can trust the current counter, | |
845 | * do this before we pause the PL011 block, else we may | |
846 | * overflow the FIFO. | |
847 | */ | |
848 | if (dmaengine_pause(rxchan)) | |
849 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
850 | dmastat = rxchan->device->device_tx_status(rxchan, | |
851 | dmarx->cookie, &state); | |
852 | if (dmastat != DMA_PAUSED) | |
853 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
854 | ||
855 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
856 | uap->dmacr &= ~UART011_RXDMAE; | |
857 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
858 | uap->dmarx.running = false; | |
859 | ||
860 | pending = sgbuf->sg.length - state.residue; | |
861 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
862 | /* Then we terminate the transfer - we now know our residue */ | |
863 | dmaengine_terminate_all(rxchan); | |
864 | ||
865 | /* | |
866 | * This will take the chars we have so far and insert | |
867 | * into the framework. | |
868 | */ | |
869 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
870 | ||
871 | /* Switch buffer & re-trigger DMA job */ | |
872 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
873 | if (pl011_dma_rx_trigger_dma(uap)) { | |
874 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
875 | "fall back to interrupt mode\n"); | |
876 | uap->im |= UART011_RXIM; | |
877 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
878 | } | |
879 | } | |
880 | ||
881 | static void pl011_dma_rx_callback(void *data) | |
882 | { | |
883 | struct uart_amba_port *uap = data; | |
884 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
6dc01aa6 | 885 | struct dma_chan *rxchan = dmarx->chan; |
ead76f32 | 886 | bool lastbuf = dmarx->use_buf_b; |
6dc01aa6 CM |
887 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? |
888 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
889 | size_t pending; | |
890 | struct dma_tx_state state; | |
ead76f32 LW |
891 | int ret; |
892 | ||
893 | /* | |
894 | * This completion interrupt occurs typically when the | |
895 | * RX buffer is totally stuffed but no timeout has yet | |
896 | * occurred. When that happens, we just want the RX | |
897 | * routine to flush out the secondary DMA buffer while | |
898 | * we immediately trigger the next DMA job. | |
899 | */ | |
900 | spin_lock_irq(&uap->port.lock); | |
6dc01aa6 CM |
901 | /* |
902 | * Rx data can be taken by the UART interrupts during | |
903 | * the DMA irq handler. So we check the residue here. | |
904 | */ | |
905 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
906 | pending = sgbuf->sg.length - state.residue; | |
907 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
908 | /* Then we terminate the transfer - we now know our residue */ | |
909 | dmaengine_terminate_all(rxchan); | |
910 | ||
ead76f32 LW |
911 | uap->dmarx.running = false; |
912 | dmarx->use_buf_b = !lastbuf; | |
913 | ret = pl011_dma_rx_trigger_dma(uap); | |
914 | ||
6dc01aa6 | 915 | pl011_dma_rx_chars(uap, pending, lastbuf, false); |
ead76f32 LW |
916 | spin_unlock_irq(&uap->port.lock); |
917 | /* | |
918 | * Do this check after we picked the DMA chars so we don't | |
919 | * get some IRQ immediately from RX. | |
920 | */ | |
921 | if (ret) { | |
922 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
923 | "fall back to interrupt mode\n"); | |
924 | uap->im |= UART011_RXIM; | |
925 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
926 | } | |
927 | } | |
928 | ||
929 | /* | |
930 | * Stop accepting received characters, when we're shutting down or | |
931 | * suspending this port. | |
932 | * Locking: called with port lock held and IRQs disabled. | |
933 | */ | |
934 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
935 | { | |
936 | /* FIXME. Just disable the DMA enable */ | |
937 | uap->dmacr &= ~UART011_RXDMAE; | |
938 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
939 | } | |
68b65f73 | 940 | |
cb06ff10 CM |
941 | /* |
942 | * Timer handler for Rx DMA polling. | |
943 | * Every polling, It checks the residue in the dma buffer and transfer | |
944 | * data to the tty. Also, last_residue is updated for the next polling. | |
945 | */ | |
946 | static void pl011_dma_rx_poll(unsigned long args) | |
947 | { | |
948 | struct uart_amba_port *uap = (struct uart_amba_port *)args; | |
949 | struct tty_port *port = &uap->port.state->port; | |
950 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
951 | struct dma_chan *rxchan = uap->dmarx.chan; | |
952 | unsigned long flags = 0; | |
953 | unsigned int dmataken = 0; | |
954 | unsigned int size = 0; | |
955 | struct pl011_sgbuf *sgbuf; | |
956 | int dma_count; | |
957 | struct dma_tx_state state; | |
958 | ||
959 | sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
960 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
961 | if (likely(state.residue < dmarx->last_residue)) { | |
962 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
963 | size = dmarx->last_residue - state.residue; | |
964 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, | |
965 | size); | |
966 | if (dma_count == size) | |
967 | dmarx->last_residue = state.residue; | |
968 | dmarx->last_jiffies = jiffies; | |
969 | } | |
970 | tty_flip_buffer_push(port); | |
971 | ||
972 | /* | |
973 | * If no data is received in poll_timeout, the driver will fall back | |
974 | * to interrupt mode. We will retrigger DMA at the first interrupt. | |
975 | */ | |
976 | if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) | |
977 | > uap->dmarx.poll_timeout) { | |
978 | ||
979 | spin_lock_irqsave(&uap->port.lock, flags); | |
980 | pl011_dma_rx_stop(uap); | |
c25a1ad7 GL |
981 | uap->im |= UART011_RXIM; |
982 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
cb06ff10 CM |
983 | spin_unlock_irqrestore(&uap->port.lock, flags); |
984 | ||
985 | uap->dmarx.running = false; | |
986 | dmaengine_terminate_all(rxchan); | |
987 | del_timer(&uap->dmarx.timer); | |
988 | } else { | |
989 | mod_timer(&uap->dmarx.timer, | |
990 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); | |
991 | } | |
992 | } | |
993 | ||
68b65f73 RK |
994 | static void pl011_dma_startup(struct uart_amba_port *uap) |
995 | { | |
ead76f32 LW |
996 | int ret; |
997 | ||
1c9be310 JRO |
998 | if (!uap->dma_probed) |
999 | pl011_dma_probe(uap); | |
1000 | ||
68b65f73 RK |
1001 | if (!uap->dmatx.chan) |
1002 | return; | |
1003 | ||
4c0be45b | 1004 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); |
68b65f73 RK |
1005 | if (!uap->dmatx.buf) { |
1006 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
1007 | uap->port.fifosize = uap->fifosize; | |
1008 | return; | |
1009 | } | |
1010 | ||
1011 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
1012 | ||
1013 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
1014 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
1015 | uap->using_tx_dma = true; |
1016 | ||
1017 | if (!uap->dmarx.chan) | |
1018 | goto skip_rx; | |
1019 | ||
1020 | /* Allocate and map DMA RX buffers */ | |
1021 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1022 | DMA_FROM_DEVICE); | |
1023 | if (ret) { | |
1024 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1025 | "RX buffer A", ret); | |
1026 | goto skip_rx; | |
1027 | } | |
68b65f73 | 1028 | |
ead76f32 LW |
1029 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
1030 | DMA_FROM_DEVICE); | |
1031 | if (ret) { | |
1032 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1033 | "RX buffer B", ret); | |
1034 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1035 | DMA_FROM_DEVICE); | |
1036 | goto skip_rx; | |
1037 | } | |
1038 | ||
1039 | uap->using_rx_dma = true; | |
68b65f73 | 1040 | |
ead76f32 | 1041 | skip_rx: |
68b65f73 RK |
1042 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
1043 | uap->dmacr |= UART011_DMAONERR; | |
1044 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
38d62436 RK |
1045 | |
1046 | /* | |
1047 | * ST Micro variants has some specific dma burst threshold | |
1048 | * compensation. Set this to 16 bytes, so burst will only | |
1049 | * be issued above/below 16 bytes. | |
1050 | */ | |
1051 | if (uap->vendor->dma_threshold) | |
1052 | writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, | |
1053 | uap->port.membase + ST_UART011_DMAWM); | |
ead76f32 LW |
1054 | |
1055 | if (uap->using_rx_dma) { | |
1056 | if (pl011_dma_rx_trigger_dma(uap)) | |
1057 | dev_dbg(uap->port.dev, "could not trigger initial " | |
1058 | "RX DMA job, fall back to interrupt mode\n"); | |
cb06ff10 CM |
1059 | if (uap->dmarx.poll_rate) { |
1060 | init_timer(&(uap->dmarx.timer)); | |
1061 | uap->dmarx.timer.function = pl011_dma_rx_poll; | |
1062 | uap->dmarx.timer.data = (unsigned long)uap; | |
1063 | mod_timer(&uap->dmarx.timer, | |
1064 | jiffies + | |
1065 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1066 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1067 | uap->dmarx.last_jiffies = jiffies; | |
1068 | } | |
ead76f32 | 1069 | } |
68b65f73 RK |
1070 | } |
1071 | ||
1072 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1073 | { | |
ead76f32 | 1074 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
1075 | return; |
1076 | ||
1077 | /* Disable RX and TX DMA */ | |
1078 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1079 | barrier(); | |
1080 | ||
1081 | spin_lock_irq(&uap->port.lock); | |
1082 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
1083 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
1084 | spin_unlock_irq(&uap->port.lock); | |
1085 | ||
ead76f32 LW |
1086 | if (uap->using_tx_dma) { |
1087 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
1088 | dmaengine_terminate_all(uap->dmatx.chan); | |
1089 | if (uap->dmatx.queued) { | |
1090 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
1091 | DMA_TO_DEVICE); | |
1092 | uap->dmatx.queued = false; | |
1093 | } | |
1094 | ||
1095 | kfree(uap->dmatx.buf); | |
1096 | uap->using_tx_dma = false; | |
68b65f73 RK |
1097 | } |
1098 | ||
ead76f32 LW |
1099 | if (uap->using_rx_dma) { |
1100 | dmaengine_terminate_all(uap->dmarx.chan); | |
1101 | /* Clean up the RX DMA */ | |
1102 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
1103 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
cb06ff10 CM |
1104 | if (uap->dmarx.poll_rate) |
1105 | del_timer_sync(&uap->dmarx.timer); | |
ead76f32 LW |
1106 | uap->using_rx_dma = false; |
1107 | } | |
1108 | } | |
68b65f73 | 1109 | |
ead76f32 LW |
1110 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
1111 | { | |
1112 | return uap->using_rx_dma; | |
68b65f73 RK |
1113 | } |
1114 | ||
ead76f32 LW |
1115 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
1116 | { | |
1117 | return uap->using_rx_dma && uap->dmarx.running; | |
1118 | } | |
1119 | ||
68b65f73 RK |
1120 | #else |
1121 | /* Blank functions if the DMA engine is not available */ | |
1c9be310 | 1122 | static inline void pl011_dma_probe(struct uart_amba_port *uap) |
68b65f73 RK |
1123 | { |
1124 | } | |
1125 | ||
1126 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
1127 | { | |
1128 | } | |
1129 | ||
1130 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
1131 | { | |
1132 | } | |
1133 | ||
1134 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1135 | { | |
1136 | } | |
1137 | ||
1138 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1139 | { | |
1140 | return false; | |
1141 | } | |
1142 | ||
1143 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1144 | { | |
1145 | } | |
1146 | ||
1147 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1148 | { | |
1149 | return false; | |
1150 | } | |
1151 | ||
ead76f32 LW |
1152 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1153 | { | |
1154 | } | |
1155 | ||
1156 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1157 | { | |
1158 | } | |
1159 | ||
1160 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1161 | { | |
1162 | return -EIO; | |
1163 | } | |
1164 | ||
1165 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1166 | { | |
1167 | return false; | |
1168 | } | |
1169 | ||
1170 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1171 | { | |
1172 | return false; | |
1173 | } | |
1174 | ||
68b65f73 RK |
1175 | #define pl011_dma_flush_buffer NULL |
1176 | #endif | |
1177 | ||
b129a8cc | 1178 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 | 1179 | { |
a5820c24 DT |
1180 | struct uart_amba_port *uap = |
1181 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1182 | |
1183 | uap->im &= ~UART011_TXIM; | |
1184 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
68b65f73 | 1185 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1186 | } |
1187 | ||
1e84d223 | 1188 | static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); |
734745ca DM |
1189 | |
1190 | /* Start TX with programmed I/O only (no DMA) */ | |
1191 | static void pl011_start_tx_pio(struct uart_amba_port *uap) | |
1192 | { | |
1193 | uap->im |= UART011_TXIM; | |
1194 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1e84d223 | 1195 | pl011_tx_chars(uap, false); |
734745ca DM |
1196 | } |
1197 | ||
b129a8cc | 1198 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 | 1199 | { |
a5820c24 DT |
1200 | struct uart_amba_port *uap = |
1201 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1202 | |
734745ca DM |
1203 | if (!pl011_dma_tx_start(uap)) |
1204 | pl011_start_tx_pio(uap); | |
1da177e4 LT |
1205 | } |
1206 | ||
1207 | static void pl011_stop_rx(struct uart_port *port) | |
1208 | { | |
a5820c24 DT |
1209 | struct uart_amba_port *uap = |
1210 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1211 | |
1212 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1213 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
1214 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
ead76f32 LW |
1215 | |
1216 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1217 | } |
1218 | ||
1219 | static void pl011_enable_ms(struct uart_port *port) | |
1220 | { | |
a5820c24 DT |
1221 | struct uart_amba_port *uap = |
1222 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1223 | |
1224 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
1225 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1226 | } | |
1227 | ||
7d12e780 | 1228 | static void pl011_rx_chars(struct uart_amba_port *uap) |
b83286bf FE |
1229 | __releases(&uap->port.lock) |
1230 | __acquires(&uap->port.lock) | |
1da177e4 | 1231 | { |
29772c4e | 1232 | pl011_fifo_to_tty(uap); |
1da177e4 | 1233 | |
2389b272 | 1234 | spin_unlock(&uap->port.lock); |
2e124b4a | 1235 | tty_flip_buffer_push(&uap->port.state->port); |
ead76f32 LW |
1236 | /* |
1237 | * If we were temporarily out of DMA mode for a while, | |
1238 | * attempt to switch back to DMA mode again. | |
1239 | */ | |
1240 | if (pl011_dma_rx_available(uap)) { | |
1241 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1242 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1243 | "fall back to interrupt mode again\n"); | |
1244 | uap->im |= UART011_RXIM; | |
30ae5859 | 1245 | writew(uap->im, uap->port.membase + UART011_IMSC); |
cb06ff10 | 1246 | } else { |
89fa28db | 1247 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1248 | /* Start Rx DMA poll */ |
1249 | if (uap->dmarx.poll_rate) { | |
1250 | uap->dmarx.last_jiffies = jiffies; | |
1251 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1252 | mod_timer(&uap->dmarx.timer, | |
1253 | jiffies + | |
1254 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1255 | } | |
89fa28db | 1256 | #endif |
cb06ff10 | 1257 | } |
ead76f32 | 1258 | } |
2389b272 | 1259 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1260 | } |
1261 | ||
1e84d223 DM |
1262 | static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, |
1263 | bool from_irq) | |
734745ca | 1264 | { |
1e84d223 DM |
1265 | if (unlikely(!from_irq) && |
1266 | readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
1267 | return false; /* unable to transmit character */ | |
1268 | ||
734745ca DM |
1269 | writew(c, uap->port.membase + UART01x_DR); |
1270 | uap->port.icount.tx++; | |
1271 | ||
1e84d223 | 1272 | return true; |
734745ca DM |
1273 | } |
1274 | ||
1e84d223 | 1275 | static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) |
1da177e4 | 1276 | { |
ebd2c8f6 | 1277 | struct circ_buf *xmit = &uap->port.state->xmit; |
1e84d223 | 1278 | int count = uap->fifosize >> 1; |
734745ca | 1279 | |
1da177e4 | 1280 | if (uap->port.x_char) { |
1e84d223 DM |
1281 | if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) |
1282 | return; | |
1da177e4 | 1283 | uap->port.x_char = 0; |
734745ca | 1284 | --count; |
1da177e4 LT |
1285 | } |
1286 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1287 | pl011_stop_tx(&uap->port); |
1e84d223 | 1288 | return; |
1da177e4 LT |
1289 | } |
1290 | ||
68b65f73 RK |
1291 | /* If we are using DMA mode, try to send some characters. */ |
1292 | if (pl011_dma_tx_irq(uap)) | |
1e84d223 | 1293 | return; |
68b65f73 | 1294 | |
1e84d223 DM |
1295 | do { |
1296 | if (likely(from_irq) && count-- == 0) | |
1da177e4 | 1297 | break; |
1e84d223 DM |
1298 | |
1299 | if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) | |
1300 | break; | |
1301 | ||
1302 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1303 | } while (!uart_circ_empty(xmit)); | |
1da177e4 LT |
1304 | |
1305 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1306 | uart_write_wakeup(&uap->port); | |
1307 | ||
1e84d223 | 1308 | if (uart_circ_empty(xmit)) |
b129a8cc | 1309 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1310 | } |
1311 | ||
1312 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1313 | { | |
1314 | unsigned int status, delta; | |
1315 | ||
1316 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1317 | ||
1318 | delta = status ^ uap->old_status; | |
1319 | uap->old_status = status; | |
1320 | ||
1321 | if (!delta) | |
1322 | return; | |
1323 | ||
1324 | if (delta & UART01x_FR_DCD) | |
1325 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1326 | ||
1327 | if (delta & UART01x_FR_DSR) | |
1328 | uap->port.icount.dsr++; | |
1329 | ||
1330 | if (delta & UART01x_FR_CTS) | |
1331 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1332 | ||
bdc04e31 | 1333 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1334 | } |
1335 | ||
9c4ef4b0 AP |
1336 | static void check_apply_cts_event_workaround(struct uart_amba_port *uap) |
1337 | { | |
1338 | unsigned int dummy_read; | |
1339 | ||
1340 | if (!uap->vendor->cts_event_workaround) | |
1341 | return; | |
1342 | ||
1343 | /* workaround to make sure that all bits are unlocked.. */ | |
1344 | writew(0x00, uap->port.membase + UART011_ICR); | |
1345 | ||
1346 | /* | |
1347 | * WA: introduce 26ns(1 uart clk) delay before W1C; | |
1348 | * single apb access will incur 2 pclk(133.12Mhz) delay, | |
1349 | * so add 2 dummy reads | |
1350 | */ | |
1351 | dummy_read = readw(uap->port.membase + UART011_ICR); | |
1352 | dummy_read = readw(uap->port.membase + UART011_ICR); | |
1353 | } | |
1354 | ||
7d12e780 | 1355 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1356 | { |
1357 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1358 | unsigned long flags; |
1da177e4 | 1359 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
075167ed | 1360 | u16 imsc; |
1da177e4 LT |
1361 | int handled = 0; |
1362 | ||
963cc981 | 1363 | spin_lock_irqsave(&uap->port.lock, flags); |
075167ed AP |
1364 | imsc = readw(uap->port.membase + UART011_IMSC); |
1365 | status = readw(uap->port.membase + UART011_RIS) & imsc; | |
1da177e4 LT |
1366 | if (status) { |
1367 | do { | |
9c4ef4b0 | 1368 | check_apply_cts_event_workaround(uap); |
4fd0690b | 1369 | |
1da177e4 LT |
1370 | writew(status & ~(UART011_TXIS|UART011_RTIS| |
1371 | UART011_RXIS), | |
1372 | uap->port.membase + UART011_ICR); | |
1373 | ||
ead76f32 LW |
1374 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1375 | if (pl011_dma_rx_running(uap)) | |
1376 | pl011_dma_rx_irq(uap); | |
1377 | else | |
1378 | pl011_rx_chars(uap); | |
1379 | } | |
1da177e4 LT |
1380 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1381 | UART011_CTSMIS|UART011_RIMIS)) | |
1382 | pl011_modem_status(uap); | |
1e84d223 DM |
1383 | if (status & UART011_TXIS) |
1384 | pl011_tx_chars(uap, true); | |
1da177e4 | 1385 | |
4fd0690b | 1386 | if (pass_counter-- == 0) |
1da177e4 LT |
1387 | break; |
1388 | ||
075167ed | 1389 | status = readw(uap->port.membase + UART011_RIS) & imsc; |
1da177e4 LT |
1390 | } while (status != 0); |
1391 | handled = 1; | |
1392 | } | |
1393 | ||
963cc981 | 1394 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1395 | |
1396 | return IRQ_RETVAL(handled); | |
1397 | } | |
1398 | ||
e643f87f | 1399 | static unsigned int pl011_tx_empty(struct uart_port *port) |
1da177e4 | 1400 | { |
a5820c24 DT |
1401 | struct uart_amba_port *uap = |
1402 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1403 | unsigned int status = readw(uap->port.membase + UART01x_FR); |
1404 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
1405 | } | |
1406 | ||
e643f87f | 1407 | static unsigned int pl011_get_mctrl(struct uart_port *port) |
1da177e4 | 1408 | { |
a5820c24 DT |
1409 | struct uart_amba_port *uap = |
1410 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1411 | unsigned int result = 0; |
1412 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1413 | ||
5159f407 | 1414 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1415 | if (status & uartbit) \ |
1416 | result |= tiocmbit | |
1417 | ||
5159f407 JS |
1418 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
1419 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
1420 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1421 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
1422 | #undef TIOCMBIT | |
1da177e4 LT |
1423 | return result; |
1424 | } | |
1425 | ||
1426 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1427 | { | |
a5820c24 DT |
1428 | struct uart_amba_port *uap = |
1429 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1430 | unsigned int cr; |
1431 | ||
1432 | cr = readw(uap->port.membase + UART011_CR); | |
1433 | ||
5159f407 | 1434 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1435 | if (mctrl & tiocmbit) \ |
1436 | cr |= uartbit; \ | |
1437 | else \ | |
1438 | cr &= ~uartbit | |
1439 | ||
5159f407 JS |
1440 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1441 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1442 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1443 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1444 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1445 | |
1446 | if (uap->autorts) { | |
1447 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1448 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1449 | } | |
5159f407 | 1450 | #undef TIOCMBIT |
1da177e4 LT |
1451 | |
1452 | writew(cr, uap->port.membase + UART011_CR); | |
1453 | } | |
1454 | ||
1455 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1456 | { | |
a5820c24 DT |
1457 | struct uart_amba_port *uap = |
1458 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1459 | unsigned long flags; |
1460 | unsigned int lcr_h; | |
1461 | ||
1462 | spin_lock_irqsave(&uap->port.lock, flags); | |
ec489aa8 | 1463 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1464 | if (break_state == -1) |
1465 | lcr_h |= UART01x_LCRH_BRK; | |
1466 | else | |
1467 | lcr_h &= ~UART01x_LCRH_BRK; | |
ec489aa8 | 1468 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1469 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1470 | } | |
1471 | ||
84b5ae15 | 1472 | #ifdef CONFIG_CONSOLE_POLL |
5c8124a0 AV |
1473 | |
1474 | static void pl011_quiesce_irqs(struct uart_port *port) | |
1475 | { | |
a5820c24 DT |
1476 | struct uart_amba_port *uap = |
1477 | container_of(port, struct uart_amba_port, port); | |
5c8124a0 AV |
1478 | unsigned char __iomem *regs = uap->port.membase; |
1479 | ||
1480 | writew(readw(regs + UART011_MIS), regs + UART011_ICR); | |
1481 | /* | |
1482 | * There is no way to clear TXIM as this is "ready to transmit IRQ", so | |
1483 | * we simply mask it. start_tx() will unmask it. | |
1484 | * | |
1485 | * Note we can race with start_tx(), and if the race happens, the | |
1486 | * polling user might get another interrupt just after we clear it. | |
1487 | * But it should be OK and can happen even w/o the race, e.g. | |
1488 | * controller immediately got some new data and raised the IRQ. | |
1489 | * | |
1490 | * And whoever uses polling routines assumes that it manages the device | |
1491 | * (including tx queue), so we're also fine with start_tx()'s caller | |
1492 | * side. | |
1493 | */ | |
1494 | writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC); | |
1495 | } | |
1496 | ||
e643f87f | 1497 | static int pl011_get_poll_char(struct uart_port *port) |
84b5ae15 | 1498 | { |
a5820c24 DT |
1499 | struct uart_amba_port *uap = |
1500 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1501 | unsigned int status; |
1502 | ||
5c8124a0 AV |
1503 | /* |
1504 | * The caller might need IRQs lowered, e.g. if used with KDB NMI | |
1505 | * debugger. | |
1506 | */ | |
1507 | pl011_quiesce_irqs(port); | |
1508 | ||
f5316b4a JW |
1509 | status = readw(uap->port.membase + UART01x_FR); |
1510 | if (status & UART01x_FR_RXFE) | |
1511 | return NO_POLL_CHAR; | |
84b5ae15 JW |
1512 | |
1513 | return readw(uap->port.membase + UART01x_DR); | |
1514 | } | |
1515 | ||
e643f87f | 1516 | static void pl011_put_poll_char(struct uart_port *port, |
84b5ae15 JW |
1517 | unsigned char ch) |
1518 | { | |
a5820c24 DT |
1519 | struct uart_amba_port *uap = |
1520 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1521 | |
1522 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
1523 | barrier(); | |
1524 | ||
1525 | writew(ch, uap->port.membase + UART01x_DR); | |
1526 | } | |
1527 | ||
1528 | #endif /* CONFIG_CONSOLE_POLL */ | |
1529 | ||
b3564c2c | 1530 | static int pl011_hwinit(struct uart_port *port) |
1da177e4 | 1531 | { |
a5820c24 DT |
1532 | struct uart_amba_port *uap = |
1533 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1534 | int retval; |
1535 | ||
78d80c5a | 1536 | /* Optionaly enable pins to be muxed in and configured */ |
2b996fc5 | 1537 | pinctrl_pm_select_default_state(port->dev); |
78d80c5a | 1538 | |
1da177e4 LT |
1539 | /* |
1540 | * Try to enable the clock producer. | |
1541 | */ | |
1c4c4394 | 1542 | retval = clk_prepare_enable(uap->clk); |
1da177e4 | 1543 | if (retval) |
7f6d942a | 1544 | return retval; |
1da177e4 LT |
1545 | |
1546 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1547 | ||
9b96fbac LW |
1548 | /* Clear pending error and receive interrupts */ |
1549 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS | | |
1550 | UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); | |
1551 | ||
b3564c2c AV |
1552 | /* |
1553 | * Save interrupts enable mask, and enable RX interrupts in case if | |
1554 | * the interrupt is used for NMI entry. | |
1555 | */ | |
1556 | uap->im = readw(uap->port.membase + UART011_IMSC); | |
1557 | writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); | |
1558 | ||
574de559 | 1559 | if (dev_get_platdata(uap->port.dev)) { |
b3564c2c AV |
1560 | struct amba_pl011_data *plat; |
1561 | ||
574de559 | 1562 | plat = dev_get_platdata(uap->port.dev); |
b3564c2c AV |
1563 | if (plat->init) |
1564 | plat->init(); | |
1565 | } | |
1566 | return 0; | |
b3564c2c AV |
1567 | } |
1568 | ||
b60f2f66 JM |
1569 | static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) |
1570 | { | |
1571 | writew(lcr_h, uap->port.membase + uap->lcrh_rx); | |
1572 | if (uap->lcrh_rx != uap->lcrh_tx) { | |
1573 | int i; | |
1574 | /* | |
1575 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1576 | * to get this delay write read only register 10 times | |
1577 | */ | |
1578 | for (i = 0; i < 10; ++i) | |
1579 | writew(0xff, uap->port.membase + UART011_MIS); | |
1580 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); | |
1581 | } | |
1582 | } | |
1583 | ||
867b8e8e AP |
1584 | static int pl011_allocate_irq(struct uart_amba_port *uap) |
1585 | { | |
1586 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1587 | ||
1588 | return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1589 | } | |
1590 | ||
1591 | /* | |
1592 | * Enable interrupts, only timeouts when using DMA | |
1593 | * if initial RX DMA job failed, start in interrupt mode | |
1594 | * as well. | |
1595 | */ | |
1596 | static void pl011_enable_interrupts(struct uart_amba_port *uap) | |
1597 | { | |
1598 | spin_lock_irq(&uap->port.lock); | |
1599 | ||
1600 | /* Clear out any spuriously appearing RX interrupts */ | |
1601 | writew(UART011_RTIS | UART011_RXIS, | |
1602 | uap->port.membase + UART011_ICR); | |
1603 | uap->im = UART011_RTIM; | |
1604 | if (!pl011_dma_rx_running(uap)) | |
1605 | uap->im |= UART011_RXIM; | |
1606 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1607 | spin_unlock_irq(&uap->port.lock); | |
1608 | } | |
1609 | ||
b3564c2c AV |
1610 | static int pl011_startup(struct uart_port *port) |
1611 | { | |
a5820c24 DT |
1612 | struct uart_amba_port *uap = |
1613 | container_of(port, struct uart_amba_port, port); | |
734745ca | 1614 | unsigned int cr; |
b3564c2c AV |
1615 | int retval; |
1616 | ||
1617 | retval = pl011_hwinit(port); | |
1618 | if (retval) | |
1619 | goto clk_dis; | |
1620 | ||
867b8e8e | 1621 | retval = pl011_allocate_irq(uap); |
1da177e4 LT |
1622 | if (retval) |
1623 | goto clk_dis; | |
1624 | ||
c19f12b5 | 1625 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 | 1626 | |
734745ca | 1627 | spin_lock_irq(&uap->port.lock); |
570d2910 | 1628 | |
d8d8ffa4 SKS |
1629 | /* restore RTS and DTR */ |
1630 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); | |
1631 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
1da177e4 LT |
1632 | writew(cr, uap->port.membase + UART011_CR); |
1633 | ||
fe433907 JM |
1634 | spin_unlock_irq(&uap->port.lock); |
1635 | ||
1da177e4 LT |
1636 | /* |
1637 | * initialise the old status of the modem signals | |
1638 | */ | |
1639 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1640 | ||
68b65f73 RK |
1641 | /* Startup DMA */ |
1642 | pl011_dma_startup(uap); | |
1643 | ||
867b8e8e | 1644 | pl011_enable_interrupts(uap); |
1da177e4 LT |
1645 | |
1646 | return 0; | |
1647 | ||
1648 | clk_dis: | |
1c4c4394 | 1649 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
1650 | return retval; |
1651 | } | |
1652 | ||
0dd1e247 AP |
1653 | static int sbsa_uart_startup(struct uart_port *port) |
1654 | { | |
1655 | struct uart_amba_port *uap = | |
1656 | container_of(port, struct uart_amba_port, port); | |
1657 | int retval; | |
1658 | ||
1659 | retval = pl011_hwinit(port); | |
1660 | if (retval) | |
1661 | return retval; | |
1662 | ||
1663 | retval = pl011_allocate_irq(uap); | |
1664 | if (retval) | |
1665 | return retval; | |
1666 | ||
1667 | /* The SBSA UART does not support any modem status lines. */ | |
1668 | uap->old_status = 0; | |
1669 | ||
1670 | pl011_enable_interrupts(uap); | |
1671 | ||
1672 | return 0; | |
1673 | } | |
1674 | ||
ec489aa8 LW |
1675 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1676 | unsigned int lcrh) | |
1677 | { | |
1678 | unsigned long val; | |
1679 | ||
1680 | val = readw(uap->port.membase + lcrh); | |
1681 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
1682 | writew(val, uap->port.membase + lcrh); | |
1683 | } | |
1684 | ||
95166a3f AP |
1685 | /* |
1686 | * disable the port. It should not disable RTS and DTR. | |
1687 | * Also RTS and DTR state should be preserved to restore | |
1688 | * it during startup(). | |
1689 | */ | |
1690 | static void pl011_disable_uart(struct uart_amba_port *uap) | |
1da177e4 | 1691 | { |
d8d8ffa4 | 1692 | unsigned int cr; |
1da177e4 | 1693 | |
3b43816f | 1694 | uap->autorts = false; |
fe433907 | 1695 | spin_lock_irq(&uap->port.lock); |
d8d8ffa4 SKS |
1696 | cr = readw(uap->port.membase + UART011_CR); |
1697 | uap->old_cr = cr; | |
1698 | cr &= UART011_CR_RTS | UART011_CR_DTR; | |
1699 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1700 | writew(cr, uap->port.membase + UART011_CR); | |
fe433907 | 1701 | spin_unlock_irq(&uap->port.lock); |
1da177e4 LT |
1702 | |
1703 | /* | |
1704 | * disable break condition and fifos | |
1705 | */ | |
ec489aa8 LW |
1706 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
1707 | if (uap->lcrh_rx != uap->lcrh_tx) | |
1708 | pl011_shutdown_channel(uap, uap->lcrh_tx); | |
95166a3f AP |
1709 | } |
1710 | ||
1711 | static void pl011_disable_interrupts(struct uart_amba_port *uap) | |
1712 | { | |
1713 | spin_lock_irq(&uap->port.lock); | |
1714 | ||
1715 | /* mask all interrupts and clear all pending ones */ | |
1716 | uap->im = 0; | |
1717 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1718 | writew(0xffff, uap->port.membase + UART011_ICR); | |
1719 | ||
1720 | spin_unlock_irq(&uap->port.lock); | |
1721 | } | |
1722 | ||
1723 | static void pl011_shutdown(struct uart_port *port) | |
1724 | { | |
1725 | struct uart_amba_port *uap = | |
1726 | container_of(port, struct uart_amba_port, port); | |
1727 | ||
1728 | pl011_disable_interrupts(uap); | |
1729 | ||
1730 | pl011_dma_shutdown(uap); | |
1731 | ||
1732 | free_irq(uap->port.irq, uap); | |
1733 | ||
1734 | pl011_disable_uart(uap); | |
1da177e4 LT |
1735 | |
1736 | /* | |
1737 | * Shut down the clock producer | |
1738 | */ | |
1c4c4394 | 1739 | clk_disable_unprepare(uap->clk); |
78d80c5a | 1740 | /* Optionally let pins go into sleep states */ |
2b996fc5 | 1741 | pinctrl_pm_select_sleep_state(port->dev); |
c16d51a3 | 1742 | |
574de559 | 1743 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
1744 | struct amba_pl011_data *plat; |
1745 | ||
574de559 | 1746 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
1747 | if (plat->exit) |
1748 | plat->exit(); | |
1749 | } | |
1750 | ||
36f339d1 PH |
1751 | if (uap->port.ops->flush_buffer) |
1752 | uap->port.ops->flush_buffer(port); | |
1da177e4 LT |
1753 | } |
1754 | ||
0dd1e247 AP |
1755 | static void sbsa_uart_shutdown(struct uart_port *port) |
1756 | { | |
1757 | struct uart_amba_port *uap = | |
1758 | container_of(port, struct uart_amba_port, port); | |
1759 | ||
1760 | pl011_disable_interrupts(uap); | |
1761 | ||
1762 | free_irq(uap->port.irq, uap); | |
1763 | ||
1764 | if (uap->port.ops->flush_buffer) | |
1765 | uap->port.ops->flush_buffer(port); | |
1766 | } | |
1767 | ||
ef5a9358 AP |
1768 | static void |
1769 | pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) | |
1770 | { | |
1771 | port->read_status_mask = UART011_DR_OE | 255; | |
1772 | if (termios->c_iflag & INPCK) | |
1773 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; | |
1774 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) | |
1775 | port->read_status_mask |= UART011_DR_BE; | |
1776 | ||
1777 | /* | |
1778 | * Characters to ignore | |
1779 | */ | |
1780 | port->ignore_status_mask = 0; | |
1781 | if (termios->c_iflag & IGNPAR) | |
1782 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; | |
1783 | if (termios->c_iflag & IGNBRK) { | |
1784 | port->ignore_status_mask |= UART011_DR_BE; | |
1785 | /* | |
1786 | * If we're ignoring parity and break indicators, | |
1787 | * ignore overruns too (for real raw support). | |
1788 | */ | |
1789 | if (termios->c_iflag & IGNPAR) | |
1790 | port->ignore_status_mask |= UART011_DR_OE; | |
1791 | } | |
1792 | ||
1793 | /* | |
1794 | * Ignore all characters if CREAD is not set. | |
1795 | */ | |
1796 | if ((termios->c_cflag & CREAD) == 0) | |
1797 | port->ignore_status_mask |= UART_DUMMY_DR_RX; | |
1798 | } | |
1799 | ||
1da177e4 | 1800 | static void |
606d099c AC |
1801 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1802 | struct ktermios *old) | |
1da177e4 | 1803 | { |
a5820c24 DT |
1804 | struct uart_amba_port *uap = |
1805 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1806 | unsigned int lcr_h, old_cr; |
1807 | unsigned long flags; | |
c19f12b5 RK |
1808 | unsigned int baud, quot, clkdiv; |
1809 | ||
1810 | if (uap->vendor->oversampling) | |
1811 | clkdiv = 8; | |
1812 | else | |
1813 | clkdiv = 16; | |
1da177e4 LT |
1814 | |
1815 | /* | |
1816 | * Ask the core to calculate the divisor for us. | |
1817 | */ | |
ac3e3fb4 | 1818 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1819 | port->uartclk / clkdiv); |
89fa28db | 1820 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1821 | /* |
1822 | * Adjust RX DMA polling rate with baud rate if not specified. | |
1823 | */ | |
1824 | if (uap->dmarx.auto_poll_rate) | |
1825 | uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); | |
89fa28db | 1826 | #endif |
ac3e3fb4 LW |
1827 | |
1828 | if (baud > port->uartclk/16) | |
1829 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1830 | else | |
1831 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1832 | |
1833 | switch (termios->c_cflag & CSIZE) { | |
1834 | case CS5: | |
1835 | lcr_h = UART01x_LCRH_WLEN_5; | |
1836 | break; | |
1837 | case CS6: | |
1838 | lcr_h = UART01x_LCRH_WLEN_6; | |
1839 | break; | |
1840 | case CS7: | |
1841 | lcr_h = UART01x_LCRH_WLEN_7; | |
1842 | break; | |
1843 | default: // CS8 | |
1844 | lcr_h = UART01x_LCRH_WLEN_8; | |
1845 | break; | |
1846 | } | |
1847 | if (termios->c_cflag & CSTOPB) | |
1848 | lcr_h |= UART01x_LCRH_STP2; | |
1849 | if (termios->c_cflag & PARENB) { | |
1850 | lcr_h |= UART01x_LCRH_PEN; | |
1851 | if (!(termios->c_cflag & PARODD)) | |
1852 | lcr_h |= UART01x_LCRH_EPS; | |
1853 | } | |
ffca2b11 | 1854 | if (uap->fifosize > 1) |
1da177e4 LT |
1855 | lcr_h |= UART01x_LCRH_FEN; |
1856 | ||
1857 | spin_lock_irqsave(&port->lock, flags); | |
1858 | ||
1859 | /* | |
1860 | * Update the per-port timeout. | |
1861 | */ | |
1862 | uart_update_timeout(port, termios->c_cflag, baud); | |
1863 | ||
ef5a9358 | 1864 | pl011_setup_status_masks(port, termios); |
1da177e4 LT |
1865 | |
1866 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1867 | pl011_enable_ms(port); | |
1868 | ||
1869 | /* first, disable everything */ | |
1870 | old_cr = readw(port->membase + UART011_CR); | |
1871 | writew(0, port->membase + UART011_CR); | |
1872 | ||
3b43816f RV |
1873 | if (termios->c_cflag & CRTSCTS) { |
1874 | if (old_cr & UART011_CR_RTS) | |
1875 | old_cr |= UART011_CR_RTSEN; | |
1876 | ||
1877 | old_cr |= UART011_CR_CTSEN; | |
1878 | uap->autorts = true; | |
1879 | } else { | |
1880 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1881 | uap->autorts = false; | |
1882 | } | |
1883 | ||
c19f12b5 RK |
1884 | if (uap->vendor->oversampling) { |
1885 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1886 | old_cr |= ST_UART011_CR_OVSFACT; |
1887 | else | |
1888 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1889 | } | |
1890 | ||
c5dd553b LW |
1891 | /* |
1892 | * Workaround for the ST Micro oversampling variants to | |
1893 | * increase the bitrate slightly, by lowering the divisor, | |
1894 | * to avoid delayed sampling of start bit at high speeds, | |
1895 | * else we see data corruption. | |
1896 | */ | |
1897 | if (uap->vendor->oversampling) { | |
1898 | if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) | |
1899 | quot -= 1; | |
1900 | else if ((baud > 3250000) && (quot > 2)) | |
1901 | quot -= 2; | |
1902 | } | |
1da177e4 LT |
1903 | /* Set baud rate */ |
1904 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
1905 | writew(quot >> 6, port->membase + UART011_IBRD); | |
1906 | ||
1907 | /* | |
1908 | * ----------v----------v----------v----------v----- | |
c5dd553b LW |
1909 | * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER |
1910 | * UART011_FBRD & UART011_IBRD. | |
1da177e4 LT |
1911 | * ----------^----------^----------^----------^----- |
1912 | */ | |
b60f2f66 | 1913 | pl011_write_lcr_h(uap, lcr_h); |
1da177e4 LT |
1914 | writew(old_cr, port->membase + UART011_CR); |
1915 | ||
1916 | spin_unlock_irqrestore(&port->lock, flags); | |
1917 | } | |
1918 | ||
0dd1e247 AP |
1919 | static void |
1920 | sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, | |
1921 | struct ktermios *old) | |
1922 | { | |
1923 | struct uart_amba_port *uap = | |
1924 | container_of(port, struct uart_amba_port, port); | |
1925 | unsigned long flags; | |
1926 | ||
1927 | tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); | |
1928 | ||
1929 | /* The SBSA UART only supports 8n1 without hardware flow control. */ | |
1930 | termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); | |
1931 | termios->c_cflag &= ~(CMSPAR | CRTSCTS); | |
1932 | termios->c_cflag |= CS8 | CLOCAL; | |
1933 | ||
1934 | spin_lock_irqsave(&port->lock, flags); | |
1935 | uart_update_timeout(port, CS8, uap->fixed_baud); | |
1936 | pl011_setup_status_masks(port, termios); | |
1937 | spin_unlock_irqrestore(&port->lock, flags); | |
1938 | } | |
1939 | ||
1da177e4 LT |
1940 | static const char *pl011_type(struct uart_port *port) |
1941 | { | |
a5820c24 DT |
1942 | struct uart_amba_port *uap = |
1943 | container_of(port, struct uart_amba_port, port); | |
e8a7ba86 | 1944 | return uap->port.type == PORT_AMBA ? uap->type : NULL; |
1da177e4 LT |
1945 | } |
1946 | ||
1947 | /* | |
1948 | * Release the memory region(s) being used by 'port' | |
1949 | */ | |
e643f87f | 1950 | static void pl011_release_port(struct uart_port *port) |
1da177e4 LT |
1951 | { |
1952 | release_mem_region(port->mapbase, SZ_4K); | |
1953 | } | |
1954 | ||
1955 | /* | |
1956 | * Request the memory region(s) being used by 'port' | |
1957 | */ | |
e643f87f | 1958 | static int pl011_request_port(struct uart_port *port) |
1da177e4 LT |
1959 | { |
1960 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
1961 | != NULL ? 0 : -EBUSY; | |
1962 | } | |
1963 | ||
1964 | /* | |
1965 | * Configure/autoconfigure the port. | |
1966 | */ | |
e643f87f | 1967 | static void pl011_config_port(struct uart_port *port, int flags) |
1da177e4 LT |
1968 | { |
1969 | if (flags & UART_CONFIG_TYPE) { | |
1970 | port->type = PORT_AMBA; | |
e643f87f | 1971 | pl011_request_port(port); |
1da177e4 LT |
1972 | } |
1973 | } | |
1974 | ||
1975 | /* | |
1976 | * verify the new serial_struct (for TIOCSSERIAL). | |
1977 | */ | |
e643f87f | 1978 | static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) |
1da177e4 LT |
1979 | { |
1980 | int ret = 0; | |
1981 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
1982 | ret = -EINVAL; | |
a62c4133 | 1983 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
1984 | ret = -EINVAL; |
1985 | if (ser->baud_base < 9600) | |
1986 | ret = -EINVAL; | |
1987 | return ret; | |
1988 | } | |
1989 | ||
1990 | static struct uart_ops amba_pl011_pops = { | |
e643f87f | 1991 | .tx_empty = pl011_tx_empty, |
1da177e4 | 1992 | .set_mctrl = pl011_set_mctrl, |
e643f87f | 1993 | .get_mctrl = pl011_get_mctrl, |
1da177e4 LT |
1994 | .stop_tx = pl011_stop_tx, |
1995 | .start_tx = pl011_start_tx, | |
1996 | .stop_rx = pl011_stop_rx, | |
1997 | .enable_ms = pl011_enable_ms, | |
1998 | .break_ctl = pl011_break_ctl, | |
1999 | .startup = pl011_startup, | |
2000 | .shutdown = pl011_shutdown, | |
68b65f73 | 2001 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
2002 | .set_termios = pl011_set_termios, |
2003 | .type = pl011_type, | |
e643f87f LW |
2004 | .release_port = pl011_release_port, |
2005 | .request_port = pl011_request_port, | |
2006 | .config_port = pl011_config_port, | |
2007 | .verify_port = pl011_verify_port, | |
84b5ae15 | 2008 | #ifdef CONFIG_CONSOLE_POLL |
b3564c2c | 2009 | .poll_init = pl011_hwinit, |
e643f87f LW |
2010 | .poll_get_char = pl011_get_poll_char, |
2011 | .poll_put_char = pl011_put_poll_char, | |
84b5ae15 | 2012 | #endif |
1da177e4 LT |
2013 | }; |
2014 | ||
0dd1e247 AP |
2015 | static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
2016 | { | |
2017 | } | |
2018 | ||
2019 | static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) | |
2020 | { | |
2021 | return 0; | |
2022 | } | |
2023 | ||
2024 | static const struct uart_ops sbsa_uart_pops = { | |
2025 | .tx_empty = pl011_tx_empty, | |
2026 | .set_mctrl = sbsa_uart_set_mctrl, | |
2027 | .get_mctrl = sbsa_uart_get_mctrl, | |
2028 | .stop_tx = pl011_stop_tx, | |
2029 | .start_tx = pl011_start_tx, | |
2030 | .stop_rx = pl011_stop_rx, | |
2031 | .startup = sbsa_uart_startup, | |
2032 | .shutdown = sbsa_uart_shutdown, | |
2033 | .set_termios = sbsa_uart_set_termios, | |
2034 | .type = pl011_type, | |
2035 | .release_port = pl011_release_port, | |
2036 | .request_port = pl011_request_port, | |
2037 | .config_port = pl011_config_port, | |
2038 | .verify_port = pl011_verify_port, | |
2039 | #ifdef CONFIG_CONSOLE_POLL | |
2040 | .poll_init = pl011_hwinit, | |
2041 | .poll_get_char = pl011_get_poll_char, | |
2042 | .poll_put_char = pl011_put_poll_char, | |
2043 | #endif | |
2044 | }; | |
2045 | ||
1da177e4 LT |
2046 | static struct uart_amba_port *amba_ports[UART_NR]; |
2047 | ||
2048 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
2049 | ||
d358788f | 2050 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 2051 | { |
a5820c24 DT |
2052 | struct uart_amba_port *uap = |
2053 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 2054 | |
d358788f RK |
2055 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
2056 | barrier(); | |
1da177e4 LT |
2057 | writew(ch, uap->port.membase + UART01x_DR); |
2058 | } | |
2059 | ||
2060 | static void | |
2061 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
2062 | { | |
2063 | struct uart_amba_port *uap = amba_ports[co->index]; | |
71eec483 | 2064 | unsigned int status, old_cr = 0, new_cr; |
ef605fdb RV |
2065 | unsigned long flags; |
2066 | int locked = 1; | |
1da177e4 LT |
2067 | |
2068 | clk_enable(uap->clk); | |
2069 | ||
ef605fdb RV |
2070 | local_irq_save(flags); |
2071 | if (uap->port.sysrq) | |
2072 | locked = 0; | |
2073 | else if (oops_in_progress) | |
2074 | locked = spin_trylock(&uap->port.lock); | |
2075 | else | |
2076 | spin_lock(&uap->port.lock); | |
2077 | ||
1da177e4 LT |
2078 | /* |
2079 | * First save the CR then disable the interrupts | |
2080 | */ | |
71eec483 AP |
2081 | if (!uap->vendor->always_enabled) { |
2082 | old_cr = readw(uap->port.membase + UART011_CR); | |
2083 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
2084 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
2085 | writew(new_cr, uap->port.membase + UART011_CR); | |
2086 | } | |
1da177e4 | 2087 | |
d358788f | 2088 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
2089 | |
2090 | /* | |
2091 | * Finally, wait for transmitter to become empty | |
2092 | * and restore the TCR | |
2093 | */ | |
2094 | do { | |
2095 | status = readw(uap->port.membase + UART01x_FR); | |
2096 | } while (status & UART01x_FR_BUSY); | |
71eec483 AP |
2097 | if (!uap->vendor->always_enabled) |
2098 | writew(old_cr, uap->port.membase + UART011_CR); | |
1da177e4 | 2099 | |
ef605fdb RV |
2100 | if (locked) |
2101 | spin_unlock(&uap->port.lock); | |
2102 | local_irq_restore(flags); | |
2103 | ||
1da177e4 LT |
2104 | clk_disable(uap->clk); |
2105 | } | |
2106 | ||
2107 | static void __init | |
2108 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
2109 | int *parity, int *bits) | |
2110 | { | |
2111 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
2112 | unsigned int lcr_h, ibrd, fbrd; | |
2113 | ||
ec489aa8 | 2114 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
2115 | |
2116 | *parity = 'n'; | |
2117 | if (lcr_h & UART01x_LCRH_PEN) { | |
2118 | if (lcr_h & UART01x_LCRH_EPS) | |
2119 | *parity = 'e'; | |
2120 | else | |
2121 | *parity = 'o'; | |
2122 | } | |
2123 | ||
2124 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
2125 | *bits = 7; | |
2126 | else | |
2127 | *bits = 8; | |
2128 | ||
2129 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
2130 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
2131 | ||
2132 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 2133 | |
c19f12b5 | 2134 | if (uap->vendor->oversampling) { |
ac3e3fb4 LW |
2135 | if (readw(uap->port.membase + UART011_CR) |
2136 | & ST_UART011_CR_OVSFACT) | |
2137 | *baud *= 2; | |
2138 | } | |
1da177e4 LT |
2139 | } |
2140 | } | |
2141 | ||
2142 | static int __init pl011_console_setup(struct console *co, char *options) | |
2143 | { | |
2144 | struct uart_amba_port *uap; | |
2145 | int baud = 38400; | |
2146 | int bits = 8; | |
2147 | int parity = 'n'; | |
2148 | int flow = 'n'; | |
4b4851c6 | 2149 | int ret; |
1da177e4 LT |
2150 | |
2151 | /* | |
2152 | * Check whether an invalid uart number has been specified, and | |
2153 | * if so, search for the first available port that does have | |
2154 | * console support. | |
2155 | */ | |
2156 | if (co->index >= UART_NR) | |
2157 | co->index = 0; | |
2158 | uap = amba_ports[co->index]; | |
d28122a5 RK |
2159 | if (!uap) |
2160 | return -ENODEV; | |
1da177e4 | 2161 | |
78d80c5a | 2162 | /* Allow pins to be muxed in and configured */ |
2b996fc5 | 2163 | pinctrl_pm_select_default_state(uap->port.dev); |
78d80c5a | 2164 | |
4b4851c6 RK |
2165 | ret = clk_prepare(uap->clk); |
2166 | if (ret) | |
2167 | return ret; | |
2168 | ||
574de559 | 2169 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
2170 | struct amba_pl011_data *plat; |
2171 | ||
574de559 | 2172 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
2173 | if (plat->init) |
2174 | plat->init(); | |
2175 | } | |
2176 | ||
1da177e4 LT |
2177 | uap->port.uartclk = clk_get_rate(uap->clk); |
2178 | ||
cefc2d1d AP |
2179 | if (uap->vendor->fixed_options) { |
2180 | baud = uap->fixed_baud; | |
2181 | } else { | |
2182 | if (options) | |
2183 | uart_parse_options(options, | |
2184 | &baud, &parity, &bits, &flow); | |
2185 | else | |
2186 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
2187 | } | |
1da177e4 LT |
2188 | |
2189 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
2190 | } | |
2191 | ||
2d93486c | 2192 | static struct uart_driver amba_reg; |
1da177e4 LT |
2193 | static struct console amba_console = { |
2194 | .name = "ttyAMA", | |
2195 | .write = pl011_console_write, | |
2196 | .device = uart_console_device, | |
2197 | .setup = pl011_console_setup, | |
2198 | .flags = CON_PRINTBUFFER, | |
2199 | .index = -1, | |
2200 | .data = &amba_reg, | |
2201 | }; | |
2202 | ||
2203 | #define AMBA_CONSOLE (&amba_console) | |
0d3c673e RH |
2204 | |
2205 | static void pl011_putc(struct uart_port *port, int c) | |
2206 | { | |
2207 | while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) | |
2208 | ; | |
2209 | writeb(c, port->membase + UART01x_DR); | |
2210 | while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) | |
2211 | ; | |
2212 | } | |
2213 | ||
2214 | static void pl011_early_write(struct console *con, const char *s, unsigned n) | |
2215 | { | |
2216 | struct earlycon_device *dev = con->data; | |
2217 | ||
2218 | uart_console_write(&dev->port, s, n, pl011_putc); | |
2219 | } | |
2220 | ||
2221 | static int __init pl011_early_console_setup(struct earlycon_device *device, | |
2222 | const char *opt) | |
2223 | { | |
2224 | if (!device->port.membase) | |
2225 | return -ENODEV; | |
2226 | ||
2227 | device->con->write = pl011_early_write; | |
2228 | return 0; | |
2229 | } | |
2230 | EARLYCON_DECLARE(pl011, pl011_early_console_setup); | |
45e0f0f5 | 2231 | OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); |
0d3c673e | 2232 | |
1da177e4 LT |
2233 | #else |
2234 | #define AMBA_CONSOLE NULL | |
2235 | #endif | |
2236 | ||
2237 | static struct uart_driver amba_reg = { | |
2238 | .owner = THIS_MODULE, | |
2239 | .driver_name = "ttyAMA", | |
2240 | .dev_name = "ttyAMA", | |
2241 | .major = SERIAL_AMBA_MAJOR, | |
2242 | .minor = SERIAL_AMBA_MINOR, | |
2243 | .nr = UART_NR, | |
2244 | .cons = AMBA_CONSOLE, | |
2245 | }; | |
2246 | ||
32614aad ML |
2247 | static int pl011_probe_dt_alias(int index, struct device *dev) |
2248 | { | |
2249 | struct device_node *np; | |
2250 | static bool seen_dev_with_alias = false; | |
2251 | static bool seen_dev_without_alias = false; | |
2252 | int ret = index; | |
2253 | ||
2254 | if (!IS_ENABLED(CONFIG_OF)) | |
2255 | return ret; | |
2256 | ||
2257 | np = dev->of_node; | |
2258 | if (!np) | |
2259 | return ret; | |
2260 | ||
2261 | ret = of_alias_get_id(np, "serial"); | |
2262 | if (IS_ERR_VALUE(ret)) { | |
2263 | seen_dev_without_alias = true; | |
2264 | ret = index; | |
2265 | } else { | |
2266 | seen_dev_with_alias = true; | |
2267 | if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { | |
2268 | dev_warn(dev, "requested serial port %d not available.\n", ret); | |
2269 | ret = index; | |
2270 | } | |
2271 | } | |
2272 | ||
2273 | if (seen_dev_with_alias && seen_dev_without_alias) | |
2274 | dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); | |
2275 | ||
2276 | return ret; | |
2277 | } | |
2278 | ||
49bb3c86 AP |
2279 | /* unregisters the driver also if no more ports are left */ |
2280 | static void pl011_unregister_port(struct uart_amba_port *uap) | |
2281 | { | |
2282 | int i; | |
2283 | bool busy = false; | |
2284 | ||
2285 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { | |
2286 | if (amba_ports[i] == uap) | |
2287 | amba_ports[i] = NULL; | |
2288 | else if (amba_ports[i]) | |
2289 | busy = true; | |
2290 | } | |
2291 | pl011_dma_remove(uap); | |
2292 | if (!busy) | |
2293 | uart_unregister_driver(&amba_reg); | |
2294 | } | |
2295 | ||
3873e2d7 | 2296 | static int pl011_find_free_port(void) |
1da177e4 | 2297 | { |
3873e2d7 | 2298 | int i; |
1da177e4 LT |
2299 | |
2300 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2301 | if (amba_ports[i] == NULL) | |
3873e2d7 | 2302 | return i; |
1da177e4 | 2303 | |
3873e2d7 AP |
2304 | return -EBUSY; |
2305 | } | |
1da177e4 | 2306 | |
3873e2d7 AP |
2307 | static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, |
2308 | struct resource *mmiobase, int index) | |
2309 | { | |
2310 | void __iomem *base; | |
32614aad | 2311 | |
3873e2d7 | 2312 | base = devm_ioremap_resource(dev, mmiobase); |
97a60eac KK |
2313 | if (IS_ERR(base)) |
2314 | return PTR_ERR(base); | |
1da177e4 | 2315 | |
3873e2d7 | 2316 | index = pl011_probe_dt_alias(index, dev); |
1da177e4 | 2317 | |
d8d8ffa4 | 2318 | uap->old_cr = 0; |
3873e2d7 AP |
2319 | uap->port.dev = dev; |
2320 | uap->port.mapbase = mmiobase->start; | |
1da177e4 LT |
2321 | uap->port.membase = base; |
2322 | uap->port.iotype = UPIO_MEM; | |
ffca2b11 | 2323 | uap->port.fifosize = uap->fifosize; |
1da177e4 | 2324 | uap->port.flags = UPF_BOOT_AUTOCONF; |
3873e2d7 | 2325 | uap->port.line = index; |
1da177e4 | 2326 | |
3873e2d7 | 2327 | amba_ports[index] = uap; |
c3d8b76f | 2328 | |
3873e2d7 AP |
2329 | return 0; |
2330 | } | |
e8a7ba86 | 2331 | |
3873e2d7 AP |
2332 | static int pl011_register_port(struct uart_amba_port *uap) |
2333 | { | |
2334 | int ret; | |
1da177e4 | 2335 | |
3873e2d7 AP |
2336 | /* Ensure interrupts from this UART are masked and cleared */ |
2337 | writew(0, uap->port.membase + UART011_IMSC); | |
2338 | writew(0xffff, uap->port.membase + UART011_ICR); | |
ef2889f7 TB |
2339 | |
2340 | if (!amba_reg.state) { | |
2341 | ret = uart_register_driver(&amba_reg); | |
2342 | if (ret < 0) { | |
3873e2d7 | 2343 | dev_err(uap->port.dev, |
1c9be310 | 2344 | "Failed to register AMBA-PL011 driver\n"); |
ef2889f7 TB |
2345 | return ret; |
2346 | } | |
2347 | } | |
2348 | ||
1da177e4 | 2349 | ret = uart_add_one_port(&amba_reg, &uap->port); |
49bb3c86 AP |
2350 | if (ret) |
2351 | pl011_unregister_port(uap); | |
7f6d942a | 2352 | |
1da177e4 LT |
2353 | return ret; |
2354 | } | |
2355 | ||
3873e2d7 AP |
2356 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
2357 | { | |
2358 | struct uart_amba_port *uap; | |
2359 | struct vendor_data *vendor = id->data; | |
2360 | int portnr, ret; | |
2361 | ||
2362 | portnr = pl011_find_free_port(); | |
2363 | if (portnr < 0) | |
2364 | return portnr; | |
2365 | ||
2366 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), | |
2367 | GFP_KERNEL); | |
2368 | if (!uap) | |
2369 | return -ENOMEM; | |
2370 | ||
2371 | uap->clk = devm_clk_get(&dev->dev, NULL); | |
2372 | if (IS_ERR(uap->clk)) | |
2373 | return PTR_ERR(uap->clk); | |
2374 | ||
2375 | uap->vendor = vendor; | |
2376 | uap->lcrh_rx = vendor->lcrh_rx; | |
2377 | uap->lcrh_tx = vendor->lcrh_tx; | |
2378 | uap->fifosize = vendor->get_fifosize(dev); | |
2379 | uap->port.irq = dev->irq[0]; | |
2380 | uap->port.ops = &amba_pl011_pops; | |
2381 | ||
2382 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); | |
2383 | ||
2384 | ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); | |
2385 | if (ret) | |
2386 | return ret; | |
2387 | ||
2388 | amba_set_drvdata(dev, uap); | |
2389 | ||
2390 | return pl011_register_port(uap); | |
2391 | } | |
2392 | ||
1da177e4 LT |
2393 | static int pl011_remove(struct amba_device *dev) |
2394 | { | |
2395 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1da177e4 | 2396 | |
1da177e4 | 2397 | uart_remove_one_port(&amba_reg, &uap->port); |
49bb3c86 | 2398 | pl011_unregister_port(uap); |
1da177e4 LT |
2399 | return 0; |
2400 | } | |
2401 | ||
d0ce850d UH |
2402 | #ifdef CONFIG_PM_SLEEP |
2403 | static int pl011_suspend(struct device *dev) | |
b736b89f | 2404 | { |
d0ce850d | 2405 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2406 | |
2407 | if (!uap) | |
2408 | return -EINVAL; | |
2409 | ||
2410 | return uart_suspend_port(&amba_reg, &uap->port); | |
2411 | } | |
2412 | ||
d0ce850d | 2413 | static int pl011_resume(struct device *dev) |
b736b89f | 2414 | { |
d0ce850d | 2415 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2416 | |
2417 | if (!uap) | |
2418 | return -EINVAL; | |
2419 | ||
2420 | return uart_resume_port(&amba_reg, &uap->port); | |
2421 | } | |
2422 | #endif | |
2423 | ||
d0ce850d UH |
2424 | static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); |
2425 | ||
0dd1e247 AP |
2426 | static int sbsa_uart_probe(struct platform_device *pdev) |
2427 | { | |
2428 | struct uart_amba_port *uap; | |
2429 | struct resource *r; | |
2430 | int portnr, ret; | |
2431 | int baudrate; | |
2432 | ||
2433 | /* | |
2434 | * Check the mandatory baud rate parameter in the DT node early | |
2435 | * so that we can easily exit with the error. | |
2436 | */ | |
2437 | if (pdev->dev.of_node) { | |
2438 | struct device_node *np = pdev->dev.of_node; | |
2439 | ||
2440 | ret = of_property_read_u32(np, "current-speed", &baudrate); | |
2441 | if (ret) | |
2442 | return ret; | |
2443 | } else { | |
2444 | baudrate = 115200; | |
2445 | } | |
2446 | ||
2447 | portnr = pl011_find_free_port(); | |
2448 | if (portnr < 0) | |
2449 | return portnr; | |
2450 | ||
2451 | uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), | |
2452 | GFP_KERNEL); | |
2453 | if (!uap) | |
2454 | return -ENOMEM; | |
2455 | ||
2456 | uap->vendor = &vendor_sbsa; | |
2457 | uap->fifosize = 32; | |
2458 | uap->port.irq = platform_get_irq(pdev, 0); | |
2459 | uap->port.ops = &sbsa_uart_pops; | |
2460 | uap->fixed_baud = baudrate; | |
2461 | ||
2462 | snprintf(uap->type, sizeof(uap->type), "SBSA"); | |
2463 | ||
2464 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2465 | ||
2466 | ret = pl011_setup_port(&pdev->dev, uap, r, portnr); | |
2467 | if (ret) | |
2468 | return ret; | |
2469 | ||
2470 | platform_set_drvdata(pdev, uap); | |
2471 | ||
2472 | return pl011_register_port(uap); | |
2473 | } | |
2474 | ||
2475 | static int sbsa_uart_remove(struct platform_device *pdev) | |
2476 | { | |
2477 | struct uart_amba_port *uap = platform_get_drvdata(pdev); | |
2478 | ||
2479 | uart_remove_one_port(&amba_reg, &uap->port); | |
2480 | pl011_unregister_port(uap); | |
2481 | return 0; | |
2482 | } | |
2483 | ||
2484 | static const struct of_device_id sbsa_uart_of_match[] = { | |
2485 | { .compatible = "arm,sbsa-uart", }, | |
2486 | {}, | |
2487 | }; | |
2488 | MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); | |
2489 | ||
3db9ab0b GG |
2490 | static const struct acpi_device_id sbsa_uart_acpi_match[] = { |
2491 | { "ARMH0011", 0 }, | |
2492 | {}, | |
2493 | }; | |
2494 | MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); | |
2495 | ||
0dd1e247 AP |
2496 | static struct platform_driver arm_sbsa_uart_platform_driver = { |
2497 | .probe = sbsa_uart_probe, | |
2498 | .remove = sbsa_uart_remove, | |
2499 | .driver = { | |
2500 | .name = "sbsa-uart", | |
2501 | .of_match_table = of_match_ptr(sbsa_uart_of_match), | |
3db9ab0b | 2502 | .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), |
0dd1e247 AP |
2503 | }, |
2504 | }; | |
2505 | ||
2c39c9e1 | 2506 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
2507 | { |
2508 | .id = 0x00041011, | |
2509 | .mask = 0x000fffff, | |
5926a295 AR |
2510 | .data = &vendor_arm, |
2511 | }, | |
2512 | { | |
2513 | .id = 0x00380802, | |
2514 | .mask = 0x00ffffff, | |
2515 | .data = &vendor_st, | |
1da177e4 LT |
2516 | }, |
2517 | { 0, 0 }, | |
2518 | }; | |
2519 | ||
60f7a33b DM |
2520 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
2521 | ||
1da177e4 LT |
2522 | static struct amba_driver pl011_driver = { |
2523 | .drv = { | |
2524 | .name = "uart-pl011", | |
d0ce850d | 2525 | .pm = &pl011_dev_pm_ops, |
1da177e4 LT |
2526 | }, |
2527 | .id_table = pl011_ids, | |
2528 | .probe = pl011_probe, | |
2529 | .remove = pl011_remove, | |
2530 | }; | |
2531 | ||
2532 | static int __init pl011_init(void) | |
2533 | { | |
1da177e4 LT |
2534 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); |
2535 | ||
0dd1e247 AP |
2536 | if (platform_driver_register(&arm_sbsa_uart_platform_driver)) |
2537 | pr_warn("could not register SBSA UART platform driver\n"); | |
ef2889f7 | 2538 | return amba_driver_register(&pl011_driver); |
1da177e4 LT |
2539 | } |
2540 | ||
2541 | static void __exit pl011_exit(void) | |
2542 | { | |
0dd1e247 | 2543 | platform_driver_unregister(&arm_sbsa_uart_platform_driver); |
1da177e4 | 2544 | amba_driver_unregister(&pl011_driver); |
1da177e4 LT |
2545 | } |
2546 | ||
4dd9e742 AR |
2547 | /* |
2548 | * While this can be a module, if builtin it's most likely the console | |
2549 | * So let's leave module_exit but move module_init to an earlier place | |
2550 | */ | |
2551 | arch_initcall(pl011_init); | |
1da177e4 LT |
2552 | module_exit(pl011_exit); |
2553 | ||
2554 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
2555 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
2556 | MODULE_LICENSE("GPL"); |